KR100892683B1 - Clock and data recovery circuit - Google Patents

Abstract

A clock and data recovery circuit is provided to respectively control a clock bandwidth for tracking data and a clock bandwidth for tracking jitter, thereby reducing time for tracking data and a real valid interval of data. A reference clock generating unit(100) receives an external clock to generate a reference clock. A data tracking unit(200) synchronizes an internal clock with data consecutively received in response to the reference clock generated from the external clock. An eye tracking unit(300) produces a plurality of sampling clocks for tracking eyes having different phase from the clock signal synchronized with the data. The plurality of sampling clocks for tracking eyes is controlled according to a digital code control signal to restore the data.

Description

Clock and Data Recovery Circuit

The present invention relates to a clock and data recovery circuit, and more particularly, to a clock and data recovery circuit for synchronizing data to a clock during data transmission.

In general, a signal transmission system transmits and receives data in the form of a binary digital signal using a clock signal. In this case, a timing skew problem occurs between a clock signal coming from the outside and a clock signal supplied to the inside. Therefore, it is difficult to accurately synchronize the data with the clock. In addition, the mismatch of multiple data transmission channels results in different arrival times of the received data. Thus, a clock and data recovery circuit (CDR) is provided to receive the recovered data in synchronization with the restored clock.

Phase-locked loops (hereinafter referred to as "PLLs") are widely used as the clock and data recovery circuits. Here, a phase-locked loop (PLL) refers to a device for locking a phase, and is a circuit for generating a restored clock by synchronizing a phase of an external clock. This PLL can be used to implement a data tracking loop circuit that synchronizes the phase of the data to the clock.

On the other hand, jitter may occur in the synchronized data. Thus, there may be a case where the jitter part of the data is mistaken for data. Thus, there is a need for a data eye tracking loop to find the actual valid interval of this synchronized data.

An object of the present invention is to provide a clock and data recovery circuit with improved bit error rate.

In order to achieve the technical object of the present invention, the clock and data recovery circuit according to an embodiment of the present invention, the data tracking unit for synchronizing the internal clock to the data continuously received in response to the reference clock generated from the external clock, And generating a plurality of eye tracking sampling clocks having different phases from the clock signal synchronized with the data, wherein the plurality of eye tracking sampling clocks are controlled according to a digital code control signal to restore the data. Include.

In order to achieve the technical object of the present invention, a clock and data recovery circuit according to another embodiment of the present invention, a reference clock generator for generating an external clock by receiving an external clock, delayed clock whose phase is adjusted from the reference clock A data tracking unit for synchronizing the data with the data, and generating a center clock signal using the delay clock to sample the data to generate reconstructed data, wherein the center clock signal includes an eye tracker controlled according to a digital code control signal. When the delayed clock is received, the sampling clock signal for interpolating the phase is generated to compensate for the operation time of the eye tracker.

According to an embodiment of the present invention, a loop operation is performed to synchronize data with respect to a reference clock using an analog voltage signal or a digital code during data transmission. In addition, the bit error rate (BER) can be improved by sampling the sampling data with a sampling clock signal always located at the center from both positions of the jitter. On the other hand, when generating a sampling clock that defines the effective period of the actual data, the jitter tracking clock can be independently controlled by digital code to track the jitter. Therefore, since the clock bandwidth for data tracking and the clock bandwidth for jitter tracking can be controlled, respectively, it is possible to reduce the time for tracking data and the actual valid period of data.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a conceptual block diagram of a clock and data recovery circuit according to an embodiment of the present invention. 2 is a detailed block diagram of the clock and data recovery circuit according to FIG. 1, and FIG. 3 is a detailed block diagram of the eye tracker 300 according to FIG. 1.

1 to 3, the clock and data recovery circuit includes a reference clock generator 100, a data tracker 200, and an eye tracker 300.

First, the reference clock generator 100 receives an external clock ECLK and generates a reference clock REFCLK. The reference clock REFCLK is a clock that becomes a reference for synchronizing the received data DATA. The reference clock generator 100 provides n reference clocks REFCLK having a 1 / n frequency of a bandwidth of the input data DATA and having a constant phase difference. In this example, the bandwidth of the input data DATA is 6.4 Gbps and eight reference clocks REFCLK are generated. Accordingly, the frequency of the reference clock REFCLK is 800 MHz, specifically, phases of 0 °, 45 °, 90 °, 135 °, 180 °, 225 °, 270 °, and 315 °. As a reference clock generator 100 according to an embodiment of the present invention, a PLL circuit is illustrated, but is not limited thereto.

The data tracking unit 200 according to an exemplary embodiment synchronizes the data DATA continuously received and the sampling clock signal ICLK for data tracking in an analog manner.

In more detail, the data tracker 200 includes a phase detector 210, a charge pump 220, a loop filter 230, a voltage controlled delay line 240, and a first phase interpolator 250.

The phase detector 210 outputs an up signal UP or a down signal DN by comparing the phase of the data tracking sampling clock ICLK at the timing of the transition of the received data DATA. That is, the phase detector 210 compares only the phase of the data DATA and the phase order of the data tracking sampling clock ICLK. For example, when the phase of the data DATA is ahead of the phase of the data tracking sampling clock ICLK, the up signal UP is provided. On the contrary, when the phase of the data tracking sampling clock ICLK is earlier than the phase of the data DATA, the down signal UP is provided. The satellite detector 210 may be any conventional phase detector.

The charge pump 220 provides a constant output voltage by pumping charges in response to the up signal UP and down signal DN.

In addition, the loop filter 230 filters the output voltage of the charge pump 220 to output a DC voltage from which high frequency components are removed. The loop filter 230 is illustrated with a typical low pass filter.

The voltage control delay line 240 is controlled by the output voltage of the loop filter 230 to delay the phase of the input reference clock REFCLK to generate the delay clock DCLK.

In particular, the first phase interpolator 250 receives the delay clock DCLK and generates a sampling clock ICLK for phase interpolation. The first phase interpolator 250 receives n delay clocks DCLK and generates 2n data tracking sampling clocks ICLK. Specifically, the delayed clock DCLK having a phase of adjacent 0 ° and 45 ° is received, and the sampling clock for data tracking ICLK having a phase of 0 ° and 45 ° and a sampling clock for data tracking having a phase of 22.5 ° are provided. Create one more. Similarly, create another sampling clock (ICLK) for data tracking with a phase of 67.5 ° between 45 ° and 90 °. For example, when the pattern of the data DATA is a NRZ (none return to zero) pattern, the sampling clock ICLK for tracking data having phases of 0 ° and 45 ° to track the transition position of the correct data DATA. Generate another sampling clock (ICLK) for data tracking with a phase of 22.5 ° in between. That is, if the transition timing of the data DATA is exactly 0 °, the operation is not completed here, but the phase clocks of 22.5 ° and -22.5 ° (or 337.5 °) are compared to track whether the data DATA transition position is correct. However, unlike the prior art, the first phase interpolator 250 is a kind of compensation that compensates the time for the data tracker 200 as much as the time delayed in the interpolation clock generator 330 which will be described later. It acts as a flicker. Thus, the timing of the sampling clocks of the data tracking unit 200 and the eye tracking unit 300 can be synchronized.

Here, the delay clock DCLK input to the first phase interpolator 250 receives a signal controlled by an analog voltage, and the sampling clock ICLK for data tracking output through the first phase interpolator 250 is fed back. It is fixed through a loop. As a result, the data tracking sampling clock ICLK for synchronizing the data DATA in the data tracking unit 200 is controlled in an analog manner to prevent the occurrence of phase jump and to release the finiteness of the phase resolution. You can.

This data tracking unit 200 is illustrated as having a first phase interpolator 250 in addition to the conventional DLL circuit.

The eye tracker 300 according to an embodiment of the present invention includes a sampler 310, an eye tracker 320, and an interpolation clock generator 330.

The sampler 310 generates reconstruction data REDATA by sampling the data DATA in response to the first jitter, the second jitter, and the center tracking clocks LCLK, RCLK, and CCLK, which are phase interpolated eye tracking clocks. Meanwhile, the sampler 310 always provides sampling data SDATA to the eye tracking controller 320.

The eye tracking control unit 320 determines whether jitter has occurred using the transition position of the sampled data SDATA, and detects the presence or absence of jitter from the first group and the second group control signals (a plurality of digital control signals). cont <0:11>, contb <0:11>). The eye tracking control unit 320 includes a jitter detector 321 and a code generator 322.

The jitter detector 321 detects the position of the transition of continuously received sampled data SDATA, integrates it into one unit interval UI, and detects jitter at both sides of the sampled data SDATA. And second location information (e1, e2). The code generator 322 receives the plurality of first group control signals cont <0:11> from the first position information e1 and the plurality of second group control signals contb <0 from the second position information e2. : 11>). Although not shown, such code generator 322 typically includes a shift register. Here, the first position information e1 detects left jitter information of the sampling data SDATA, and the second position information e2 detects right jitter information of the sampling data SDATA, but the present invention is not limited thereto. . That is, the jitter detector 321 may be provided if it provides jitter information when the jitter is detected. In addition, since the number of the first group control signal cont <0:11> and the second group control signal contb <0:11> is meaningful as a digital signal for adjusting the current, the clock signal to be controlled may be finely adjusted. The number of chords can vary as you adjust.

The interpolation clock generation unit 330 uses three adjacent delay clocks DCLK in response to the plurality of first and second group control signals cont <0:11> and contb <0:11> to form three mutually adjacent ones. A first jitter tracking clock signal LCLK, a second jitter tracking clock signal RCLK, and a center clock signal CCLK having different phases are provided. The interpolation clock generator 330 includes a first jitter tracking phase interpolator 332, a center tracking phase interpolator 334, and a second jitter tracking phase interpolator 336.

For example, the interpolation clock generator 330 may include a plurality of first and second group control signals cont <0:11> and contb <activated from delay clocks DCLK0 ° and DCLK45 ° having two adjacent phases. 0:11>) to generate clock signals with three different phases.

Specifically, when the delay clock DCLK receives a delay clock DCLK having a phase of adjacent 0 ° and 45 °, the first jitter tracking phase interpolator 332 generates an interpolation clock between 0 ° and 45 °. However, the first jitter tracking clock signal LCLK is generated to be earlier in phase than the center clock signal CCLK. Thus, the first jitter tracking clock signal LCLK may track until the left jitter of the sampled data SDATA is found. In addition, the second jitter tracking phase interpolator 336 generates an interpolation clock between 0 ° and 45 °, but generates a second jitter tracking clock signal RCLK whose phase is delayed from the center clock signal CCLK. . Thus, the second jitter tracking clock signal RCLK can track until it finds the right jitter of the sampled data. The center tracking clock generator 334 generates a center clock signal CCLK having a phase always positioned at the center of the first jitter tracking clock signal LCLK and the second jitter tracking clock signal RCLK. The center clock signal CCLK substantially becomes a sampling clock of the sampling data SDATA.

Accordingly, the eye tracker 300 generates a plurality of clock signals having different phases based on the delayed clock DCLK synchronized with the data DATA, but searches for a valid section of the sampling data SDATA. Can be controlled.

As such, according to an embodiment of the present invention, the reference clock REFCLK is used to synchronize the data DATA, and in response thereto, the center clock signal CCLK is generated using the delay clock DCLK. You can sample (SDATA). The center clock signal CCLK samples the sampling data SDATA at a stable position from the jitter position to restore the data. Therefore, since the reconstructed data REDATA according to an embodiment of the present invention is data sampled in an actual valid data interval, the bit error rate is improved. The bit error rate refers to the ratio of the number of error bits generated to the total number of bits of the transmitted data signal.

4 is a circuit diagram of the center tracking clock generator 334, and FIG. 5 is a diagram showing a phase relationship between clocks.

4 and 5, the center tracking clock generator 334 receives the delayed clock DCLK having two selected phases, thereby receiving the first and second group control signals cont <0:11> and contb <. Current is regulated in response to providing a phase adjusted center clock signal (CCLK, CCLKB).

The center tracking clock generator 334 includes NMOS transistor pairs N1-N2 and N3-N4, a first controller 334a, and a second controller 334b.

The NMOS transistor pairs N1-N2 and N3-N4 receive a delay clock DCLK having two selected phases and an inverted clock signal having a phase complementary to the selected phase.

The first controller 334a is turned on by receiving the first group control signal cont <0:11>. That is, the first controller 334a controls the phase of the clock signal output by adjusting the current in response to the number of activated first group control signals cont <0:11>. The amount of current flowing through the first control unit 334a is digitally controlled in accordance with each control signal. Since the frequency of the normal signal is proportional to the voltage, the phase of the clock signal may be adjusted in proportion to the output voltage.

The second controller 334b is turned on by receiving the second group control signal contb <0:11>. That is, the second controller 334b controls the phase of the clock signal to be output by adjusting the current in response to the number of activated second group control signals contb <0:11>.

Meanwhile, circuit diagrams of the first jitter tracking phase interpolator (see 332 of FIG. 3) and the second jitter tracking generator (see 336 of FIG. 2) are not illustrated. However, they differ from the center tracking clock generator 334 in that only the first group control signal cont <0:11> or the second group control signal contb <0:11> are applied.

In other words, the first jitter tracking clock generator (see 332 of FIG. 3) receives only the control of the first group control signal cont <0:11> with respect to the input delay clock DCLK, but the center clock signal ( Produces a signal with a phase earlier than CCLK). Thus, the first jitter tracking phase interpolator 332 generates the first jitter tracking clock signal LCLK to finely move and controls the left jitter of the data to be tracked. For example, if the first jitter tracking clock signal LCLK does not find the left jitter, it means that the first jitter tracking clock signal LCLK has a phase delayed from the left jitter, and thus the first group control signal cont <0: 11>) to reduce the number of signals so that a large voltage signal is output. If the first jitter tracking clock signal LCLK has already found the left jitter, the first jitter tracking clock generator 332 may activate the first group control signal cont <0:11 to find the jitter boundary. Increasing the number of &quot;) and generating a first jitter tracking clock signal LCLK having a phase delayed from the present time.

In the same way, the second jitter tracking clock generator (see 336 of FIG. 3) is configured to receive only the control of the second group control signal contb <0:11> with respect to the input delay clock DCLK, but the center clock signal. Control to have a signal with a delayed phase rather than (CCLK). Thus, the second jitter tracking phase interpolator 336 generates and finely moves the second jitter tracking clock signal RCLK and controls to track the right jitter of the data. Since the control method of the second jitter tracking clock generator (see 336 of FIG. 3) is similar to that of the first jitter tracking clock generator 332, redundant description thereof will be omitted.

Since the center tracking clock generator 334 is similar to the configuration of a conventional phase interpolator, it will be understood by those skilled in the art, so a detailed description of the configuration will be omitted and the characteristics of the operation will be described in detail.

An example is a case where data is sampled by a delay clock DCLK of 0 ° and 45 ° adjacent to each other.

4, the center tracking clock generator 334 receives a bias signal by a constant constant current power supply. The first NMOS transistor N1 and the second NMOS transistor N2 receive a phase of 0 ° and an inverted phase of 0 ° (or 180 °, see FIG. 4), and thus a delayed clock DCLK of 0 °. The first NMOS transistor N1 is turned on when the high level of. Similarly, the third NMOS transistor N3 and the fourth NMOS transistor N4 receive a phase of 45 ° and an inverted 45 ° phase (or 225 °, see FIG. 4), and thus a 45 ° delay clock ( The third NMOS transistor N3 is turned on when the high level of DCLK is received. In this case, the first control unit 334a and the first control unit responsive to the number of the first and second group control signals cont <0:11> and contb <0:11> provided from the eye tracking control unit 320 of FIG. 2. 2 The intensity of the current flowing to the control unit 334b varies. Accordingly, the center clock signal CCLK may be generated having a phase between 0 ° and 45 °, that is, between the first jitter tracking clock signal LCLK and the second jitter tracking clock signal RCLK in which jitter is considered. . As described above, the first and second group control signals cont <0:11> and contb <0:11> have both the first jitter tracking clock signal LCLK or the second jitter tracking clock signal RCLK. A signal with a value that has already been adjusted to track jitter. Therefore, the center clock signal CCLK controlled by the first and second group control signals cont <0:11> and contb <0:11> is the first and second jitter tracking clock signals LCLK and the second jitter. The interpolation phase is positioned at the center of the tracking clock signal RCLK.

As such, the eye tracker 300 of FIG. 2 generates the first jitter tracking and the second jitter tracking clock signals LCLK and RCLK to track jitter, and these signals are independent of each other. Can be controlled to track the location of the actual jitter. Therefore, the center clock signal CCLK generated by these two signals may be a sampling clock capable of sampling the actual valid period of data.

Also, the eye tracker 300 (see 300 in FIG. 2) receives and operates the delay clock DCLK from the data tracker (see 200 in FIG. 2), but does not form a feedback loop with each other. As in the exemplary embodiment of the present invention, the data tracking unit and the eye tracking unit do not form a feedback loop with each other, so that the clock frequency for tracking data and the clock frequency of the eye tracking unit may be independent of each other. In other words, the data tracker (see 200 in FIG. 2) forwards the delay clock DCLK to the eye tracker (see 300 in FIG. 2), and outputs the eye tracker (see 300 in FIG. 2). No feedback is given. Therefore, the clock bandwidth for synchronizing the data and the bandwidth of the clock signal for tracking the valid period of the data can be controlled independently of each other. For this reason, the time for restoring the data in synchronization with the clock can be reduced.

Meanwhile, although a plurality of first group and second group control signals cont <0:11> and contb <0:11> for controlling the center tracking clock generator 334 are illustrated, the present invention is not limited thereto. . That is, when the signal swing range of the center clock signal CCLK is limited, the plurality of first group and second group control signals cont <0:11> and contb <0:11> may be controlled. The number can be reduced.

6 is a diagram illustrating an eye tracking algorithm using a data eye to generate and find an interpolation clock to find a data valid period of sampling data SDATA according to FIG. 3.

The first experimental example (i) is a case where the first jitter tracking, center and second jitter tracking clock signals LCLK, CCLK, RCLK are located in the sampling data SDATA. Yet, since the first and second jitter tracking clock signals LCLK and RCLK have not found jitter, it is necessary to independently move the first and second jitter tracking clock signals LCLK and RCLK, respectively. Thus, the first jitter tracking clock signal LCLK is moved to the left until the jitter is found with the first group control signal (cont <0:11> in FIG. 2). Also, the second jitter tracking clock signal RCLK is moved to the right until the jitter is found by the second group control signal (contb <0:11> in FIG. 2). The center clock signal CCLK at this time is always located at the center of the data eye.

In the second experimental example (ii), the center and the second jitter tracking clock signals CCLK and RCLK are located in the sampling data SDATA, but only the first jitter tracking clock signal LCLK finds jitter. In this case, the first jitter tracking clock signal LCLK is moved to the right to move away from jitter and finds the jitter boundary. On the other hand, since the second jitter tracking clock signal RCLK has not yet found jitter, the second jitter tracking clock signal RCLK keeps moving to the right until the jitter is found to track the jitter. Thus, the eye tracking loop is repeated until the first jitter tracking clock signal LCLK and the second jitter tracking clock signal RCLK find and lock the boundary of the jitter.

In the third experimental example (iii), in contrast to the second embodiment, the second jitter tracking clock signal RCLK has already found jitter, and the first jitter tracking clock signal LCLK is required to keep track of the jitter. As described above, the eye tracking loop is repeated until both sides of the jitter are found and fixed, and the center clock signal CCLK is always the center of the first jitter tracking clock signal LCLK and the second jitter tracking clock signal RCLK. In this case, the sampling data SDATA may be sampled.

The fourth experimental example (iv) is a case where the first jitter tracking clock signal LCLK has already been fixed by finding the boundary of the jitter. In this case, only the second jitter tracking clock signal RCLK is tracked and fixed so as to find jitter, and as a result, the center clock signal CCLK which is always located at the center of the data eye may be generated.

7 is a block diagram of a data tracking unit 200 according to another embodiment of the present invention.

Referring to FIG. 7, the data tracking unit 200 according to another embodiment of the present invention digitally synchronizes the data DATA continuously received and the sampling clock signal ICLK for data tracking.

The data tracker 200 according to FIG. 7 includes a phase detector 21, a majority voting 260, a digital filter 270, a second phase interpolator 280, and a third phase interpolator 290. Include.

Since the phase detector 210 has the same configuration as the phase detector 210 in the above-described analog data tracking unit 200 (refer to 200 of FIG. 2), redundant description will be omitted. That is, the phase detector 210 outputs an up signal UP or a down signal DN by comparing the phase of the data tracking sampling clock ICLK at the timing of the transition of the received data DATA.

The majority voting unit 260 accumulates a predetermined amount of the up signal UP and the down signal DN and outputs the result as a 1-bit signal depending on whether the up signal UP or the down signal DN are large. Thus, the majority voter 260 provides a signal of '1' if there are more up signals UP, and a signal of '0' if there are more down signals DN. The majority voting unit 260 functions to correspond to the charge pump (see 220 in FIG. 2) in the analog data tracking unit (see 200 in FIG. 2).

The digital filter 270 continuously accumulates the output signals of the plurality of voters 260 and averages them, and outputs an average result of the up signal UP and the down signal DN as a 1-bit signal. The digital filter 270 functions to correspond to the loop filter (see 230 of FIG. 2) in the analog data tracking unit (see 200 of FIG. 2).

The second phase interpolator 280 is a digital phase interpolator controlled as an output signal of the digital filter 270, that is, a digital code. The second phase interpolator 280 is controlled as an output signal of the digital filter 270 to delay the phase of the input reference clock REFCLK to generate the delay clock DCLK.

Meanwhile, the third phase interpolator 290 receives the delay clock DCLK, generates a phase interpolated data tracking sampling clock ICLK, and feeds it back to the phase detector 210. The third phase interpolator 290 corresponds to the first phase interpolator (see 250 of FIG. 2) in the analog data tracking unit (see 200 of FIG. 2).

As described above, when transmitting and receiving data, a clock and recovery circuit may be provided to transmit data without skew of the clock signal. According to embodiments of the present invention, a loop operation is performed to synchronize the delay clock DCLK to data with respect to a reference clock using an analog voltage signal or a digital code. Meanwhile, the bit error rate (BER) can be improved by sampling the sampling data with a sampling clock signal located at the center from both positions of the jitter. As such, when generating a sampling clock defining an effective period of actual data, the jitter tracking clock may be independently controlled by a digital code to track the jitter. In the clock and data recovery circuit, a clock frequency for tracking data and a clock frequency of an eye tracker may be independent of each other. In other words, the clock bandwidth for synchronizing the data and the bandwidth of the clock signal for tracking the valid period of the data may be controlled independently of each other. For this reason, the time for restoring the data in synchronization with the clock can be reduced.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 and 2 are block diagrams of a clock and data recovery circuit in accordance with one embodiment of the present invention;

3 is a detailed block diagram of an eye tracker according to FIG. 2;

4 is a circuit diagram of a center tracking clock generator according to FIG. 3;

5 is a diagram illustrating a phase relationship between clocks in a circle;

6 is an experimental example showing the jitter tracking operation characteristic of the clock and data recovery circuit according to FIG. 2; and

7 is a block diagram of a data tracking unit according to another exemplary embodiment.

<Explanation of symbols for main parts of the drawings>

100: reference clock generation unit 200: data tracking unit

300: eye tracking unit 310: sampler

320: eye tracking control unit 330: interpolation clock generation unit

Claims (22)

 A data tracking unit configured to synchronize an internal clock with data continuously received in response to a reference clock generated from an external clock; And A plurality of eye tracking sampling clocks having different phases are generated from a clock signal synchronized with the data, wherein the plurality of eye tracking sampling clocks include an eye tracking unit for restoring the data by being controlled according to a digital code control signal. Clock and data recovery circuit. The method of claim 1, And the data tracking unit uses a voltage controlled delay line controlled by an analog voltage. The method of claim 2, The data tracking unit, A phase detector for comparing a phase of a sampling clock for tracking data and outputting an up signal or a down signal at the timing of transition of the received data; A charge pump providing a voltage by pumping charge in response to the up signal and the down signal; A loop filter for filtering the output voltage of the charge pump to remove high frequency components; The voltage controlled delay line configured to generate a delayed clock by adjusting a phase of the reference clock by being controlled by an output voltage of the loop filter; And And a first phase interpolator providing the data tracking sampling clock signal fed back to the phase detector by receiving the delayed clock and interpolating the phase. The method of claim 3, wherein And a delay clock which is an input signal of the first phase interpolator is phase locked through a feedback loop. The method of claim 1, And a data retrieval circuit using a digital code controlled phase interpolator. The method of claim 5, The data tracking unit, A phase detector for comparing a phase of a sampling clock for tracking data and outputting an up signal or a down signal at the timing of transition of the received data; A majority voting unit that receives the up signal and the down signal and selects a plurality of signals from the two signals and provides them as digital signals; A digital filter accumulating a predetermined amount of digital signals output from the plurality of voting machines and providing an average output signal as a digital signal; A second phase interpolator configured to generate a delayed clock by controlling a phase of the reference clock by being controlled by a digital signal provided from the digital filter; And And a third phase interpolator receiving the delay clock of the second phase interpolator and providing the phase interpolated sampling clock signal for phase tracking to the phase detector. The method of claim 6, And a delay clock which is an input signal of the third phase interpolator is phase locked through a feedback loop. The method of claim 3, wherein The eye tracking unit, An interpolation clock generator providing the eye tracking sampling clock having three phases different from each other in response to two adjacent delay clocks; A sampler that receives the eye tracking sampling clock having three phases different from each other and samples the data to generate reconstructed data and sampling data; And And an eye tracking control unit configured to determine whether jitter is generated using the transition position of the sampled data, and to provide first and second group control signals, which are a plurality of digital control signals, from the detected positional information on both sides of the jitter. Clock and data recovery circuit. The method of claim 8, The eye tracking sampling clock having three different phases includes a first jitter tracking clock signal, a center clock signal, and a second jitter tracking clock signal, which are sequentially delayed in phase. The interpolation clock generator, A first jitter tracking phase interpolator, controlled by the plurality of first group control signals, to generate the first jitter tracking clock signal using two adjacent delayed clocks; A center tracking phase interpolator, controlled by the plurality of first and second group control signals, to generate the center clock signal using the two adjacent delayed clocks; And  And a second jitter tracking phase interpolator, controlled by the plurality of second group control signals, to generate the second jitter tracking clock signal using the two adjacent delayed clocks. The method of claim 9, The first jitter tracking clock signal tracks one side jitter of the sampling data, and the second jitter tracking clock signal tracks the other side jitter of the sampling data. The method of claim 10, And the center clock signal has a phase always located at the center of the first jitter tracking clock signal and the second jitter tracking clock signal. The method of claim 8, The eye tracking control unit, A jitter detector which detects jitter at both sides of the continuously received sampling data and provides first and second location information, respectively; And And a code generator for providing the plurality of first group control signals from the first location information and for providing the plurality of second group control signals from the second location information. A reference clock generator configured to receive an external clock and generate a reference clock; A data tracking unit for synchronizing a delayed clock whose phase is adjusted from the reference clock with data continuously received; And A center clock signal is generated using the delay clock to sample the data to generate reconstructed data, wherein the center clock signal includes an eye tracker controlled according to a digital code control signal. A clock and data recovery circuit configured to compensate for the operation time of the eye tracker by generating a sampling clock signal for interpolating a phase when receiving the delayed clock. The method of claim 13, The data tracking unit, A phase detector for outputting an up signal or a down signal by comparing phases of the sampling clock for data tracking at a timing of transition of the received data; A charge pump providing a voltage by pumping charge in response to the up signal and the down signal; A loop filter for filtering the output voltage of the charge pump to remove high frequency components; A voltage controlled delay line configured to generate the delayed clock by adjusting a phase of the reference clock by being controlled by an output voltage of the loop filter; And And a first phase interpolator providing the data tracking sampling clock signal interpolated with the delayed clock to provide a feedback signal to the phase detector. And a replicator circuit for compensating for the operation time of the eye tracker by generating the sampling clock signal for data tracking. The method of claim 14, And a delay clock which is an input signal of the first phase interpolator is phase locked through a feedback loop. The method of claim 13, The data tracking unit, A phase detector for comparing a phase of a sampling clock for tracking data and outputting an up signal or a down signal at the timing of transition of the received data; A majority voting unit for receiving the up signal and the down signal and selecting a plurality of signals from the two signals and providing the signals as digital signals; A digital filter accumulating a predetermined amount of digital signals output from the plurality of voting machines and providing an average output signal as a digital signal; A second phase interpolator configured to generate a delayed clock by controlling a phase of the reference clock by being controlled by a digital signal provided from the digital filter; And And a third phase interpolator receiving the delay clock of the second phase interpolator and providing the phase interpolated feedback data sampling clock signal to the phase detector. And the third phase interpolator is a replicator circuit that compensates for the operation time of the eye tracker by generating the data tracking sampling clock signal having the phase interpolated upon receiving the delay clock. The method of claim 16, And a delay clock which is an input signal of the third phase interpolator is phase locked through a feedback loop. The method of claim 13, The eye tracking unit, An interpolation clock generator providing an eye tracking sampling clock having three phases different from each other in response to two adjacent delay clocks; A sampler configured to receive the eye tracking sampling clock having three phases different from each other and sample the data to generate the reconstructed data and the sampling data; And And an eye tracking control unit configured to determine whether jitter is generated using the transition position of the sampled data, and to provide first and second group control signals, which are a plurality of digital control signals, from the detected position information of both jitters. Clock and data recovery circuit. The method of claim 18, The eye tracking sampling clock having three different phases includes a first jitter tracking clock signal, a center clock signal, and a second jitter tracking clock signal, which are sequentially delayed in phase, The interpolation clock generator, A first jitter tracking phase interpolator, controlled by the plurality of first group control signals, to generate the first jitter tracking clock signal using two adjacent delayed clocks; A center tracking phase interpolator, controlled by the plurality of first and second group control signals, to generate the center clock signal using the two adjacent delayed clocks; And  And a second jitter tracking phase interpolator, controlled by the plurality of second group control signals, to generate the second jitter tracking clock signal using the two adjacent delayed clocks. The method of claim 19, The first jitter tracking clock signal tracks one side jitter of the sampling data, and the second jitter tracking clock signal tracks the other side jitter of the sampling data. The method of claim 19, And the center clock signal has a phase located at the center of the first jitter tracking clock signal and the second jitter tracking clock signal. The method of claim 18, The eye tracking control unit, A jitter detector which detects jitter at both sides of the continuously received sampling data and provides first and second location information, respectively; And And a code generator for providing the plurality of first group control signals from the first location information and for providing the plurality of second group control signals from the second location information.

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