KR100890383B1 - Semiconductor device and method for fabricating the same - Google Patents

Abstract

The present invention relates to a semiconductor device capable of alleviating Hot Electron Induced Punch Through (HEIP) without using a gate tap, and a method of manufacturing the same. A substrate provided with an area; A punch-through prevention film covering the device isolation region on the substrate and both ends of which extend to edges of the active region; A gate insulating film formed on the substrate of the active region exposed by the punch-through prevention film and a gate electrode formed on the gate insulating film. According to the present invention described above, the HEIP phenomenon is prevented without using a gate tab. can do.

Gate Tap, Tap, HEIP

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device capable of alleviating Hot Electron Induced Punch through (HEIP) without using a gate tap and a method of manufacturing the same. .

As the integration of semiconductor devices, for example, DRAM (Dynamic Random Access Memory) devices, has been rapidly progressed, the pattern for realizing the devices has been further refined. Due to the high integration of the semiconductor device, the gate length of the transistor, that is, the line width of the gate line is getting smaller, but the reliability of the transistor is required to be maintained at least the same.

In the case of PMOS transistors, as the gate length decreases, hot electron induced punch through (HIP) phenomenon occurs due to hot electrons generated at the edges of the active region in contact with the device isolation region. It becomes a factor which degrades the electrical characteristic of a jistor.

FIG. 1A is a plan view of a semiconductor device according to the prior art, and FIG. 1B is a cross-sectional view of the semiconductor device according to the prior art along the line II ′ and the II-II ′ of FIG. 1A.

As shown in FIGS. 1A and 1B, an isolation region 12 is formed on a semiconductor substrate 11 through a shallow trench isolation (STI) process to define an active region 13. In this case, the device isolation region 12 may include a liner nitride layer. Next, a gate insulating film 14 is formed on the semiconductor substrate 11. Next, after the gate electrode 15, that is, the gate line is formed on the gate insulating film 14, the source and drain regions 17 are formed in the active regions on both sides of the gate electrode 15.

Here, when driving a PMOS transistor device, hot electrons having energy above average are generated due to the high electric field applied to the channel region 18, and the generated hot electrons collide with atoms in the semiconductor substrate 11 to ionize the atoms. EHP (Electron-Hole Pair) is generated. At this time, since the hot electrons generated by the EHP have high energy above the average, they penetrate through the gate insulating film 14 and are trapped in the gate insulating film 14, or penetrate through the device isolation region 12 to penetrate the sidewall oxide film ( HEIP phenomenon occurs as it is trapped in the liner nitride film (not shown) or (not shown). At this time, a leakage current occurs due to the HEIP phenomenon. This leakage current flows along the interface between the gate electrode 15 and the active region 13 below it, which causes the channel length to decrease. That is, the length of the channel region formed on the interface between the gate electrode 15 and the active region 10A below it is physically the same, but shorter electrically.

In order to solve this problem, recently, a gate tap for increasing the gate length at the edge of the active region has been applied.

2 is a plan view illustrating a semiconductor device according to the related art to which a gate tab is applied.

As shown in FIG. 2, the gate tab 16 is formed in the gate electrode 15 positioned at the edge of the active region 13 to increase the length of the gate electrode 15 in this portion. As a result, the length L ₂ of the channel formed at the edge of the active region 13 where the HEIP phenomenon is mainly generated becomes longer than the length L ₁ of the channel formed at the center, thereby alleviating the HEIP phenomenon.

However, as device integration increases, the length of the channel decreases, so that the length of the gate tap 16 must be increased to compensate for the decrease in the channel length, in which case the area where the transistors requiring the gate tap 16 are densely packed. In this case, since the active region 13 needs to be increased to maintain a constant distance between the gate electrodes 15, the circuit area becomes large. Therefore, there is a problem that it is difficult to improve the degree of integration of the semiconductor device.

The present invention has been proposed to solve the problems of the prior art, and an object thereof is to provide a semiconductor device and a method of manufacturing the same, which can prevent the HEIP phenomenon without using a gate tab.

According to an aspect of the present invention, a semiconductor device includes a substrate having an isolation region and an active region; A punch-through prevention film covering the device isolation region on the substrate and both ends of which extend to edges of the active region; And a gate insulating film formed on the remaining substrate exposed by the punch-through prevention film and a gate electrode formed on the gate insulating film. In this case, the punch-through prevention film may be any one selected from the group consisting of an oxide film series, a nitride film series, a carbon-containing film, and an oxynitride, wherein the carbon-containing film is an amorphous carbon layer (ACL) or a carbon rich polymer. Membrane (Carbon Rich Polymer).

The gate electrode may be connected to the first gate conductive layer and the first gate conductive layer formed on the gate insulating layer to have the same height as that of the punchthrough prevention layer, and the second gate conductive layer formed on the punchthrough prevention layer. It may include. In this case, the first gate conductive film may be a polysilicon film, and the second gate conductive film may be a polysilicon film or a tungsten-containing film. The tungsten-containing film may be a tungsten film or a tungsten silicide film.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, which includes punching through the device isolation region on both sides of the substrate including the device isolation region and the active region, and both ends of which extend to the edge of the active region. Forming a protective film; Forming a gate insulating film on the substrate of the remaining active region exposed by the punch-through prevention film, and forming a gate electrode on the gate insulating film.

The forming of the punch through prevention film may include forming an insulating film for punch through prevention film on the substrate; Forming a photoresist pattern covering the device isolation region on both sides of the insulating film for punch-through prevention layer, and both ends of which extend to the edge of the active region, and etching the insulating film for punch-through prevention layer using the photoresist pattern as an etch barrier It may include. In this case, the punch-through prevention film may be formed of any one selected from the group consisting of an oxide film series, a nitride film series, a carbon-containing film, and a nitride oxide film, and the carbon-containing film may be formed of an amorphous carbon film or a carbon rich polymer film.

 The forming of the gate electrode may include forming a first gate conductive film on an entire surface including the gate insulating film; And planarizing the first gate conductive layer to expose the surface of the punchthrough prevention layer, and forming a second gate conductive layer connected to the first gate conductive layer on the punchthrough prevention layer. In this case, the first gate conductive film may be formed of a polysilicon film, and the second gate conductive film may be formed of any one of a polysilicon film or a tungsten-containing film. The tungsten-containing film may be formed of any one of a tungsten film and a tungsten silicide film.

The planarization may use a chemical mechanical polishing (CMP) or etch back process.

The present invention forms a punch-through prevention film covering the device isolation region and both ends of which extend to the edge of the active region so that the interface between the device isolation region and the active region where the HEIP phenomenon occurs is not electrically used, so that no gate tab is used. There is an effect that can mitigate HEIP phenomenon without. In addition, the manufacturing cost can be reduced by simplifying the process, and the integration degree of the semiconductor device can be improved by overcoming the difficulty of integration due to the gate tap. In addition, since the gate tab is not formed, an increase in the circuit area due to the integration of the semiconductor device can be prevented, and a gate line having the same shape as that of adjacent peripheral transistors can be formed, thereby achieving an unified layout.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

3 is a cross-sectional view of a semiconductor device according to a preferred embodiment of the present invention taken along the line II ′ shown in FIG. 1A.

As shown in FIG. 3, the semiconductor device of the present invention covers the device isolation region 22 and the substrate 21 having the active region 23, the device isolation region 22 on the substrate 21, and both ends thereof. The punch-through prevention film 24 extending to the edge of the active region 23 and the gate insulating film 25 formed on the substrate 21 of the remaining active region 23 exposed by the punch-through prevention film 24. And a gate electrode formed on the gate insulating film 25.

The punch-through prevention film 24 may be any one selected from the group consisting of an oxide film series, a nitride film series, a carbon-containing film, and an oxynitride. For example, the oxide layer may be a silicon oxide film (SiO ₂ ), boron phosphorus silicate glass (BPSG), phosphorus silicalicate glass (PSG), tetra ethoxy ortho silicate (TEOS), un-doped silicate glass (USG), or spin on glass (SOG). , Any one selected from the group consisting of High Density Plasma (HDP) and Spin On Dielectric (SOD) can be used, Si ₃ N ₄ can be used as the nitride film series, amorphous carbon film as the carbon-containing film Amorphous Carbon Layer (ACL) or Carbon Rich Polymer may be used.

The gate electrode is connected to the first gate conductive film 26 and the first gate conductive film 26 formed on the gate insulating film 25 to have the same height as the punch-through prevention film 24 and the punch-through prevention film 24. ) May include a second gate conductive layer 27. Although not shown in the drawings, the gate hard mask layer formed on the second gate conductive layer 27 may be further included. In this case, the first gate conductive layer 26 may be a polysilicon layer, and the second gate conductive layer 27 may be a polysilicon layer or a tungsten-containing layer. The tungsten-containing film may be a tungsten film or a tungsten silicide film.

As described above, the present invention forms a punch-through prevention film covering the device isolation region and both ends of which extend to the edge of the active region so that the interface between the device isolation region and the active region where the HEIP phenomenon occurs is not electrically used. HEIP can be alleviated without using. In addition, the manufacturing cost can be reduced by simplifying the process, and the degree of integration can be improved by overcoming the difficulty of integrating the semiconductor device due to the gate tap. In addition, since the gate tab is not formed, an increase in the circuit area due to the integration of semiconductor devices can be prevented, and gate lines having the same shape as that of adjacent peripheral transistors can be formed.

4A through 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention, taken along the line II ′ shown in FIG. 1A.

As shown in FIG. 4A, after the trench is formed in a predetermined region of the semiconductor substrate 21, the device isolation region 22 is formed by filling the trench with an insulating film, for example, a high density plasma (HDP) oxide film to form an isolation layer. ). In this case, in order to protect the surface of the trench, the trench may be formed of an isolation layer including a liner nitride layer. For example, in the device isolation layer including a liner nitride layer, a pad oxide layer (not shown) and a pad nitride layer (not shown) are deposited on the semiconductor substrate 21, and trenches are formed through a device isolation mask process and an etching process. A sidewall oxide film (not shown), a liner nitride film (not shown), and a liner oxide film (not shown) are sequentially formed on the surface thereof. Next, the gap inside the trench is filled using a high density plasma (HDP) insulating film, and then annealed to improve the strength of the HDP insulating film. Subsequently, it may be formed through a series of processes of planarizing through chemical mechanical polishing (CMP) process until the surface of the pad nitride film is exposed, and then removing the pad nitride film and the pad oxide film.

Here, an area other than the device isolation region 22 is formed in the semiconductor substrate 21 is defined as the active region 23.

Next, an insulating film for punch-through prevention film is formed over the entire semiconductor substrate 21. In this case, the insulating film for punch-through prevention film may be formed of any one selected from the group consisting of an oxide film series, a nitride film series, an oxynitride, and a carbon-containing film. For example, the oxide layer may be a silicon oxide film (SiO ₂ ), boron phosphorus silicate glass (BPSG), phosphorus silicalicate glass (PSG), tetra ethoxy ortho silicate (TEOS), un-doped silicate glass (USG), or spin on glass (SOG). , Any one selected from the group consisting of High Density Plasma (HDP) and Spin On Dielectric (SOD) can be used, Si ₃ N ₄ can be used as the nitride film series, amorphous carbon film as the carbon-containing film Amorphous Carbon Layer (ACL) or Carbon Rich Polymer may be used.

Next, the photoresist pattern 28 is formed on the insulating film for punch-through prevention film, and both ends thereof extend to the edge of the active region 23, and then the photoresist pattern 28 is etched. The punch-through prevention film 24 is etched by using an etch barrier to form the punch-through prevention film 24.

As shown in FIG. 4B, the gate insulating layer 25 is formed on the semiconductor substrate 21 of the remaining active region 23 having the surface exposed due to the punch-through prevention layer 24. In this case, the gate insulating layer 25 may be formed of a silicon oxide layer (SiO ₂ ) by thermal oxidation.

Next, the first gate conductive layer 26 is deposited on the entire surface including the gate insulating layer 25. In this case, the first gate conductive layer 26 may be formed of the gate insulating layer 25, for example, a polysilicon layer having excellent interface characteristics with the silicon oxide layer.

Next, the first gate conductive film 26 is planarized so that the surface of the punch-through prevention film 24 is exposed. In this case, the planarization process may use a chemical mechanical polishing (CMP) or etchback process.

As shown in FIG. 4C, the second gate conductive layer 27 is formed on the punch-through prevention layer 24 to be connected to the first gate conductive layer 26. In this case, the second gate conductive layer 27 may be formed of a polysilicon layer or a tungsten-containing layer, and the tungsten-containing layer may be formed of any one of tungsten silicide (WSi _x ) or tungsten layer (W).

Next, although not shown in the drawing, after the gate hard mask film is formed on the second gate conductive film 27, the gate hard mask film, the second gate conductive film 27, and the insulating film 24 are selectively selected. The gate line may be formed by etching.

Next, although not shown in the figure, a transistor may be completed by forming source and drain regions in the semiconductor substrate 21 of the active region 23 on both sides of the gate line.

As such, the present invention forms a punch-through prevention film covering the device isolation region and both ends extending to the edge of the active region so that the gate tab is not electrically used between the device isolation region and the active region where the HEIP phenomenon occurs. It is possible to alleviate the HEIP phenomenon without forming a. In addition, this can simplify the manufacturing process of the semiconductor device, it is possible to reduce the manufacturing cost. In addition, since the HEIP phenomenon can be alleviated without forming a gate tab, an increase in circuit area due to integration of semiconductor devices can be prevented, and gate lines having the same shape as adjacent peripheral transistors can be formed, thereby unifying layout. It can be done.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

Figure 1a is a plan view showing a semiconductor device according to the prior art

1B is a cross-sectional view of a semiconductor device according to the prior art along the lines II ′ and II-II ′ of FIG. 1A;

2 is a plan view illustrating a semiconductor device according to the related art to which a gate tab is applied.

3 is a cross-sectional view of a semiconductor device according to a preferred embodiment of the present invention taken along the line II ′ shown in FIG. 1A.

4A through 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention, taken along the line II ′ shown in FIG. 1A.

* Description of symbols on the main parts of the drawings *

21 substrate 22 device isolation region

23: active area 24: punch-through prevention film

26 gate insulating film 26 first gate conductive film

27: second gate conductive film 28: photosensitive film pattern

Claims (16)

A substrate having an isolation region and an active region; A punch-through prevention film covering the device isolation region on the substrate and both ends of which extend to edges of the active region; A gate insulating film formed on the substrate of the remaining active region exposed by the punch-through prevention film; And A gate electrode formed on the gate insulating layer Semiconductor device comprising a. The method of claim 1, The punch-through prevention film is any one selected from the group consisting of an oxide film series, a nitride film series, a carbon-containing film and an oxynitride. The method of claim 2, The carbon-containing film includes an amorphous carbon film (Amorphous Carbon Layer, ACL) or a carbon rich polymer film (Carbon Rich Polymer). The method of claim 1, The gate electrode, A first gate conductive film formed on the gate insulating film such that the punch-through prevention film has the same height as a surface thereof; And A second gate conductive layer connected to the first gate conductive layer and formed on the punch-through prevention layer Semiconductor device comprising a. The method of claim 4, wherein The first gate conductive layer includes a polysilicon layer. The method of claim 4, wherein The second gate conductive film includes a polysilicon film or a tungsten-containing film. The method of claim 6, The tungsten-containing film includes a tungsten film or a tungsten silicide film. Forming a punch-through prevention film covering the device isolation region on the substrate including the device isolation region and the active region and extending at both ends to an edge of the active region; Forming a gate insulating film on the substrate of the remaining active region exposed by the punch-through prevention film; And Forming a gate electrode on the gate insulating layer Method of manufacturing a semiconductor device comprising a. The method of claim 8, Forming the punch-through prevention film, Forming an insulating film for a punchthrough prevention film on the substrate; Forming a photoresist pattern covering the device isolation region on the insulating film for punch-through prevention layer, the both ends of which extend to an edge of the active region; And Etching the insulating film for punch-through prevention layer using the photoresist pattern as an etch barrier Method of manufacturing a semiconductor device comprising a. The method according to claim 8, wherein The punch-through prevention film is a semiconductor device manufacturing method of any one selected from the group consisting of oxide film series, nitride film series, carbon containing film and nitride oxide film. The method of claim 10, The carbon-containing film is a semiconductor device manufacturing method formed of any one of an amorphous carbon film or a carbon rich polymer film. The method of claim 8, Forming the gate electrode, Forming a first gate conductive film on the entire surface including the gate insulating film; Planarizing the first gate conductive film to expose a surface of the punch-through prevention film; And Forming a second gate conductive layer on the punch-through prevention layer, the second gate conductive layer being connected to the first gate conductive layer Method of manufacturing a semiconductor device comprising a. The method of claim 12, The first gate conductive film is formed of a polysilicon film. The method of claim 12, And the second gate conductive film is formed of any one of a polysilicon film and a tungsten-containing film. The method of claim 14, The tungsten-containing film is a semiconductor device manufacturing method formed of any one of a tungsten film or tungsten silicide film. The method of claim 12, The planarization method of manufacturing a semiconductor device using a chemical mechanical polishing (CMP) or etch back process.

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