KR100886075B1 - 방송 시스템에서 복수의 정보 비트를 포함한 데이터를인코딩하는데 이용되는 저밀도 패리티 검사 코드를설계하기 위한 방법 및 시스템 - Google Patents
방송 시스템에서 복수의 정보 비트를 포함한 데이터를인코딩하는데 이용되는 저밀도 패리티 검사 코드를설계하기 위한 방법 및 시스템 Download PDFInfo
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
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- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
- H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
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- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
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- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
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- H04L1/0047—Decoding adapted to other signal detection operation
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- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
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- H04L1/02—Arrangements for detecting or preventing errors in the information received by diversity reception
- H04L1/06—Arrangements for detecting or preventing errors in the information received by diversity reception using space diversity
- H04L1/0618—Space-time coding
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- H04L1/00—Arrangements for detecting or preventing errors in the information received
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- H04L1/06—Arrangements for detecting or preventing errors in the information received by diversity reception using space diversity
- H04L1/0618—Space-time coding
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- H04L1/0643—Properties of the code block codes
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
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- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
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Abstract
Description
Claims (20)
- 방송 시스템에서 복수의 정보 비트를 포함한 데이터를 코딩하는데 이용되는 저밀도 패리티 검사(Low Density Parity Check; LDPC) 코드를 설계하기 위한 시스템으로서,복수의 병렬 누산 엔진 - 상기 복수의 병렬 누산 엔진의 개수는 M과 같음 - ; 및패리티 비트 검사 행렬을 포함하고, 상기 패리티 비트 검사 행렬에서,상기 복수의 병렬 누산 엔진을 이용하여 제1 특정 패리티 비트 어드레스 집합에서 제1 정보 비트가 누산되고,각각의 새로운 정보 비트마다 상기 제1 특정 패리티 비트 어드레스 집합의 각각의 원소에 대한 패리티 비트 어드레스가 소정의 오프셋만큼 증가하고,M+1 정보 비트에 도달할 때까지 상기 소정의 오프셋만큼 상기 특정 패리티 비트 어드레스로부터 오프셋되는 패리티 비트 어드레스에서 후속 정보 비트가 누산되고,상기 복수의 병렬 누산 엔진을 이용하여 다음 M개의 정보 비트가 제2 특정 패리티 비트 어드레스 집합에서 누산되고, 각각의 새로운 정보 비트마다 상기 제2 특정 패리티 비트 어드레스 집합의 각각의 원소에 대한 패리티 비트 어드레스가 상기 소정의 오프셋만큼 증가하고,상기 복수의 정보 비트 내의 모든 정보 비트가 누산될 때까지 추가 특정 패리티 비트 어드레스 집합과 소정의 오프셋을 이용하여 상기 복수의 정보 비트 내의 각각의 정보 비트가 누산되는 방송 시스템에서 복수의 정보 비트를 포함한 데이터를 코딩하는데 이용되는 저밀도 패리티 검사 코드를 설계하기 위한 시스템.
- 제1항에 있어서,상기 LDPC 코드는 다중입력 다중출력(Multiple-Input, Multiple-Output; MIMO) 시스템에서 이용되는 시스템.
- 제2항에 있어서,상기 소정의 오프셋은 코드-의존형(code-dependent)인 시스템.
- 제3항에 있어서,각각의 패리티 비트 어드레스의 패리티 비트를 바로 이전 패리티 비트 어드레스의 패리티 비트에 더함으로써 상기 패리티 비트를 누산하기 위한 패리티 비트 누산기를 더 포함하는 시스템.
- 제4항에 있어서,상기 LDPC 코드는 LDPC 인코더에서 이용되는 시스템.
- 제5항에 있어서,상기 M은 400인 시스템.
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- 복수의 정보 비트를 포함한 데이터를 인코딩하는데 이용되는 저밀도 패리티 검사(Low Density Parity Check; LDPC) 코드를 설계하기 위한 방법으로서,a) 복수의 병렬 누산 엔진을 이용하여 제1 특정 패리티 비트 어드레스 집합에서 제1 정보 비트를 누산하는 단계;b) 각각의 새로운 정보 비트마다 상기 제1 특정 패리티 비트 어드레스 집합의 각각의 원소에 대한 패리티 비트 어드레스를 소정의 오프셋만큼 증가시키는 단계;c) 상기 복수의 병렬 누산 엔진의 개수와 같은 인덱스 번호를 갖는 정보 비트에 도달할 때까지 소정의 오프셋만큼 상기 특정 패리티 비트 어드레스로부터 오프셋되는 패리티 비트 어드레스에서 후속 정보 비트를 누산하는 단계;d) 상기 복수의 병렬 누산 엔진을 이용하여 제2 특정 패리티 비트 어드레스 집합에서 다음 번호의 상기 복수의 병렬 누산 엔진 정보 비트를 누산하는 단계; 및e) 각각의 새로운 정보 비트마다 상기 제2 특정 패리티 비트 어드레스 집합의 각각의 원소에 대한 패리티 비트 어드레스를 소정의 오프셋만큼 증가시키는 단계를 포함하고,상기 복수의 정보 비트 내의 모든 정보 비트가 누산될 때까지 추가 특정 패리티 비트 어드레스 집합과 소정의 오프셋을 이용하여 상기 복수의 정보 비트 내의 각각의 정보 비트가 누산되는 복수의 정보 비트를 포함한 데이터를 인코딩하는데 이용되는 저밀도 패리티 검사 코드를 설계하기 위한 방법.
- 제8항에 있어서,상기 소정의 오프셋은 코드-의존형인 방법.
- 제9항에 있어서,각각의 패리티 비트 어드레스의 패리티 비트를 바로 이전 패리티 비트 어드레스의 패리티 비트에 더함으로써 상기 패리티 비트를 누산하는 단계를 더 포함하는 방법.
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Applications Claiming Priority (11)
Application Number | Priority Date | Filing Date | Title |
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US60153304P | 2004-08-13 | 2004-08-13 | |
US60/601,533 | 2004-08-13 | ||
US65113105P | 2005-02-08 | 2005-02-08 | |
US60/651,131 | 2005-02-08 | ||
US65259705P | 2005-02-14 | 2005-02-14 | |
US60/652,597 | 2005-02-14 | ||
US65600305P | 2005-02-24 | 2005-02-24 | |
US60/656,003 | 2005-02-24 | ||
US65786005P | 2005-03-02 | 2005-03-02 | |
US60/657,860 | 2005-03-02 | ||
PCT/US2005/027447 WO2006020460A2 (en) | 2004-08-13 | 2005-08-03 | Code design and implementation improvements for low density parity check codes for multiple-input multiple-output channels |
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KR20070035115A KR20070035115A (ko) | 2007-03-29 |
KR100886075B1 true KR100886075B1 (ko) | 2009-02-26 |
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EP (1) | EP1790083B1 (ko) |
JP (1) | JP4891243B2 (ko) |
KR (1) | KR100886075B1 (ko) |
AT (1) | ATE495582T1 (ko) |
CA (1) | CA2577291C (ko) |
DE (1) | DE602005025896D1 (ko) |
HK (1) | HK1130124A1 (ko) |
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EP1790083B1 (en) * | 2004-08-13 | 2011-01-12 | Dtvg Licensing, Inc | Code design and implementation improvements for low density parity check codes for multiple-input multiple-output channels |
US8010870B2 (en) | 2005-04-25 | 2011-08-30 | Sony Corporation | Coding apparatus and coding method |
CN100446427C (zh) * | 2006-08-07 | 2008-12-24 | 北京泰美世纪科技有限公司 | 移动数字多媒体广播系统中ldpc码的构造方法 |
KR100975695B1 (ko) * | 2007-02-02 | 2010-08-12 | 삼성전자주식회사 | 통신 시스템에서 신호 수신 장치 및 방법 |
US20100122143A1 (en) * | 2007-03-27 | 2010-05-13 | Hughes Network Systems, Llc | Method and system for providing low density parity check (ldpc) coding for scrambled coded multiple access (scma) |
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CA2577291C (en) | 2015-05-19 |
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WO2006020460A3 (en) | 2006-05-18 |
EP1790083B1 (en) | 2011-01-12 |
CA2577291A1 (en) | 2006-02-23 |
JP4891243B2 (ja) | 2012-03-07 |
EP1790083A4 (en) | 2009-04-29 |
ATE495582T1 (de) | 2011-01-15 |
HK1130124A1 (en) | 2009-12-18 |
WO2006020460A2 (en) | 2006-02-23 |
DE602005025896D1 (de) | 2011-02-24 |
KR20070035115A (ko) | 2007-03-29 |
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