KR100884642B1 - Apparatus and method for DLL-based frequency multiplier with self-calibration - Google Patents

Abstract

The present invention relates to a delay locked loop based frequency multiplication apparatus and method having a self-correction function. The frequency multiplying device includes a voltage control delay line and a buffer stage having N delay stages, and locks the last reference clock past the buffer stage through the voltage control delay line to the reference clock signal passing through the buffer stage, A delay locked loop for generating N + 1 differential clock signals evenly distributed from the reference clock signal by the number N of delay stages from the reference clock signal, and passing the differential clock signals through the buffer stage; A self-correction block for correcting mismatches of the differential clock signals passing through the buffer stage, the output signal of the delay locked loop; And an edge combiner for generating an output clock multiplied by a multiple of the differential clock signals corrected in the self-correction block.

Self-Calibration, Delay-Locked Loop, Frequency Multiplier, Voltage-Controlled Delay Line

Description

Apparatus and method for DLL-based frequency multiplier with self-calibration}

1 is a block diagram of a delay locked loop based frequency multiplier with self-correction function in accordance with a preferred embodiment of the present invention.

2 is a diagram illustrating an example in which a frequency doubled in a frequency multiplier according to an exemplary embodiment of the present invention.

3 is a block diagram of a self-correction block according to an embodiment of the present invention.

4 is a view for explaining the operation of the timing error comparator (Timing Error Comparator) according to an embodiment of the present invention.

5 is a circuit diagram of a lock detector in accordance with a preferred embodiment of the present invention.

6 is a flowchart illustrating a frequency multiplication procedure in a delay locked loop based frequency multiplier having a self-correcting function according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

110: Delay-Locked Loop (DLL)

111: voltage controlled delay line (VCDL)

113: buffer stage

119: Lock Detector

120: Self-Calibration Block

130: Edge Combiner

The present invention relates to a delay locked loop based frequency multiplication apparatus and method having a self-correction function.

In the 21st century, the world is entering an information society. An information society is a society that can access information and use it freely anytime and anywhere. The biggest technological factor that has made this information society possible is the rapid development of microprocessors. Since 1971, when Intel introduced the 4004, a 108KHz speed microprocessor consisting of 2,250 10-micron transistors, Samsung's alpha processor reached its 1GHz operating range in 2000 and Intel in December 2002. With the introduction of the 3GHz Pentium4, microprocessor technology has entered the "Beyond GHz" era. In 2010, an 11GHz microprocessor with an estimated 100 nanometer transistors of 40nm line width is expected to be developed.

As microprocessors advance to higher performance, the bandwidth of many components in computers and digital communications is increasing. The time for data transmission or movement is getting shorter, and the time for determining and processing it is also getting shorter. However, the time that registers stabilize when storing data is no longer short. In addition, the development of low jitter clock generators is an important issue for many systems, because the effects of jitter or skew, which are indeterminate time domains, must be considered. This phenomenon becomes more important in a situation where a System on a Chip (SoC) is in progress. Therefore, the development of low-jitter clock generators will be important as systems become increasingly faster and more integrated.

Most clock generators in conventional systems have used a phase-locked loop that incorporates a voltage controlled oscillator. However, the voltage controlled oscillator has a disadvantage in that the output jitter is accumulated during various oscillation cycles, and the switching to the low power essential various operating modes is slow. In contrast, a delay-locked loop-based frequency multiplier that uses a voltage controlled delay line does not allow the voltage-controlled delay line to scale jitter and to operate differently in each mode of operation. It has the advantage of fast relocking when switching to mode. Here, the frequency multiplier refers to a device for multiplying the frequency. In addition, the delay lock loop-based frequency multiplier can maintain stability as a first-order system and has the advantage of easy integration of loop filters.

Using this advantage of delay lock loops, delay lock loop based frequency sieves have been proposed. However, conventional delay lock loop based frequency multipliers use an edge combiner that uses a multi-phase clock signal generated from a voltage controlled delay line as an input to multiply frequencies. In general, a mismatch is inevitably generated in a layout process and a manufacturing process between the multiple clocks generated at the delay stages of the voltage control delay lines. This mismatch generates fixed pattern jitter and spurs in the delay locked loop based frequency multiplier output, which degrades the performance of the delay locked loop based frequency multiplier. Therefore, there is a growing need for a frequency multiplier that can reduce such mismatches and reduce jitter.

An object of the present invention for solving the above problems is inevitably generated between the multiple clock (Multi Phase Clock) occurring in the delay stage of each voltage control delay line through the self-correction circuit in the delay lock loop-based frequency multiplier It is an object of the present invention to provide an apparatus and a method for reducing fixed pattern jitter and spurs which affect the output of a frequency multiplier due to mismatches.

In order to achieve the above objects, according to an aspect of the present invention includes a voltage controlled delay line and a buffer stage having N delay stages, and pass the voltage controlled delay line to the reference clock signal passing through the buffer stage to the buffer stage. Locking the last reference clock past the second reference clock, generating N + 1 differential clock signals evenly distributed from the reference clock signal by the number N of delay stages in the locked state, and passing the differential clock signals through the buffer stage. Delay locked loop; A self-correction block for correcting mismatches of the differential clock signals passing through the buffer stage, the output signal of the delay locked loop; And an edge combiner for generating an output clock multiplied by a predetermined multiple from the differential clock signals corrected in the self-correction block.

In a preferred embodiment, the delay lock loop further comprises a phase detector and a charge pump, the phase detector detecting a phase difference between the buffered reference clock signal and the voltage control delay line and the last clock signal passed through the buffer stage. The charge pump changes the signals UP and DN corresponding to the phase difference into voltage signals so that the voltage control delay line generates a delay amount proportional to the voltage signal Vc, and thus the reference clock. The phase difference between the signal and the last clock signal is locked to be zero.

The delay lock loop may further include a lock detector, and the lock detector compares two signals of the differential clock signals that have passed through the buffer stage, when the difference between the two clock signals is smaller than a predetermined delay amount. The self-correction block may generate a control signal to perform the correction operation. The two signals may be signals in which the reverse signal of the reference signal passes through the buffer terminal and the reverse signal of the last clock of the voltage control delay line passes through the buffer terminal.

The self-correcting block of the frequency multiplying device may further include: a delay cell including N + 1 delay stages input from the voltage control delay line to the differential clock signals passing through the buffer stage; And adjusting a control voltage corresponding to a time difference between the differential output clocks passing through the delay cell and adjusting a delay amount of the delay stage according to the adjusted control voltage to correct a mismatch generated in the voltage control delay line. And N timing comparators.
The timing comparator may further include a first AND gate configured to perform a logic operation on a clock signal (/ C _{mod16 (i + 2)} or C _{mod16 (i + 1)} ) input from the delay cell; An inverter for inverting and outputting a signal input from the first AND gate; A first PMOS transistor driven by a signal input from the inverter; A second AND gate for performing a logic operation on the clock signals / C _{mod (i + 1)} and C _{mod16 (i)} input from the delay cell; A first NMOS transistor driven by a signal input from the second AND gate; A second NMOS transistor operating as a current source by a first bias voltage bias1 generated in the bias circuit; A second PMOS transistor operating as a current source by a second bias voltage bias2 generated in the bias circuit; A third NMOS transistor acting as a switch turned on or off by a control signal generated by the lock detector; And a third PMOS transistor which _operates as a capacitor to charge and discharge and adjusts the value of the control voltage V _{mod16 (i + 1)} .

In addition, the frequency multiplication device further comprises a multiplier regulator, characterized in that controlled by the multiplication ratio of the predetermined multiple by the control signal of the multiplier regulator.

According to another aspect of the present invention, in a delay locked loop-based frequency multiplication method having a self-correction function, a reference clock signal B ₀ passing through a buffer stage includes a voltage control delay line including N delay stages. Locking the voltage control delay line by locking a last clock signal (B _N ) of the voltage control delay line past the buffer stage; Generating differential clock signals evenly distributed by the number N of delay stages by passing the reference clock signal through the delay stages of the voltage controlled delay line while the voltage control delay line is locked; Passing the differential clock signals through the buffer stage to generate output differential signals; Correcting mismatches between the output differential clock signals; And generating an output clock frequency-multiplied by a constant multiplication ratio from the corrected output differential clock signals.

The frequency multiplication method may further include determining whether the delay locked loop is locked, and a signal Bb _{0 in which} an inverse signal of a reference clock signal passes through the buffer stage among the output differential signals passed through the buffer stage. And determining whether the delay locked loop is locked by comparing the inverse signal of the last clock passing through the last delay stage of the voltage control delay line with the signal Bb _N passing through the buffer stage.

In a preferred embodiment, correcting the mismatch between the output differential clock signals comprises delaying the delay cell by a delay cell after the differential clock signals generated at the voltage control delay line and passing through the buffer stage. Adjusting a control voltage according to the time difference between the differential output clocks that pass, and by adjusting the delay amount of the delay cell according to the adjusted control voltage to correct the mismatch generated in the voltage control delay line. .

Next, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a delay locked loop based frequency multiplier having a self-correcting function according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the frequency multiplier according to the present invention includes a delay locked loop (DLL), a self-calibration block (120), an edge combiner (130), A multiplication factor controller 140 is included to dynamically multiply the frequency of the input clock to generate an output clock Clk _mul .

The delay locked loop (DLL) 110 includes a voltage controlled delay line (VCDL) 111, a buffer stage 113, a phase detector 115, a charge pump 117, and a lock detector. (Lock Detector, 119). Meanwhile, in the embodiment of the present invention, the delay locked loop 110 includes 16 delay stages, but is not limited thereto. The operation of the delay locked loop 110 having the above configurations will be described below. The delay locked loop 110 passes the voltage control delay line 111 to the reference clock signal B ₀ passing through the buffer stage 113 to receive the last clock signal B ₁₆ past the buffer stage 113. Lock it. At this time, the delay locked loop 110 phases out the phase difference between the buffered reference clock signal B ₀ , the voltage control delay line 111, and the last clock signal B ₁₆ that has passed through the buffer terminal 113. After comparison through the detector 115, the signals UP and DN corresponding to the phase difference are changed into the voltage signal Vc through the charge pump 117. The voltage control delay line 111 generates a delay amount proportional to the voltage signal Vc, and eventually locks the phase difference between the B ₀ signal and the B ₁₆ signal to be zero.

In this state in which the delay lock loop 110 is locked, the voltage control delay lines 111 are clock signals A ₀ -A _N and Ab distributed evenly by the number of delay stages N (= 16) within one period. ₀ -Ab _N ) is generated. The A ₀ signal is a reference clock signal Clk _ref , and the Ab ₀ signal is an inverse signal Clk _refb of the reference clock signal Clk _ref . The A _N signal is a signal in which the reference clock signal Clk _ref is delayed by N delay stages, and the Ab _N signal is a signal in which the inverse signal Clk _refb of the reference clock signal is delayed by N delay stages. The voltage control delay line 111 of the delay lock loop 110 is designed to have a differential structure, and thus the voltage control delay line 111 may provide differential clock signals of A ₀ -A _N and Ab ₀ -Ab _N. Generate.

The buffer stage 113 generates differential clock signals B ₀ -B _N and Bb ₀ -Bb _N as inputs of the differential clock signals A ₀ -A _N and Ab ₀ -Ab _N. That is, the differential clock signals of B ₀ -B _N and Bb ₀ -Bb _{N correspond to} signals where the differential clock signals of A ₀ -A _N and Ab ₀ -Ab _N pass through the buffer stage 113.

When the period of the reference clock signal Clk _{ref is} referred to as T _ref , the differential clock signals B ₀ -B _N and Bb ₀ -Bb _N in the state where the delay locked loop 110 is locked are T _ref / Delay evenly by N hours. For example, the time difference between B ₀ and B ₁ is T _ref / N.

The lock detector 119 of the delay lock loop 110 is configured to generate the delay lock loop by using two clock signals Bb ₀ and Bb ₁₆ generated from the voltage control delay line 111 and passed through the buffer terminal 113. It is determined whether or not 110 is locked to generate an output signal en_calib for controlling the self-correction block 120. The self-calibration block 120 operates normally when the en_calib signal is 'L', and the self-calibration block 120 does not operate when the en_calib signal is 'H'. That is, the self-correction block 120 starts to operate only when the delay lock loop 110 is locked to some extent (Coarse Locking).

The self-correction block 120 receives clock signals B ₀ -B _{16 and} Bb ₀ -Bb ₁₆ generated from the voltage control delay line 111 and passed through the buffer terminal 113 as inputs, and the clock signals are inputted. It serves to correct mismatches between them.

The edge combiner 130 multiplies the frequency by using the clock signals C ₀ -C _{16 and} Cb ₀ -Cb ₁₆ corrected in the self-correction block 120. The multiplier regulator 140 adjusts the multiplication ratio by generating a control signal S ₁ -S ₄ to the self-correction block 120. The frequency of the _final output clock signal Clk _mul may vary by 0.5 times, 1 times, 2 times, 4 times, or 8 times the input clock frequency according to the control signals S ₁ -S ₄ . Table 1 below shows the multiplication ratio of the output clock (Clk _mul ) frequency to the input clock frequency in accordance with the control signal of the multiplication ratio regulator.

2 is a diagram illustrating an example in which a frequency doubled in a frequency multiplier according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the case where the number N of delay stages of the voltage control delay line is 4 will be described as an example. However, it is preferable that the multiplier based on the low jitter delay locked loop having the self-correcting function actually implemented has 16 delay stages. The C _i clock signals are clock signals generated at the voltage control delay line and passed through the buffer stage, and mismatched between the clocks by the self-correction block. Using the C _i clock signals, an edge combiner generates P _i signals and generates an output clock signal Clk _mul multiplied by two times using the P _i signals. Each of the clock signals C _i P _i signal at each rising edge is reversed and, it can be seen that the output clock signal (Clk _mul) is inverted at every falling edge of the signal P _i. In the above example, the output clock signal has a double multiplication ratio, but when the number of delay stages is N, the frequency multiplication ratio of the output clock signal is N / 2.

After all, the frequency multiplier according to the present invention operates only in response to the rising edges of the clocks generated from the voltage control delay line VCDL, so that the duty ratio of the multiplied clock is 50 even if the duty ratio of the input clock is not 50%. Can be set to%.

3 is a block diagram of a self-correction block according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the self-correction block 120 includes a delay cell 310 and a timing error comparator 320. At this time, the delay cell 310 includes one more delay stages than the number N (= 16) of the delay stages of the voltage control delay line VCDL of the delay locked loop DLL. In addition, the timing comparator 320 exists by the number N of delay stages of the voltage control delay line VCDL.

The delay cell 310 of the self-correction block 120 inputs clock signals B ₀ -B ₁₆ and Bb ₀ -Bb ₁₆ generated from the voltage control delay line VCDL and passed through the buffer terminal 113. It is done. The timing comparator 320 receives the outputs C ₀ -C ₁₅ and Cb ₀ -Cb ₁₅ of the delay cell 310 as inputs.

4 is a diagram for describing an operation of a timing error comparator according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the signals on the left show the operation waveform of the timing comparator, and the right shows the circuit diagram of the timing comparator. The timing comparator includes a first AND gate 401, a second AND gate 403, an inverter 405, a first NMOS transistor M ₁ , a second NMOS transistor M ₂ , and a third NMOS transistor ( M ₅ ), a first PMOS transistor M ₄ , a second PMOS transistor M ₃ , and a third PMOS transistor M ₆ . The first AND gate 401 performs a logic operation on the clock signals / C _{mod16 (i + 2)} and C _{mod16 (i + 1)} input from the delay cell 310, and outputs the second AND gate. In operation 403, the clock signals / C _{mod16 (i + 1)} and C _{mod16 (i)} input from the delay cell 310 are logically outputted. The inverter 405 inverts and outputs a signal input from the first AND gate 401. The first PMOS transistor M ₄ is driven by a signal input from the inverter 405, and the first NMOS transistor M ₁ is driven by a signal input from the second AND gate 403. Driven. The second NMOS transistor M ₂ operates as a current source by the first bias voltage bias1 generated in the bias circuit, and the second PMOS transistor M ₃ is a second generated in the bias circuit. The bias voltage bias2 operates as a current source. The third NMOS transistor M ₅ operates as a switch turned on or off by an en_calib signal, which is a control signal generated from the lock detector, and the third PMOS transistor M ₆ operates like a capacitor.

One timing comparator takes four clocks (/ C _{mod16 (i + 2)} , C _{mod16 (i + 1)} , / C _{mod (i + 1)} , and C _{mod16 (i} ) as inputs to determine the time difference between the clocks. Compare. The time difference between C _{mod16 (i)} and C _{mod16 (i + 1)} generates a signal of Phi_d _{, and} the time difference between C _{mod (i + 1)} and C _{mod16 (i + 2)} generates a signal of Phi_u. The timing comparator adjusts the value of the control voltage V _{mod16 (i + 1)} by charging and discharging the PMOS transistor M ₆ by the Phi_d signal and the Phi_u signal. The adjusted control voltage corrects mismatches generated in the voltage control delay line VCDL by adjusting the delay amount of the delay stage of the self-correction block.

The en_calib signal input to the NMOS transistor M ₅ is a signal generated by a lock detector, and the lock detector sets the value of the en_calib signal to 'H' until the delay lock loop becomes somewhat locked. The control voltage V _{mod16 (i + 1} ) is initialized by holding.

5 is a circuit diagram of a lock detector according to a preferred embodiment of the present invention.

Referring to FIG. 5, the lock detector initializes the control voltage values V _{mod16 (i + 1)} of the self-correction block until the delay locked loop DLL is locked. Therefore, when the control voltage value is not initialized, initial error values that may be generated by the timing comparator operation may be eliminated until the delay locked loop is locked. The lock detector inputs two clock signals Bb ₀ and Bb ₁₆ which have passed through the buffer stage. The Bb ₀ signal is an inverse signal of the reference clock passing through the buffer stage, and the Bb ₁₆ signal is an inverse signal of the last clock of the voltage control delay line passing through the buffer stage. When the difference between the two clock signals is smaller than the predetermined delay amount t _d , the lock detector changes the en_calib signal from 'H' to 'L' and the self-correction block starts a correction operation.

6 is a flowchart illustrating a frequency multiplication procedure in a delay locked loop based frequency multiplier having a self-correcting function according to an exemplary embodiment of the present invention.

Referring to FIG. 6, the frequency multiplier according to the present invention first locks the last clock signal B ₁₆ past the buffer stage through the voltage control delay line VCDL to the reference clock signal B ₀ having passed through the buffer stage. Lock the delay lock loop (DLL) (step 601). With the delay lock loop DLL locked, the frequency multiplier generates differential clock signals evenly distributed by the number of delay stages by passing a reference signal through the delay stages of the voltage control delay line VCDL (step). 603). The frequency multiplier then passes the differential clock signals through the buffer stage to generate output differential signals (step 605). Here, the output differential signals passing through the buffer stage are input to an input of a self-correction block.

Meanwhile, the lock detector of the frequency multiplier determines whether the delay locked loop DLL is locked (step 607). In this case, the lock detector includes a signal Bb _{0 in which} an inverse signal of the reference clock signal passes through the buffer stage and an inverse signal of the last clock that passed through the last delay stage of the voltage control delay line. It is determined whether the delay locked loop DLL is locked by comparing the signal Bb ₁₆ passing through the buffer stage.

If it is determined in step 607 that the delay locked loop is locked, the frequency multiplier corrects mismatches between the output differential clock signals (step 609). The frequency multiplier then performs frequency multiplication of the corrected output differential clock signals at a desired multiplication ratio under the control of a multiplier regulator (step 611).

The present invention is not limited to the above embodiments, and many variations are possible by those skilled in the art within the spirit of the present invention.

According to the present invention, in the delay lock loop-based frequency multiplier, a mismatch inevitably generated between the multi-phase clocks generated in the delay stages of the voltage control delay lines may be corrected through a self-correction circuit.

In addition, according to the present invention, there is an advantage of reducing jitter and spur affecting the output of the frequency multiplier due to mismatches between multiple clocks occurring at the delay stages of the voltage control delay lines. have.

Claims (11)

And a voltage controlled delay line having a N delay stage and a buffer stage, and locking the last reference clock past the buffer stage through the voltage controlled delay line to the reference clock signal passing through the buffer stage, and in the locked state. A delay locked loop for generating N + 1 differential clock signals evenly distributed from a reference clock signal by the number N of delay stages, and passing the differential clock signals through the buffer stage; A self-correction block for correcting mismatches of the differential clock signals passing through the buffer stage, the output signal of the delay locked loop; And And a self-correction function comprising an edge combiner for generating an output clock multiplied by a multiple of the differential clock signals corrected in the self-correction block. The method of claim 1, The delay locked loop further comprises a phase detector and a charge pump, The phase detector detects a phase difference between the buffered reference clock signal and the voltage control delay line and the last clock signal passing through the buffer stage, and the charge pump applies a signal UP, DN corresponding to the phase difference, to a voltage signal. The voltage controlled delay line generates a delay amount proportional to the voltage signal, and thus the reference clock. The phase difference between the signal and the last clock signal is locked to zero A delay locked loop based frequency multiplication device having a self-correcting function. The method of claim 1, The delay locked loop further comprises a lock detector, The lock detector compares two signals of the differential clock signals passing through the buffer stage, and supplies a control signal to the self-correction block to perform the correction operation when the difference between the two clock signals is smaller than a predetermined delay amount. Generator A delay locked loop based frequency multiplication device having a self-correcting function. The method of claim 3, The two signals are delayed loop based self-correction function, characterized in that the reverse signal of the reference signal has passed through the buffer terminal and the reverse signal of the last clock of the voltage control delay line has passed through the buffer terminal. Frequency multiplication device. The self-correcting block of claim 1, wherein A delay cell including N + 1 delay stages generated at the voltage control delay line and inputting the differential clock signals passing through the buffer stage; And By adjusting a control voltage corresponding to the time difference of the differential output clocks passing through the delay cell, and adjusting the delay amount of the delay stage according to the adjusted control voltage to correct the mismatch generated in the voltage control delay line A delay locked loop based frequency multiplier device having self-correction function comprising N timing comparators. The method of claim 5, wherein the timing comparator, A first AND gate for performing a logic operation on the clock signals (/ C _{mod16 (i + 2)} and C _{mod16 (i + 1)} ) input from the delay cell; An inverter for inverting and outputting a signal input from the first AND gate; A first PMOS transistor driven by a signal input from the inverter; A second AND gate for performing a logic operation on the clock signals / C _{mod (i + 1)} and C _{mod16 (i)} input from the delay cell; A first NMOS transistor driven by a signal input from the second AND gate; A second NMOS transistor operating as a current source by a first bias voltage bias1 generated in the bias circuit; A second PMOS transistor operating as a current source by a second bias voltage bias2 generated in the bias circuit; A third NMOS transistor acting as a switch turned on or off by a control signal generated by the lock detector; And And a third PMOS transistor configured to operate as a capacitor to charge and discharge to adjust a value of the control voltage V _{mod16 (i + 1)} . The method of claim 1, And a multiplier adjuster, and the delay multiplier-based frequency multiplying device having a self-correcting function characterized in that the multiplier is controlled at a multiplier ratio of the predetermined multiple by a control signal of the multiplier adjuster. In the delay lock loop-based frequency multiplication method having a self-correction function, The voltage control delay line is locked by locking the last clock signal B _{N of} the voltage control delay line passing through the buffer stage through the voltage control delay line including N delay stages to the reference clock signal B ₀ passing through the buffer stage. Locking the; Generating differential clock signals evenly distributed by the number N of delay stages by passing the reference clock signal through the delay stages of the voltage controlled delay line while the voltage control delay line is locked; Passing the differential clock signals through the buffer stage to generate output differential signals; Correcting mismatches between the output differential clock signals; And Generating an output clock frequency multiplied by a constant multiplication ratio from the corrected output differential clock signals. The method of claim 8, And determining whether the delay locked loop has been locked. The method of claim 9, Of the output differential signals passing through the buffer stage, a signal Bb _{0 in which} a reverse signal of a reference clock signal passes through the buffer stage and a reverse signal of a last clock passing through the last delay stage of the voltage control delay line pass through the buffer stage. And determining whether the delay locked loop is locked by comparing one signal (Bb _N ). The method of claim 8, Correcting mismatch between the output differential clock signals Delaying the differential clock signals generated at the voltage control delay line and passing through the buffer stage by a delay cell, and then adjusting a control voltage according to the time difference of the differential output clocks passing through the delay cell, And multiplying the delay amount of the delay cell according to a control voltage to correct a mismatch generated in the voltage control delay line.

Images