KR100884606B1 - Input buffer of semiconductor memory device - Google Patents

Abstract

The present invention provides an input buffer of a semiconductor memory device capable of stably recognizing a signal without being influenced by noise introduced from the outside. The present invention provides a first amplifying means for amplifying an input signal; And second amplifying means for sensing, amplifying, and outputting a level of the output signal of the first amplifying means with respect to a reference voltage.

Input Buffer, Multi-Step Amplification, Noise Immunity, NMOS Transistor, Gain

Description

Input buffer of semiconductor memory device {INPUT BUFFER OF SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly to an input buffer of a semiconductor memory device.

Semiconductor devices are manufactured based on semiconductor technology including silicon wafer processing technology and logic design technology. The final product of the semiconductor manufacturing process is a chip in a plastic package, which has different logic and functions depending on the purpose of use. Most semiconductor chips are mounted on a printed circuit board (PCB), which is an important element in the system configuration, and is supplied with an appropriate driving voltage for driving the chip. All semiconductor devices, including semiconductor memories, operate by input / output of signals having a special purpose. That is, the operation and operation method of the semiconductor device are determined by the combination of the input signals, and the result is output according to the movement of the output signals.

On the other hand, the output signal of one semiconductor device will be used as the input signal of another semiconductor device in the same system. The input buffer is a portion for buffering a signal applied from the outside to be input into the semiconductor device. The simplest form is a static input buffer. The static input buffer has a form of an inverter in which a PMOS transistor and an NMOS transistor are connected in series between a power supply and a ground supply. The static input buffer has the advantage of being very simple in its configuration, but it is weak in noise and requires a large input signal shape. That is, it is required that the swing widths of the levels of the logic level high and the logic level low be large. Therefore, application to devices requiring a small swing width or high operating frequency of the input signal is inappropriate.

To meet these demands, differential amplified input buffers have been proposed. In contrast to traditional static input buffers, differential amplified input buffers are often referred to as dynamic input buffers.

1 is a circuit diagram of an input buffer in a semiconductor memory device according to the prior art.

Referring to FIG. 1, the input buffer according to the related art is connected in series with a current source transistor NM1 and a current source transistor NM1 for supplying a driving current in response to a driving signal EN, and is inputted with a reference voltage VREF1. A loading unit for outputting the first positive and negative output signals OUT1 and OUT1_B connected in series with the differential input transistors NM2 and NM3 having the signal IN1 as a differential input and the differential input transistors NM2 and NM3. 10).

Here, the loading unit 10 is the passive resistance elements R1 and R2 disposed between the supply terminals of the differential input transistors NM2 and NM3 and the power supply voltage VDD, respectively.

Let's look briefly at the operation. Here, it is assumed that the input signal IN1 has a voltage level higher than the reference voltage VREF1.

First, when the driving signal EN is activated at the logic level 'H', the current source transistor NM1 is activated to supply the driving current.

Subsequently, the differential input transistors NM2 and NM3 are turned on by the reference voltage VREF1 and the input signal IN1, respectively. At this time, since the voltage level of the input signal IN1 is higher than the reference voltage VREF1, the differential input transistor NM3 is turned on more. Therefore, the first positive output signal OUT1 has a logic level 'H' and the first sub output signal OUT1_B has a logic level 'L'.

On the other hand, when the input signal IN1 has a voltage level lower than the reference voltage VREF1, the first positive output signal OUT1 has a logic level 'L' and the first sub output signal OUT1_B has a logic level 'H'.

2 is an internal circuit diagram of another input buffer according to the related art.

When comparing the input buffer according to another prior art shown in FIG. 2 with the prior art shown in FIG. 1, it can be seen that the loading unit is different. That is, the loading unit shown in FIG. 2 is current mirror type loading units PM1 and PM2 implemented by PMOS transistors, and is connected to the differential input transistors NM2 and NM3.

In addition, the input buffer according to another prior art outputs only one output signal.

Let's look briefly at driving. Here, it is assumed that the input signal IN2 has a voltage level lower than the reference voltage VREF2.

First, when the driving signal EN is activated to the logic level 'H', the current source transistor NM1 is activated to supply the driving current.

Subsequently, the differential input transistors NM2 and NM3 are turned on by the reference voltage VREF2 and the input signal IN2, respectively. At this time, since the voltage level of the input signal IN2 is lower than the reference voltage VREF2, the differential input transistor NM2 is turned on more. Thus, the output signal OUT2 has a logic level 'H'.

On the other hand, if the input signal IN1 has a voltage level higher than the reference voltage VREF1, the output signal OUT2 has a logic level 'L'.

As described above, the input buffer according to the prior art determines the logic level of the input signal IN1 or IN2 based on the reference voltage VREF1 or VREF2 and converts the output signal OUT1, OUT1_B, OUT2 by converting it to an internal voltage level. Output That is, the duty rate of the output signals OUT1, OUT1_B, and OUT2 is changed according to the level variation of the reference voltage VREF1 or VREF2. Referring to the case illustrated in FIG. 1 as an example, when the level of the reference voltage VREF1 becomes higher than the target, the interval of the logic level 'H' becomes longer because the common level of the output is lowered, and the logic level 'L' The interval becomes smaller. In addition, when the reference voltage VREF1 is lower than the target, the opposite phenomenon occurs.

Therefore, when noise occurs in the reference voltage VREF1 or VREF2, a problem arises in that the duty ratio of the output signal as described above is changed.

Furthermore, as the driving power is lowered, the swing width of the input signal IN1 or IN2 decreases, so that the output signal is sensitive to noise introduced into the reference voltage VREF1 or VREF2. That is, the smaller the swing width of the input signal IN1 or IN2, the greater the influence.

As described above, when the input buffer according to the prior art is used, the duty ratio of the output signal is changed due to noise introduced into the reference voltage, and thus the signal cannot be recognized because the setup / hold time for the clock is not satisfied. .

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide an input buffer of a semiconductor memory device capable of stably recognizing a signal without being affected by noise introduced from the outside.

According to an aspect of the present invention, an input buffer includes: first amplifying means for amplifying an input signal; And second amplifying means for detecting, amplifying and outputting a level of the output signal of the first amplifying means with respect to the reference voltage.

The above-described present invention amplifies the input signal in advance irrespective of the reference voltage, thereby increasing immunity to noise introduced into the reference voltage, thereby improving the timing margin of the setup / hold time of the output signal of the input buffer. .

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

Example 1

3 is an internal circuit diagram of an input buffer of a semiconductor memory device according to a first embodiment of the present invention.

Referring to FIG. 3, the input buffer according to the first embodiment includes a first amplifier 100 for amplifying the input signal IN3 and an output signal of the first amplifier 100 with respect to the reference voltage VREF3. And a second amplifier 200 for sensing and amplifying the level of the signal and outputting the positive and negative output signals OUT3 and OUT3_B.

The first amplifier 100 has a resistor R3 connected between the supply terminal of the power supply voltage VDD and the output node N1, an input signal IN3 as a gate input, and has an output node N1 and a ground voltage ( And an NMOS transistor NM4 having a drain-source path between the supply ends of the VSS.

The second amplifier 200 is connected in series with the current source transistor NM5 and the current source transistor NM5 for supplying a driving current in response to the drive signal EN, and the reference voltage VREF3 and the first amplifier 100 are connected to each other. A differential input transistor unit 220 having an output signal of a differential input) 220 and a loading unit 240 connected in series with the differential input transistor unit 220 to output the first positive and negative output signals OUT3 and OUT3_B. ).

The differential input transistor 220 has an output signal of the first amplifier 100 as a gate input and an NMOS transistor NM7 having a drain-source path between the node N2 and the drain terminal of the current source transistor NM3. And an NMOS transistor NM6 having a reference voltage VREF3 as a gate input and having a drain-source path between the node N3 and the drain terminal of the current source transistor NM3.

The loading unit 240 includes passive resistance elements R4 and R5 respectively disposed between the nodes N2 and N3 and the supply terminal of the power supply voltage VDD.

For reference, the gain of the first amplifier 100 is one or more.

Let's look briefly at driving. Here, it is assumed that the input signal IN3 has a voltage level higher than the reference voltage VREF3.

First, since the first amplifier 100 inverts and amplifies the level of the input signal IN3 and outputs the output signal, the output signal has a level corresponding to the logic level 'L'. In other words, the power supply voltage is divided and output by the turn-on resistance value of the NMOS transistor NM4 adjusted according to the level of the input signal IN3 and the resistor R3.

Subsequently, when the driving signal EN is activated at the logic level 'H', the current source transistor NM5 is activated to supply the driving current.

Subsequently, the differential input transistors NM6 and NM7 are turned on by the reference voltage VREF3 and the output signal of the first amplifier 100, respectively. At this time, since the voltage level of the output signal of the first amplifier 100 is lower than the reference voltage VREF1, the differential input transistor NM6 is turned on more. Therefore, the positive output signal OUT3 has a logic level 'H' and the negative output signal OUT3_B has a logic level 'L'.

On the other hand, when the input signal IN3 has a voltage level lower than the reference voltage VREF1, the positive output signal OUT3 has a logic level 'L' and the negative output signal OUT3_B has a logic level 'H'.

As described above, the input buffer according to the first embodiment further includes a first amplifier 100 to increase the swing width of the input signal IN3. That is, the noise flowing into the reference voltage VREF3 increases the swing width of the input signal IN3 while having a constant change width, and thus is less affected by noise. Therefore, the phenomenon that the duty ratio of the output signal is distorted can be prevented, thereby ensuring the timing margin of the setup / hold time.

Example 2

4 is an internal circuit diagram of an input buffer of the semiconductor memory device according to the second embodiment.

Comparing the input buffer according to the second embodiment shown in FIG. 4 with the first embodiment of FIG. 3, it can be seen that the loading unit is different.

That is, the loading unit 240 of the second amplifier 200 according to the second embodiment is a current mirror rod disposed between the nodes N2 and N3 and the supply terminal of the power supply voltage VDD.

In other words, the loading unit 240 has a voltage applied to the node N3 as a gate input, a PMOS transistor PM3 having a source-drain path between the supply terminal of the power supply voltage VDD and the node N3, and a voltage applied to the node N3. Is provided as a gate input and has a PMOS transistor PM4 having a source-drain path between the supply terminal of the power supply voltage VDD and the node N4, and outputs a voltage applied to the node N4 as an output signal OUT4.

In addition, the input buffer according to the second embodiment outputs only one output signal, but since driving is the same, a detailed description thereof will be omitted.

Therefore, the input buffer according to the first and second embodiments first amplifies the input signal regardless of the reference voltage, and then detects and amplifies the level based on the reference voltage. Since the input signal has a large swing width relative to the noise introduced into the reference voltage, there is no influence on the noise, thereby outputting an output signal having a stable duty ratio. Thus, an output signal with a stable duty ratio improves the timing margin of setup / hold time.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

1 is a circuit diagram of an input buffer in a semiconductor memory device according to the prior art.

2 is an internal circuit diagram of another input buffer according to the prior art.

3 is an internal circuit diagram of an input buffer of a semiconductor memory device according to a first embodiment of the present invention.

4 is an internal circuit diagram of an input buffer of a semiconductor memory device according to a second embodiment.

* Explanation of symbols for the main parts of the drawings

100: first amplifier

200: second amplifier

Claims (8)

First amplifying means for amplifying the input signal; And Second amplifying means for detecting, amplifying and outputting a level of the output signal of the first amplifying means with respect to a reference voltage An input buffer of a semiconductor memory device having a. The method of claim 1, The first amplifying means, And an output buffer having a swing width greater than that of the input signal. The method of claim 2, The first amplifying means, A resistor connected between the supply terminal of the power supply voltage and the first node, And a first NMOS transistor having the input signal as a gate input and having a drain-source path between the first node and a supply terminal of a ground voltage. The method of claim 3, The second amplifying means, A current source transistor for supplying a driving current in response to the driving signal; A differential input transistor section connected in series with the current source transistor and having a differential input having the reference voltage and the output signal of the first amplifying means; And a loading unit connected in series with the differential input transistor to output first positive and negative output signals. The method of claim 4, wherein The current source transistor, And a second NMOS transistor having the driving signal as a gate input and having a drain-source path between a second node and a supply terminal of the ground voltage. The method of claim 5, The differential input transistor unit, A third NMOS transistor having a gate input as an output signal of the first amplifying means and having a drain-source path between a third node and the second node; And a fourth NMOS transistor having the reference voltage as a gate input and having a drain-source path between a fourth node and the second node. The method of claim 6, The loading unit includes second and third resistors disposed between the third and fourth nodes and a supply terminal of the power voltage. And a voltage applied to the third node as a negative output signal, and a voltage applied to the fourth node as a positive output signal. The method of claim 6, The loading unit, A first PMOS transistor having a voltage applied to the third node as a gate input and having a source-drain path between the supply terminal of the power supply voltage and the third node; A third PMOS transistor having a voltage applied to the third node as a gate input and having a source-drain path between a supply terminal of the power supply voltage and the fourth node, And outputting the voltage applied to the fourth node as the output signal.

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