KR100884591B1 - On Die Termination Circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit, and more particularly, to an on-die termination circuit having a difference in on-die termination resistance value corresponding to a change in a control code within a predetermined range. The disclosed invention includes a hybrid resistor circuit having a plurality of resistor sections to which at least two resistance variable modes are applied, and forming an on die termination resistor value as the resistor section selected by a control code; And a control circuit which compares the on die termination resistance value with a reference resistance value and provides the plurality of bits of the control code such that the on die termination resistance value has a resistance value within a calibration range. By the accuracy of the calibration is effective.

Description

On Die Termination Circuit

1 is a block diagram showing an ODT circuit according to the prior art.

FIG. 2 is a detailed circuit diagram of the resistance circuit of FIG. 1. FIG.

3 is a graph simulating the characteristics of the ODT resistance formed by the control code in the ODT circuit of FIG.

4 is a block diagram showing an ODT circuit according to an embodiment of the present invention.

FIG. 5 is a detailed circuit diagram of the hybrid resistance circuit of FIG. 4. FIG.

FIG. 6 is a detailed circuit diagram of the control circuit of FIG. 4.

7 to 9 is a simulation graph comparing the present invention and the prior art.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit, and more particularly, to an on die termination circuit in which a difference in on die termination resistance value corresponding to a change in a control code has a value within a predetermined range.

In general, a semiconductor circuit transmits and receives a signal through an external system and a transmission line, and signal reflection occurs when the impedance of the transmission line and the impedance in the semiconductor circuit directly connected to the transmission line are different from each other.

Since the signal reflection inhibits high speed operation, the semiconductor circuit includes an on die termination circuit (OTD) circuit on the input / output pin to match the impedance of the semiconductor circuit directly connected to the transmission line with the impedance of the transmission line. do.

Referring to FIG. 1, the ODT circuit according to the related art includes a resistor circuit 10 and a control circuit 20.

The resistor circuit 10 includes a plurality of branches B1 to Bn connected in parallel between the power supply voltage terminal VDDQ and the common node ND1 as shown in FIG. 2, and each branch B1 to Bn is connected in series. Switch (S1 to Sn) and resistors (R1 to Rn) connected to each other, and the switches (S1 to Sn) selected by the control code PCODE <1: n> are operated to form a current path. Provide the total sum of parallel resistance as the ODT resistance.

Here, the switches S1 to Sn are constituted by PMOS transistors selectively turned on by the control codes PCODE <1: n> applied to the gates.

In addition, the relative resistance ratios of the resistors R1 to Rn are determined according to the setting method. When the full binary weighting method is used, the resistance ratio between the branches is set to 2, and the equation is as follows. same.

R2 = 1 / 2R1; R3 = 1 / 4R1; R4 = 1 / 8R1; ...; Rn = 1/2 ^n-1 R1

In FIG. 1, the control circuit 20 compares the divided voltage VIN distributed by the reference resistor ZQ and the ODT resistor and the reference resistor ZQ connected between the common node ND1 and the ground voltage terminal VSS to the reference voltage VREF. 22), the counter unit 24 for increasing or decreasing by the comparison signal COM output from the comparing unit 22 and outputting a count signal COUNT synchronized with the clock CLK, and each branch B1 to Bn of the resistance circuit 10. ) Is a one-to-one correspondence and includes a control unit 26 that increases or decreases by the counter signal COUNT and is controlled by the enable signal EN and outputs the control code PCODE.

Here, the level of the reference voltage VREF is typically set to the VDDQ / 2 level, which is half the level of the power supply voltage terminal VDDQ, which is equal to the level of the divided voltage VIN when the ODT resistance and the reference resistor ZQ have the same magnitude.

The number of bits of the count signal COUNT and the number of bits of the control code PCODE are the same, and the increase or decrease of the counter signal COUNT and the control code PCODE means an increase or decrease of the bit value.

The control circuit 20 compares the magnitudes of the ODT resistor and the reference resistor ZQ, and adjusts the bit value of the control code PCODE so that the difference between the ODT resistor and the reference resistor ZQ is gradually reduced as the clock CLK progresses.

As a result, the ODT resistor converges to a difference within the 1-bit resolution from the reference resistor ZQ within a finite clock. Here, the bit resolution is defined as the difference in the ODT resistance value according to one bit change of the control code PCODE.

Referring to FIG. 3, the ODT circuit according to the related art provides the ODT resistance non-linearly corresponding to the control code PCODE as shown in the graph G1.

Here, for convenience of description, the resistance circuit 10 is controlled by a 5-bit control code PCODE, the reference resistor ZQ is 240 ohms (Ω), and the ODT resistance is 240 ohms at the bit value "11000" of the control code PCODE. Assume that it is calibrated to

At this time, the bit value "11000" of the control code PCODE is referred to as a reference code (Default Code; DC), the X axis of FIG. 3 represents the bit value of the control code PCODE in decimal, and the Y axis represents the ODT resistance.

Referring to the graph G1, the ODT resistance value has a higher bit resolution with respect to the direction in which the control code PCODE decreases based on the reference code 24, and conversely, a bit resolution decreases with respect to a direction in which the control code PCODE increases. have.

That is, the bit resolution is not constant in the ODT resistance corresponding to the change of the control code PCODE. This is a general characteristic of the ODT circuit in which the resistance ratio is set by the full binary weighting method.

On the other hand, since the resistance (R1 ~ Rn) of the ODT circuit is generated by the process, it often occurs to have a different resistance value than the design time due to changes in the external environment, for example, PVT (Process, Voltage, Temperature). Therefore, the ODT circuit adjusts the control code PCODE to calibrate the ODT resistance to approach the reference resistance ZQ.

For example, as shown in the graph G2 of FIG. 3, when the ODT resistance corresponding to the reference code 24 is 270 (Ω) larger than 240 Ω (Ω), which is the reference resistance ZQ, the ODT circuit increases the control code PCODE to increase the ODT resistance. Is reduced to the reference resistance ZQ.

On the contrary, when the ODT resistance corresponding to the reference code 24 is 210 (Ω) smaller than 240 Ω (Ω) of the reference resistance ZQ, as shown in the graph G3 of FIG. 3, the ODT circuit decreases the control code PCODE to reduce the ODT. Increase the resistance to the reference resistance ZQ.

Therefore, when the difference of the ODT resistance value corresponding to the change of the control code PCODE, that is, the bit resolution is not constant, the accuracy of the calibration decreases, which makes it difficult to operate the semiconductor at high speed.

In particular, when the control code PCODE decreases to correct the ODT resistance value, the bit resolution increases, so that the accuracy of the calibration is further reduced.

Accordingly, an object of the present invention is to control the ODT resistance value so that the difference in the ODT resistance value has a value within a predetermined range in response to the change of the control code.

The on-die termination circuit of the present invention for achieving the above object, has a plurality of resistor portions to which at least two resistance variable mode is applied, and a hybrid resistor circuit for forming an on die termination resistance value with the resistor portion selected by a control code. ; And a control circuit which compares the on die termination resistance value with a reference resistance value and provides the control code for adjusting the on die termination resistance value to have a resistance value within a calibration range.

The hybrid resistor circuit may include a first resistor unit configured to form the on die termination resistor value as a plurality of branches to which a resistance value designation mode is applied; And a second resistor unit configured to form the on die termination resistance value as a plurality of branches to which the resistance value sequential variable mode is applied; Characterized in that configured to include.

Preferably, the first and second resistor units are connected in parallel between the power supply terminal and the common node, and each branch includes a switch and a resistor connected in series.

Here, it is preferable that the first resistor unit is set by the resistance value designation mode in which the difference in the on-die termination resistance value corresponding to the change of the control code is uniform.

The second resistor unit may be set by the resistance value sequential variable mode in which the value of the resistance is gradually varied in the difference between the on-die termination resistance value corresponding to the change of the control code.

Preferably, the difference in the on die termination resistance value gradually decreases in response to an increase in the control code.

Preferably, the switch is a MOS transistor controlled by the control code applied to a gate to transfer the voltage level of the power supply terminal to the common node.

Preferably, the power stage is a power supply voltage level and the switch is a PMOS transistor.

Preferably, the power supply stage is a ground voltage level and the switch is an NMOS transistor.

The control circuit may include: a comparison unit comparing the on-die termination resistance value with the reference resistance value to compare a comparison signal; A counter unit for outputting a count signal that increases or decreases in response to the comparison signal; And a controller which decodes the count signal and outputs the control code corresponding thereto.

The control unit includes a decoding unit for decoding the count signal; And an output unit which outputs the decoded signal by the enable signal to the control code.

Preferably, the decoding unit includes a decoding circuit corresponding to each of the resistor units, one of the decoding circuits is selected by the count signal, and decoding of the count signal by the selected decoding circuit is performed.

The decoding circuit may include: a first decoding circuit configured to generate a first decoded signal representing the on die termination resistance value with the first resistor unit to which the resistance value specifying mode is applied; And a second decoding circuit configured to generate a second decoded signal representing the on die termination resistance value as the second resistor unit to which the resistance value sequential variable mode is applied.

Preferably, the first decoding circuit outputs the first decoding signal of more bits than the count signal by the combination of the count signals.

Preferably, the second decoding circuit outputs the second decoding signal by transferring the count signal.

Another on-die termination device for achieving the object of the present invention comprises a control unit for outputting the first and second control codes for comparing the output resistance value and the target resistance value to adjust the output resistance value to the target resistance value; A first resistor unit configured to increase the output resistance value to a uniform size by the first control code to adjust the target resistance value; And a second resistor unit configured to reduce the output resistance value to a variable magnitude by the second control code to adjust the target resistance value to the target resistance value.

Preferably, the first and second resistor units include a plurality of branches connected in parallel between a power supply terminal and a common node, and each branch includes a switch and a resistor connected in series.

Preferably, the first resistor unit sets the resistance value of each branch so that the change in the output resistance value output in response to the change in the first control code is uniform.

Preferably, the second resistor unit is set such that the resistance value between the branches has a constant magnification.

The switch is preferably a MOS transistor controlled by the first and second control codes applied to the gate to transfer the voltage level of the power supply terminal to the common node.

Preferably, the power stage is a power supply voltage level and the switch is a PMOS transistor.

Preferably, the power supply stage is a ground voltage level and the switch is an NMOS transistor.

The controller may include: a first controller configured to output the first control code to control the first resistor unit by count signals; And a second control unit for outputting the second control code for controlling the second resistor unit by the count signals.

The count signals may be signals in which the signal obtained by comparing the output resistance value with the target resistance value is output in synchronization with a clock.

The first controller is configured to output the first control code of more bits than the count signal by combining the count signals.

Preferably, the second control unit inverts the count signal and outputs the count signal to the second control code.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

The present invention discloses an ODT circuit for improving calibration accuracy by providing an ODT resistance value in which the difference in the ODT resistance value is equal to or less than a predetermined range in response to a change in the control code.

Referring to FIG. 4, an ODT circuit according to an embodiment of the present invention has a plurality of resistor parts to which at least two resistance variable modes are applied, and forms a ODT resistance value as a resistor part selected by a control code. And a control circuit 120 for comparing the ODT resistance value with the reference resistance value and providing a plurality of the control codes so that the ODT resistance value has a resistance value within a calibration range.

Hereinafter, for convenience of description, in the ODT circuit of this embodiment, the ODT resistance is calibrated in 15 steps by the control code PCODE, and sets the calibration range of the ODT resistance by 7 steps each up and down based on the target resistance RT. Here, the target resistance RT is a resistance when the ODT resistance value is equal to the reference resistance value.

Specifically, as shown in FIG. 5, the hybrid resistor circuit 110 includes the first resistor unit 112 forming a seven-step ODT resistance value larger than the target resistance RT, and the seven stages smaller than the target resistance RT and the target resistance RT. And a second resistor 114 to form an ODT resistance value.

Here, the first resistor 112 and the second resistor 114 are a plurality of branches (<BR0, BR1, BR1x, BR2, BR2x>, <(BR3, BR4) connected in parallel between the power supply terminal and the common node ND2. , BR5, BR6)>, and each of these branches has a series connected switch (<SW0, SW1, SW1x, SW2, SW2x>, <SW3, SW4, SW5, SW6>) and a resistor (<RR0, RR1, RR1x, RR2, RR2x>, <RR3, RR4, RR5, RR6>), and the switch is selectively switched by the control codes PCODE <0, 1, 1x, 2, 2x>, PCODE <3, 4, 5, 6>. In operation, the voltage level of the power supply terminal is transferred to the common node ND2 to form an ODT resistance value.

Here, the switches (<SW0, SW1, SW1x, SW2, SW2x>, <SW3, SW4, SW5, SW6>), when the power supply terminal is the power supply voltage VDDQ, control the power supply voltage VDDQ by the control code applied to the gate. When the power supply terminal is the ground voltage VSS, the power supply terminal may be configured as an NMOS transistor that transfers the ground voltage VSS to the common node ND2 by a control code applied to the gate. .

Specifically, the first resistor unit 112 sets the values of the resistors RR0, RR1, RR1x, RR2, and RR2x constituting the branch by the resistance value designation mode.

Here, the resistance value designation mode is used to set the value of each resistance (RR0, RR1, RR1x, RR2, RR2x) so that the difference in the ODT resistance value corresponding to the change of the control code PCODE, that is, the ODT resistance value with uniform bit resolution is formed. That's the way.

Meanwhile, the second resistor unit 114 sets the values of the resistors RR3, RR4, RR5, and RR6 constituting the branch in the resistance value sequential variable mode.

Here, in the resistance value sequential mode, an ODT resistance value in which the bit resolution, which is a difference between the ODT resistance values corresponding to the change of the control code PCODE, is gradually formed, is formed, and a constant value between the respective resistances RR3, RR4, RR5, and RR6 is formed. It is a setting method to have a ratio (for example, 2 times).

In detail, the first resistor unit 112 should form a seven-step ODT resistance value larger than the target resistance RT and having a uniform bit resolution. For example, when the bit resolution of the ODT resistance value formed in the first resistor unit 112 is ΔR, the ODT resistance values for each stage are RT + ΔR, RT + 2ΔR, RT + 3ΔR, RT + 4Δ. R, RT + 5ΔR, RT + 6ΔR, RT + 7ΔR, which may be represented by three branches BR0, BR1, and BR2 as shown in Table 1.

Hereinafter, in the table, "1" means turn-on of the branch and "0" means turn-off.

Step BR2 BR1 BR0 ODT resistance 7 0 0 One RT + 7 △ R 6 0 One 0 RT + 6 △ R 5 0 One One RT + 5 △ R 4 One 0 0 RT + 4 △ R 3 One 0 One RT + 3 △ R 2 One One 0 RT + 2 △ R One One One One RT + 1 △ R

Here, the branch BR2 is designated as the most significant bit (MSB) with the smallest resistance value, the branch BR0 is designated as the least significant bit (LSB) with the largest resistance value, and the branches BR0, BR1, and BR2 are binary sequences. When operating at, the resistance of each branch BR0, BR1, BR2 is obtained as shown in Table 2.

Step BR2 BR1 BR0 ODT resistance 7 0 0 RT + 7 △ R RT + 7 △ R 6 0 RT + 6 △ R 0 RT + 6 △ R 5 0

RT + 7 △ R RT + 5 △ R 4 RT + 4 △ R 0 0 RT + 4 △ R 3

0 RT + 7 △ R RT + 3 △ R 2

RT + 6 △ R 0 RT + 2 △ R One

RT + 7 △ R RT + 1 △ R

That is, one branch (RT + 7ΔR) for branch BR0, and two branches (RT + 6ΔR, (RT + 7ΔR) (RT + 5ΔR) / 2ΔR) for branch BR1. , Branch (BR2) has four types (RT + 4 △ R, (RT + 7 △ R) (RT + 3ΔR) / 4 △ R, (RT + 6ΔR) (RT + 2ΔR) / 4 Since resistors of ΔR and (RT + 5ΔR) (RT + ΔR) / 4ΔR) are required, a total of seven resistors are required.

Here, the resistance of the branch BR2 may be reduced to two types (RT + 4ΔR, (RT + 6ΔR) (RT + 2ΔR) / 4ΔR), which is a step 5 and 7 step. It causes a difference in the sum resistance. However, the difference is so small that it can be ignored.

For example, when the target resistance RT, that is, the reference resistance ZQ is 240 ohms and the bit resolution ΔR is 8 ohms, an ideal summing resistor of five and seven steps formed by four types of resistors The resistance difference between the value and the summed resistance value formed by the two abbreviated resistors is 1.7 ohms, which is sufficiently small compared to the bit resolution 8 ohms.

Therefore, as shown in Table 3, the first resistor unit 112 may include five branches BR0, BR1, BR1x, BR2, and BR2x that correspond one to one to five resistors. This is less than 7 the number of branches that bit resolution typically requires to form a constant seven ODT resistors.

Step BR2X BR2 BR1X BR1 BR0 ODT resistance One 0 0 0 0 RT + 7 △ R RT + 7 △ R 2 0 0 0 RT + 6 △ R 0 RT + 6 △ R 3 0 0

0 RT + 7 △ R RT + 5 △ R 4 0 RT + 4 △ R 0 0 0 RT + 4 △ R 5

0 0 0 RT + 7 △ R RT + 3 △ R 6

0 0 RT + 6 △ R 0 RT + 2 △ R 7

0

0 RT + 7 △ R RT + 1 △ R

Subsequently, since the second resistor unit 114 includes the target resistor RT, the ODT resistance value is smaller than the target resistance RT and the bit resolution is gradually variable, that is, the total ODT resistance value of eight steps is formed. Branches BR3, BR4, BR5, and BR6 may be represented.

The values of the resistances RR3, RR4, RR5, and RR6 of each of the branches BR3, BR4, BR5, and BR6 have a resistance ratio in which the resistance values are constant (double here) as shown in Table 4.

Step BR6 BR5 BR4 BR3 ODT resistance 8 RT 0 0 0 RT 9 RT 0 0 24RT 24 / 25RT 10 RT 0 12RT 0 12 / 13RT 11 RT 0 12RT 24RT 24 / 27RT 12 RT 6RT 0 0 6 / 7RT 13 RT 6RT OFF 24RT 24 / 29RT 14 RT 6RT 12RT 0 12 / 19RT 15 RT 6RT 12RT 24RT 24 / 31RT

Here, if the branch BR6 is set to the MSB having the smallest resistance value and the branch BR3 is set to the LSB having the largest resistance value, when they operate in a binary sequence, the resistance value of the branch BR6 is set to the target resistance RT. , Resistance values of the branches BR5, BR4, BR3 are set to 6 * RT, 12 * RT and 24 * RT, respectively.

Here, the reason why the resistance ratio of the branch BR6 and the branch BR5 is applied 6 times instead of 2 times is that the target resistance RT is represented by the state in which the upper two bits become larger (that is, 11000) in the conventional method (Fig. 2). Since the embodiment of the present invention is abbreviated to 1 bit, since the resistance corresponding to 2 bits and the parallel resistance value is RT is 3 / 2RT, 3 * RT, the branch BR5 becomes 6 * RT, which is 2 times 3 * RT.

When the bit resolution line of the ODT resistance value formed in the second resistor unit 114 is Δr, the bit resolution Δr gradually varies. Since the ODT resistance value formed in the second resistor unit 114 is smaller than the ODT resistance value formed in the first resistor unit 112, the bit resolution Δr is not larger than the bit resolution ΔR.

As shown in Table 5, the hybrid resistor circuit 110 includes first and second resistors 112 and 114 whose resistance values are set by different resistance variable modes, and the first and second resistors are controlled by the control code PCODE. Any one of the units 112 and 114 is selected to form the parallel sum resistance of the turned-on branches as the ODT resistance value, thereby adjusting the ODT resistance value so that the difference in the ODT resistance value, that is, the bit resolution has a value within a predetermined range. .

Step RB6 RB5 BR4 BR3 BR2X RB2 BR1X BR1 RB0 ODT resistance One 0 0 0 0 0 0 0 0 One RT + 7 △ R 2 0 0 0 0 0 0 0 One 0 RT + 6 △ R 3 0 0 0 0 0 0 One 0 One RT + 5 △ R 4 0 0 0 0 0 One 0 0 0 RT + 4 △ R 5 0 0 0 0 One 0 0 0 One

RT+3△R

RT + 3 △ R 6 0 0 0 0 One 0 0 One 0 RT + 2 △ R 7 0 0 0 0 One 0 One 0 One

RT + △ R 8 One 0 0 0 0 0 0 0 0 RT 9 One 0 0 One 0 0 0 0 0 24 / 25RT 10 One 0 One 0 0 0 0 0 0 12 / 13RT 11 One 0 One One 0 0 0 0 0 24 / 27RT 12 One One 0 0 0 0 0 0 0 6 / 7RT 13 One One 0 One 0 0 0 0 0 24 / 29RT 14 One One One 0 0 0 0 0 0 12 / 19RT 15 One One One One 0 0 0 0 0 24 / 31RT

Referring back to FIG. 4, the control circuit 120 that provides the control code PCODE for controlling the hybrid resistance circuit 110 includes a comparator 122, a counter 124, and a controller 126.

The comparator 122 compares the divided voltage VIN divided by the reference resistor ZQ and the ODT resistance value connected between the common node ND2 and the ground voltage terminal VSS with the reference voltage VREF and outputs a comparison signal COM corresponding to the result. do.

Here, the level of the reference voltage VREF is set to the VDDQ / 2 level, which is half of the power supply voltage terminal VDDQ level, which is the level of the divided voltage VIN when the ODT resistance value is the same as the reference resistance value ZQ.

The counter unit 124 outputs the counter signal COUNT which is increased or decreased by the comparison signal COM in synchronization with the clock CLK.

Here, the number of bits of the counter signal COUNT is preferably represented by 4 bits to represent the control code PCODE corresponding to one branch to the nine branches constituting the hybrid resistor circuit 110.

Referring to FIG. 6, the control unit 126 decodes the count signals COUNT <0: 3> and controls control codes PCODE <0, 1, 1x, 2, 2x, 3, which control turn-on of each branch as shown in Table 5 above. Decoding section 132 providing 4, 5, 6> and an output section controlling the output of control codes PCODE <0, 1, 1x, 2, 2x, 3, 4, 5, 6> by enable signal EN 134 is configured.

Here, the increase or decrease of the counter signal COUNT <0: 3> and the control codes PCODE <0, 1, 1x, 2, 2x, 3, 4, 5, 6> means an increase or decrease of the bit value.

The decoding unit 132 includes NAND gates NAND1 to NAND9, a NOA gate NOR1, and inverters INV1 to INV5, and the first or second resistor units 112 and 114 by the count signal COUNT <3>. ), And outputs control codes PCODE <0, 1, 1x, 2, 2x, 3, 4, 5, 6> for controlling the branch of the selected first or second resistors 112 and 114. do.

Specifically, when the count signal COUNT <3> is at the low level, the control code PCODE <0, 1, 1x, 2, 2x> for controlling the first resistor unit 112 by the count signal <0: 3>, that is, One or more of the output signals of the NAND gates NAND1, NAND2, NAND3, NAND5, and NAND6 are activated at a low level, and control codes PCODE <3, 4, 5, 6> for controlling the second resistor unit 114, that is, The output signals of the NAND gates NAND7, NAND8, and NAND9 and the inverter INV5 are all inactivated to a high level.

In other words, when the count signal COUNT <3> is at the low level, the NAND gate NAND1 inverts the count signal COUNT <0> to output the control code PCODE <0>, and the NAND gate NAND2 inverts the count signal. COUNT <0> and count signal COUNT <1> are combined to output control code PCODE <1x>, and NAND gate (NAND3) is combined with count signal COUNT <0: 1> and output control code PCODE <1>. The NAND gate NAND5 outputs the control code PCODE <2> by combining the output of the NOA gate NOR1 combining the count signal COUNT <0: 1> and the count signal COUNT <2>, and the NAND gate NAND6 The control code PCODE <2> is output by combining the inverted signal of the NOR gate NOR1 and the count signal COUNT <2>.

Since the NAND gates NAND7, NAND8, and NAND9 and the inverter INV5 have a low level in the count signal COUNT <3>, the control codes PCODE <3, which are deactivated to a high level regardless of the count signals COUNT <0: 2>. 4, 5, 6>

Here, the inverter INV1 inverts the count signal COUNT <0>, the NAND gate NAND4 couples the count signal COUNT <2: 3>, and the inverter INV2 inverts the output of the NAND gate NAND4. Inverter INV3 inverts the output of NOR gate NOR1, and inverter INV4 inverts the count signal COUNT <3>.

On the other hand, when the count signal COUNT <3> is at a high level, the control code PCODE <3, 4, 5, 6> that controls the second resistor unit 114 by the count signal <0: 3>, that is, the NAND gate ( One or more of the output signals of NAND7 to NAND9) and the inverter INV5 are activated at a low level, and the control codes PCODE << 0, 1, 1x, 2, 2x> for controlling the first resistor unit 112 are counted. Independent of signal COUNT <0: 2>, it is deactivated to a high level.

The output unit 134 shown in FIG. 4 is composed of inverters INV6 to INV15 and NOA gates NOR2 to NOR10. When the enable signal EN is at a high level, the control codes PCODE <0, 1, 1x, Outputs 2, 2x, 3, 4, 5, 6> to allow the ODT circuit to perform a calibration operation. If enable signal EN is at a low level, control code PCODE <0, 1, 1x, 2, 2x, 3, 4 , 5, 6> maintains the turn-off state of the ODT circuit.

Specifically, each NOR gate NOR2 to NOR10 combines the enable signal EN inverted by the inverter INV6 and the control codes PCODE <0, 1, 1x, 2, 2x, 3, 4, 5, 6>. Each inverter INV6 to INV15 inverts the output of the NOA gates NOR2 to NOR10 and outputs the control codes PCODE <0, 1, 1x, 2, 2x, 3, 4, 5, 6>.

If the ODT resistance value is less than the reference resistance ZQ, the control circuit 120 decreases the count signal COUNT <0: 3> by the corresponding comparison signal COM, decodes the count signal COUNT <0: 3>, and decodes the first resistor. The control code PCODE <0, 1, 1x, 2, 2x> controlling the unit 112 is reduced and output. At this time, all of the control codes PCODE <3, 4, 5, 6> controlling the second resistor unit 114 are output at a high level.

On the other hand, if the ODT resistance value is larger than the reference resistance ZQ, the count signal COUNT <0: 3> is increased by the corresponding comparison signal COM, and the second resistor unit 114 is decoded by decoding the count signal COUNT <0: 3>. Increase the control code PCODE <3, 4, 5, 6> to output. At this time, the control codes PCODE <0, 1, 1x, 2, 2x> for controlling the first resistor unit 112 are all output at a high level.

7 to 9 are graphs simulated to compare the ODT circuit according to the present invention with the prior art.

First, the technology used in the simulation is Hynix's A Technology Model Parameter, and the resistance of each branch is determined by the series summation resistance of the transistor used as a switch (here, PMOS transistor) and the resistance. In consideration of the linearity, the area of the layout, and the size tolerance standard of the parasitic capacitance, the ratio was configured to 3: 7 and the target resistance RT was set to 240 ohms.

The ODT circuit according to the prior art is composed of five branches (B1 ~ B5) having a resistance value set by the full binary weighting scheme of the resistor circuit (10 in Fig. 1), the upper two bits are turned on, that is, the control code PCCODE When <1: 5> is "11000", 240 ohms are output, and the average bit resolution of the 7-stage ODT resistor smaller than the target resistance RT is 8 ohms. Configure switch and resistor of B1 ~ B5).

Branch B <5> B <4> B <3> B <2> B <1>  Transistor Type TPMOS TPMOS TPMOS TPMOS TPMOS Width [um] 69.0 34.0 17.0 8.2 4.1 Length [um] 0.21 0.21 0.21 0.21 0.21 Resistor [Ω] 251.8 512.1 1052.2 2109.4 4241.8

The ODT circuit according to the embodiment of the present invention uses the resistance value designation mode such that the bit resolution ΔR of the 7-step ODT resistance value larger than the target resistance RT is 8 Ω. By the resistance value sequential mode, the branch (BR0, BR1, BR1x, BR2, BR2x) having the set resistance value and the average bit resolution Δr of the 7-stage ODT resistance value smaller than the target resistance RT become 8 Ω. Branches BR3, BR4, BR5, and BR6 having a set resistance value are configured, and switches and resistors of each branch are configured as shown in FIG.

Referring to FIG. 7, it can be seen that the ODT circuit according to the prior art and the ODT circuit according to the embodiment of the present invention have almost the same output characteristics of the target resistance of 240 Ω.

The divided voltage VIN by the ODT resistance value and the reference resistance ZQ, i.e., the voltages of the common nodes ND1 and ND2, show nonlinearity near the 0 (V) level, due to the nonlinearity of the transistor used as the switch. Although it is possible to improve by increasing the composition ratio of the ODT resistance, it is not preferable because the layout area and the parasitic capacitance may be too large.

Referring to FIG. 8, the ODT resistance values of the upper and lower stages of the target resistance RT calibrated in the ODT circuit according to the related art and the ODT circuit according to the embodiment of the present invention are shown as graphs G4 and G5. According to the ODT circuit, it can be seen that the linearity of the 7-step ODT resistance value larger than the target resistance RT (graph G5) is much superior to the linearity of the ODT resistance value output by the ODT circuit according to the prior art (graph G4).

9, the bit resolution of the ODT resistance values provided in the ODT circuit according to the prior art and the ODT circuit according to the embodiment of the present invention are shown as graphs G6 and G7.

That is, the bit resolution of the ODT resistance value corrected in the ODT circuit according to the prior art is non-linear as shown in the graph G6, while the bit resolution of the ODT resistance value corrected in the ODT circuit according to the embodiment of the present invention As can be seen from the calibration range, it remains constant at almost 8 ohms.

As described above, in the ODT circuit according to the exemplary embodiment of the present invention, when the ODT resistance value is smaller than the target resistance RT and the control code PCODE is reduced, the branches BR0, BR1, BR1x, and BR2 in which the resistance value is set by the resistance value designation mode. Since the ODT resistance value is calibrated through the first resistor part 112 including BR2x, the bit resolution is constant to improve the accuracy of the calibration.

In addition, in the ODT circuit according to the exemplary embodiment of the present invention, when the ODT resistance value is larger than the target resistance RT and the control code PCODE is increased, the branches BR3, BR4, BR5, and BR6 in which the resistance value is set by the resistance value sequential variable mode are used. By correcting the ODT resistance value through the second resistor unit 114 including), the accuracy of the calibration is improved.

Therefore, according to the present invention, there is an effect of improving the accuracy of calibration by an ODT circuit that provides an ODT resistance value in which the difference in the ODT resistance value is within a predetermined range corresponding to the change of the control code.

Claims (26)

A hybrid resistor circuit having a plurality of resistor sections to which at least two resistance variable modes are applied, and forming an on die termination resistor value as the resistor section selected by a control code; And A control circuit for comparing the on die termination resistance value with a reference resistance value and providing the control code for adjusting the on die termination resistance value to have a resistance value within a calibration range; On die termination circuit, characterized in that comprises a. The method of claim 1, The hybrid resistor circuit, A first resistor unit configured to form the on-die termination resistance value as a plurality of branches to which a resistance value designation mode is applied; And A second resistor unit configured to form the on-die termination resistor value as a plurality of branches to which the resistance value sequential variable mode is applied; On die termination circuit, characterized in that comprises a. The method of claim 2, The first and second resistor units, the branch is connected in parallel between the power supply terminal and the common node, each branch is on die termination circuit comprising a switch and a resistor connected in series. The method of claim 3, wherein The first resistor unit, An on-die termination circuit characterized in that the difference between the on-die termination resistance values corresponding to the change of the control code is set by the resistance value specifying mode. The method of claim 3, wherein And the second resistor unit is set by the resistance value sequential variable mode in which the value of the resistance is gradually varied in the difference between the on die termination resistance value corresponding to the change of the control code. The method of claim 5, wherein And the difference between the on die termination resistance values gradually decreases in response to an increase in the control code. The method of claim 3, wherein And the switch is a MOS transistor controlled by the control code applied to a gate to transfer the voltage level of the power supply terminal to the common node. The method of claim 7, wherein The power stage is a power supply voltage level, and the switch is a PMOS transistor. The method of claim 7, wherein The power stage is a ground voltage level, and the switch is an NMOS transistor. The method of claim 1, The control circuit, A comparator for comparing the on-die termination resistance with the reference resistance; A counter unit for outputting a count signal that increases or decreases in response to the comparison signal; And A controller for decoding the count signal and outputting the control code corresponding thereto; On die termination circuit, characterized in that comprises a. The method of claim 10, The control unit, A decoding unit for decoding the count signal; And An output unit for outputting the decoded signal by the enable signal to the control code; On die termination circuit, characterized in that comprises a. The method of claim 11, The decoding unit includes a decoding circuit corresponding to each of the resistor units, and one of the decoding circuits is selected by the count signal so that the decoding of the count signal by the selected decoding circuit is performed. Termination circuit. The method of claim 12, The decoding circuit, A first decoding circuit configured to generate a first decoded signal representing the on die termination resistance value with the first resistor unit to which the resistance value specifying mode is applied; And A second decoding circuit configured to generate a second decoded signal representing the on die termination resistance value as the second resistor unit to which the resistance value sequential variable mode is applied; On die termination circuit, characterized in that comprises a. The method of claim 13, And the first decoding circuit outputs the first decoded signal of more bits than the count signal by the combination of the count signals. The method of claim 13, And the second decoding circuit delivers the count signal and outputs the second decoded signal. A controller which compares an output resistance value with a target resistance value and outputs first and second control codes for adjusting the output resistance value to the target resistance value; A first resistor unit configured to increase the output resistance value to a uniform size by the first control code to adjust the target resistance value; And A second resistor unit adjusting the target resistance value by reducing the output resistance value to a variable size by the second control code; On die termination circuit, characterized in that comprises a. The method of claim 16, And the first and second resistor units include a plurality of branches connected in parallel between a power supply terminal and a common node, and each branch includes a switch and a resistor connected in series. The method of claim 17, And the first resistor unit sets the resistance value of each branch so that a change in the output resistance value output in response to a change in the first control code is uniform. The method of claim 17, And the second resistor unit is configured such that the resistance value between the branches has a constant magnification. The method of claim 16, And the switch is a MOS transistor controlled by the first and second control codes applied to a gate to transfer the voltage level of the power supply terminal to the common node. The method of claim 20, The power stage is a power supply voltage level, and the switch is a PMOS transistor. The method of claim 20, The power stage is a ground voltage level, and the switch is an NMOS transistor. The method of claim 16, The control unit, A first control unit outputting the first control code for controlling the first resistor unit by count signals; And A second control unit outputting the second control code for controlling the second resistor unit by the count signals; On die termination circuit, characterized in that comprises a. The method of claim 23, And the count signals are signals in which a signal obtained by comparing the output resistance value with the target resistance value is output in synchronization with a clock. The method of claim 23, And the first controller is configured to output the first control code of more bits than the count signal by combining the count signals. The method of claim 23, And the second control unit inverts the count signal and outputs the count signal to the second control code.

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