KR100878708B1 - Semiconductor package for high power transistors and method thereof - Google Patents

Abstract

A high power semiconductor device package is provided to increase matching impedance and to improve output property by using internal matching method with chip transistor die and chip capacitor. A high power semiconductor device package includes at least one or more capacitors(21, 22). A high power transistor(30) is arranged with the capacitor in a row. Input/output terminal lead wires(40, 50) are formed for input/output information of the high power transistor and the capacitor. The capacitor, the high power transistor, and the input/output terminal lead wires are electrically connected by a plurality of connection wires(111, 112, 113, 114). The capacitor and the transistor are connected by a three-dimensional range mode for a low input impedance matching of the high power transistor.

Description

High power semiconductor device package and method {SEMICONDUCTOR PACKAGE FOR HIGH POWER TRANSISTORS AND METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to high power transistors packaged in a package, and more particularly to an internal matching method using a chip transistor die made of a semiconductor, a wire and a chip capacitor. The present invention relates to a package structure and a method of designing the same for a high output transistor which increases output impedance and improves output characteristics to produce a higher output.

Recently, high integration and high performance are important in various mobile communication systems, broadcasting systems, and other communication systems. Therefore, the importance of high power amplifiers with higher output in the same area is increasing day by day.

In semiconductor package designs for such high-power amplifiers, transistor dies are typically used in high-integration circuits such as microwave monolithic integrated circuit (MMIC) processes and low temperature co-fired ceramic (LTCC) processes. Used via wire connection. In general, however, transistors are packaged and used on a printed circuit board (PCB). In this case, when the high output transistor has its own input impedance (low input impedance), it is difficult to design an external matching circuit. As a result, the design and manufacture of the package must use capacitors and leads to pull up the impedance to facilitate external matching. In order to pull up to impedance for high output, high inductance of the lead line of the package or the wire connected to the capacitor is required at the input terminal portion of the transistor.

However, in the case of the conventional high output transistor, the area that can be used in the package is limited, so the package design method through the wire connection method of the stepping stone type (hereinafter referred to as "SST"), which is used mainly in the package, has a high output. Since the inductance implemented by the length of the first connection line connected to the transistor input terminal side, which has a great influence, is small, the output cannot be made higher and the output is determined by the limited package area.

That is, in the package design method using SST, which is mainly used in the past, it is difficult to realize inductance for high output due to the limited package area. Therefore, there is a limit to the performance improvement of the high output transistor by internal matching. Many also had limitations in the implementation of matching to obtain higher output in a given package area. As a result, conventional high-power package transistor consumers have a limited-output package to obtain output through external matching. However, since this is an output optimization after implementation of the high-output amplifier circuit by external matching, there is a problem that the maximum output at the high-output package transistor level cannot be obtained before the circuit implementation.

1 is a top view of a package connected by a connecting line between a transistor die and a capacitor and a package lead used to implement a conventional high power transistor package. Referring to the configuration of a conventional high output transistor package with reference to FIG. 1 above, first, since the input impedance seen from the input terminal lead wire 40 is nearly 0 ohm (ohm), the at least one capacitor ( 21, 22) and the inductors 11, 12, 13, and 14 of the connecting line must be used to pull up the impedance to a high impedance favorable for external matching.

At this time, the capacitors 21 and 22 in the package inner substrate 70 provided on the package fixing metal frame (metal frame or metal base) 80, in order to pull up to a high impedance favorable for external matching as shown in FIG. The impedance value is increased by connecting the transistor die 30 and the input / output terminal lead wires 40 and 50 to the connection lines 11, 12, 13, and 14. In this case, the input / output terminal lead wires 40 and 50 are placed on a substrate 60 for connection with an input / output terminal composed of a ceramic-based substrate such as alumina (Alumina, SiO ₂ ) or another type of dielectric substrate. Consideration should be given to the low impedance of the transmission line. The connecting lines 11, 12, 13, and 14 are the elements which have the greatest influence on the output characteristics. In particular, the longer the connecting line 13 is first connected to the input terminal of the transistor die 30, the larger the inductance L3 due to this becomes. The high input impedance of the jitter can be obtained, thus allowing the high output transistor to have high output characteristics.

2 is a view showing in three dimensions the connection line connection of the SST method implemented in FIG. Each of the connecting lines 11, 12, 13, and 14 connects the input / output terminal input / output terminal lead wires 40 and 50 and the capacitors 21 and 22 and the transistor die 30 placed on the provided package inner substrate 70. It is connected in the form of a stepping bridge. It can be seen that the input / output terminal lead wires 40 and 50 lie on the substrate 60 for connection with the input / output terminals.

3 is an enlarged view of a method for connecting a connection line of the SST method implemented in FIG. 1. Each connection line 11, 12, 13, 14 connects the input / output terminal lead wires 40, 50, the capacitors 21, 22, and the transistor die 30 in an SST manner. When the SST method is used, the length of the connecting line 13 is somewhat limited due to a given area of the provided substrate 70 inside the package. The connection line indicated by (13) has a problem that the inductance L3 and the connection line which has the greatest influence on the impedance of the high output package transistor, but due to the limited area, sufficient inductance cannot be obtained.

FIG. 4 is a cross-sectional view of the SST type high output transistor package of FIG. 1. As shown in FIG. 4, it can be seen that the connection lines 11, 12, 13, and 14 are connected in the form of a stepping bridge, and the input / output terminal lead wires 40 and 50 are connected to the input / output terminals 60. It is connected to the elements inside the package through the bonding line.

FIG. 5 is an equivalent circuit diagram of a high output transistor package implemented with the SST of FIG. 1. As shown in FIG. 5, in the equivalent circuit, the equivalent circuits are replaced with the equivalent circuits by replacing the connection lines 11, 12, 13, and 14 shown in FIG. 1 with the corresponding inductors L1, L2, L3, and L4. Can be represented. The capacitors 21, 22 in the package were replaced with capacitors C1, C2, and the connecting lines 11, 12, 13, 14 were replaced with inductors L1, L2, L3, L4. Transistor die 30 has been replaced with a transistor element symbol and a TR mark. The input / output connections located at the left and right sides of the circuit are connection lines to the outside of the package by the input / output terminal lead wires 40 and 50 located on the connection board 60 to the input / output terminals.

However, as shown in FIGS. 2 to 5 including FIG. 1 above, in a package for a high output transistor, since the capacitor occupies a relatively large area in the package, the distance from the transistor to the capacitor is not sufficiently secured. There was also a problem that was not sufficiently secured. That is, the inductance of the first connection line starting from the transistor input terminal side has a great effect on the improvement of output characteristics. In the case of the existing SST, the sufficient connection line length is not secured at the connection lines 11, 12, 13, and 14 due to the limited area. As a result, there was a problem that it could not realize sufficient inductance.

Therefore, the present invention was devised to improve the output characteristics of the high output transistor due to the limitation of the package area in the conventional high output transistor package, and is different from the conventional connection line connecting method, SST. The present invention provides a semiconductor package structure and a high output transistor package design method for a high output transistor by improving the output characteristics of the high output transistor compared to the conventional SST method by implementing the connection line connection method of ").

The present invention described above is a package for a high output semiconductor device, comprising: first and second capacitors arranged in a row, high output transistors arranged in a line spaced apart from the second capacitor, and the first capacitor and the high output transistor. An input / output lead wire for input / output information, and the first and second capacitors, a high output transistor, and an input / output lead wire are respectively connected to each other, and the first and second capacitors are used to match the low input impedance of the high output transistor. And a plurality of connection lines formed to have the longest connection length between the high output transistors.

In addition, the present invention provides a package method for a high output semiconductor device, comprising the steps of arranging the first and second capacitors in a line in the substrate inside the package, and arranging the high output transistors in a line spaced apart from the second capacitor at a predetermined distance; And disposing input / output leads for input / output information of the first capacitor and the high output transistor on both sides of the first capacitor and the high output transistor, respectively, and using the plurality of connection lines, the first and second capacitors and the high output. Connecting the transistor and the input / output lead to each other, and connecting the first and second capacitors to have the longest connection length for the low input impedance matching of the high output transistor.

In the present invention, in the semiconductor package design for a high output transistor, by connecting the capacitor and the high output transistor in the package by the MCT method to form the length of the connection line between the capacitor and the high output transistor to the longest within the limited package area, necessary for high output matching By implementing a large inductance, it is possible to obtain a higher output than a conventional SST even in the same package area. In addition, since the high output can be obtained using the same size package, there is an advantage that it can be widely applied in the field of packaging of semiconductor devices requiring high power as well as various wireless communication device fields.

Hereinafter, with reference to the accompanying drawings will be described in detail the operating principle of the present invention. In the following description of the present invention, when it is determined that a detailed description of a known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. Terms to be described later are terms defined in consideration of functions in the present invention, and may be changed according to intentions or customs of users or operators. Therefore, the definition should be made based on the contents throughout the specification.

Looking at the specific core technical aspect of the present invention, in the semiconductor package design for a high output transistor, by connecting the capacitor and the high output transistor in the package by MCT method to form the longest connection line between the capacitor and the high output transistor in the limited package area By implementing a large inductance required for high output matching, the present invention can be easily achieved through a technology of obtaining a higher output than a conventional SST even in a given package area.

6 illustrates a semiconductor package structure for a high power transistor of a three-dimensional crossover method according to an embodiment of the present invention.

As shown in FIG. 6, in the package structure of the present invention, the transistor dies 30, the capacitors 21 and 22, and the input / output terminal lead wires 40 and 50 are connected to the connection lines 111, 112, 113, and 114. By using the connection, it indicates that the connection by the MCT method instead of the conventional SST method.

At this time, it should be noted that in the package structure of the present invention, the positions of the capacitors C1 (21) and C2 (22) are different from the structure shown in FIG. In addition, as shown in FIG. 6, it can be seen that the connection lines 111, 112, 113, and 114 connect the capacitor and the TR element in a three-dimensional crossover manner rather than a stepping bridge type.

That is, although the connection lines 112 and 114 connecting the high output transistor and the capacitor are the same as the connection lines 12 and 14 in the SST method shown in FIG. 1, the connection lines 111 and 113 of FIG. 6 are shown in FIG. 1. It can be seen that it is much longer than (11, 13). This means that the inductance can be sufficiently large as the length of the connecting line is secured. The results are shown separately in the inductance according to the connecting line length in Figures 12 and 13 described later.

FIG. 7 illustrates a three-dimensional view of a semiconductor package structure for an MCT type high output transistor implemented in FIG. 6. As shown in FIG. 7, in the present invention, each of the connecting lines 111, 112, 113, and 114 is disposed on the input / output terminal lead wires 40 and 50 and the capacitor 21 placed on the package inner substrate 70. 22) The transistor die 30 is connected in a three-dimensional crossover fashion. Accordingly, unlike the SST illustrated in FIG. 2, the MCT of the present invention can implement longer connection lines 111 and 113 regardless of a given package area and longer than the SST.

FIG. 8 is an enlarged view of a connection line connection method of the MCT method implemented in FIG. 6. Referring to FIG. 8 above, each of the connecting wires 111, 112, 113, and 114 is disposed on the input / output terminal lead wires 40 and 50 and the capacitors 21 and 22 and the transistor die placed on the provided package area 70. It can be seen that (30) is connected in a three-dimensional cross format.

In other words, the connection line 113 connected to the transistor die 30 is not connected to the capacitor C1 21 that is located nearby, but is connected to the capacitor C2 22 that is far apart. As such, when the connection between the capacitor and the high output transistor is implemented through the MCT method, the length of the connection line 113 in the package inner substrate 70 may be longer than that of the case manufactured through the conventional SST method. . Accordingly, the length of the connection line connecting the elements can be designed to be as long as possible even in the limited area of the package through the MCT method to realize sufficient inductance in the connection line connecting the elements due to the limited area of the package in the conventional SST method This difficult problem can be solved.

FIG. 9 is an enlarged view of a connection line connecting portion of the three-dimensional view of the semiconductor package illustrated in FIG. 7. In fact, as shown in FIG. 7 above, a plurality of connecting lines are arranged in parallel, and in FIG. 9, only one is shown at each position for convenience of explanation and understanding. However, the technical idea of the connecting line connecting method proposed in the present invention is the same regardless of the number of parallel connecting lines. As shown in FIG. 9, in the semiconductor package for the high output transistor of the present invention, the connection lines 111, 112, 113, and 114 connecting the elements are three-dimensionally intersected, and the two capacitors 21, 22 and the input // It can be seen that the output terminal lead wires 40 and 50 and the transistor die 30 are connected.

FIG. 10 illustrates a cross-sectional view of the MCT semiconductor package structure implemented in FIG. 6. As shown in FIG. 10, the connection line 113 connected to the transistor die 30 is not connected to the capacitor C1 21 located nearby, and is then connected to the capacitor C2 22. Accordingly, it can be seen that the length of the connection line 113 can be secured when compared with the package condition of the same size compared to FIG. 4 showing the connection of the conventional SST method.

11 is an equivalent circuit diagram of a semiconductor package for a high output transistor implemented by the MCT method. In the equivalent circuit illustrated in FIG. 11, the plurality of connection lines 111, 112, 113, and 114 illustrated in FIG. 6 may be represented by equivalent inductances. That is, the symbols 21 and 22 in the package are replaced with C1 and C2, respectively, and the connecting lines 111, 112, 113 and 114 are replaced with the corresponding inductors L1, L2, L3 and L4, respectively. Through the equivalent circuit can be represented. Transistor die 30 has been replaced with a transistor element symbol and a TR mark.

FIG. 12 is a table for showing an increase in inductance caused by a connection line as the length of the connection line in the semiconductor package increases. The connection line used as an example in the present invention may be used as gold, Au, or aluminum. Al) is a wire of 0.5 to 1.7 mils in diameter. In this case, 1 mil is 1/1000 inch, which corresponds to 0.0254 mm, and the diameter range of the connection line is only mentioned as a preferred embodiment, and a thinner or thicker wire outside the range may be used. FIG. 13 is a graph illustrating inductance according to the length of the connection line shown in FIG. 12. As shown in the graph of FIG. 13, it can be seen that as the length of the connecting line increases, the inductance increases in a linear proportional relationship.

FIG. 14 illustrates an application of the MCT scheme proposed in the present invention, in which an input source impedance of only a transistor die is applied to a gallium nitride (GaN) high output transistor die having a gate length of 16 mm at a frequency of 1000 MHz. The source impedance of the SST package and the source impedance of the proposed MCT package are shown in the Smith chart. In the present invention, the gallium nitride transistor is described as an example of a high output transistor for convenience of description, but a high output transistor made of any material including gallium nitride may be equally applicable.

FIG. 15 is an enlarged view of a dotted square portion of the Smith diagram shown in FIG. 14. Referring to FIG. 15, the source impedance of the package configured by the SST method and the package configured by the MCT method compared to the input source source impedance of only the transistor die. You can see the change in source impedance. That is, it can be seen that the source impedance of the package configured by the MCT scheme has changed more than the source impedance when the package is configured by the SST scheme. In this case, the difference in source impedance shown in FIG. 15 may appear to be insignificant in source impedance change, but the output power characteristic of the high output package transistor may be changed due to the input impedance change of several ohms only with the above difference. It is clear to those skilled in the art that this can make a big difference.

FIG. 16 is a diagram illustrating an improvement in output power characteristics of a high output package transistor according to the result of FIG. 15. The same input is applied to a gallium nitride transistor (GaN Transistor) having a gate length of 16 mm, and the frequency is 1000 to 1400 MHz. In this case, the output power characteristics of the high output package transistor are compared. Through the above graph, it can be seen that the output power when the package is configured by the MCT method is about 2dBm higher than the output power when the package is configured by the conventional SST method.

As described above, in the present invention, in the semiconductor package design for the high output transistor, by connecting the capacitor in the package and the high output transistor by the MCT method to form the length of the connection line between the capacitor and the high output transistor the longest within the limited package area, high power By implementing the large inductance required for the matching, higher outputs can be achieved compared to conventional SST even in the same package area.

Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. That is, the MCT package design and fabrication method of the present invention is not limited to high-power package transistors, but in all cases in which various semiconductor devices are mounted in a package, the inductance is increased by increasing the length of the connection line within a limited package area. If the purpose is to increase the same can be applied. Therefore, the scope of the invention should be determined by the claims rather than by the described embodiments.

1 is a plan view of a high-output semiconductor device package structure of the conventional SST method,

FIG. 2 is a perspective view of the semiconductor package structure of FIG. 1; FIG.

3 is an enlarged view illustrating connection lines between devices in a conventional SST semiconductor package structure;

4 is a cross-sectional view of the semiconductor package structure of FIG. 1;

5 is an equivalent circuit diagram of a conventional high power semiconductor device package of the SST method;

6 is a plan view of a high output semiconductor device package structure of the MCT method according to an embodiment of the present invention;

7 is a perspective view of the semiconductor package structure of FIG. 6;

8 is an enlarged view illustrating connection lines between devices in an MCT semiconductor package structure according to an embodiment of the present invention;

9 is a perspective view of a package structure showing only one connection line of the semiconductor package structure of FIG. 6;

10 is a cross-sectional view of the semiconductor package structure of FIG. 6;

11 is an equivalent circuit diagram of an MCT type high power semiconductor device package according to an embodiment of the present invention;

12 is an exemplary inductance value according to the length of the connection line between the elements in the package according to an embodiment of the present invention,

13 is an exemplary diagram illustrating a change in inductance according to a length of a connection line between devices in a package according to an exemplary embodiment of the present invention.

14 is a Smith diagram showing a change in source impedance between SST and MCT schemes according to an embodiment of the present invention;

15 is an enlarged view illustrating the Smith diagram of FIG. 14;

16 is a diagram illustrating output power characteristics of a high output transistor in a package structure between SST and MCT schemes according to an exemplary embodiment of the present invention.

Claims (19)

A package for high power semiconductor devices, One or more capacitors, A high output transistor arranged in line with the capacitor, An input / output terminal lead wire for input / output information of the capacitor and the high output transistor; A plurality of connection lines connecting the capacitors, the high output transistors, and the input / output terminal leads to each other, and connecting the capacitors and the transistors in a three-dimensional crossover manner for low input impedance matching of the high output transistors. High power semiconductor device package comprising a. The method of claim 1, The plurality of connection lines, A high power semiconductor device package, characterized in that formed from gold or aluminum with a diameter of 0.5 to 1.7 mils. The method of claim 1, The high output transistor, A high power semiconductor device package, characterized by a gallium nitride transistor. The method of claim 1, The capacitor and the high output transistor, A high power semiconductor device package characterized in that it is placed in a package inner substrate provided on a package fixing metal frame. The method of claim 1, The input / output terminal lead wire, A high power semiconductor device package comprising a ceramic substrate comprising alumina or a connecting substrate composed of another type of dielectric substrate. A package for high power semiconductor devices, The first and second capacitors arranged in a line, A high output transistor arranged in a line spaced apart from the second capacitor at a predetermined interval; An input / output terminal lead wire for input / output information of the first capacitor and the high output transistor; Connecting the first and second capacitors, the high output transistor, and the input / output terminal lead wires to each other, and connecting the first and second capacitors and the high output transistor in a three-dimensional crossover manner for low input impedance matching of the high output transistor. Multiple connections High power semiconductor device package comprising a. The method of claim 6, The plurality of connection lines, A first connection line connecting one end of the input terminal lead wire and the second capacitor; A second connection line connecting the first and second capacitors; A third connection line connecting one end of the first capacitor to one end of the high output transistor; A fourth connection line connecting one end of the high output transistor to an output terminal lead wire High power semiconductor device package comprising a. The method of claim 7, wherein The plurality of connection lines, A high power semiconductor device package, characterized in that formed from gold or aluminum with a diameter of 0.5 to 1.7 mils. The method of claim 6, The high output transistor, A high output semiconductor device package, characterized in that the gallium nitride transistor. The method of claim 6, The first and second capacitors and the high output transistor, A high power semiconductor device package characterized in that it is placed in a package inner substrate provided on a package fixing metal frame. The method of claim 6, The input / output terminal lead wire, A high power semiconductor device package comprising a ceramic substrate comprising alumina or a connecting substrate composed of another type of dielectric substrate. As a package method for a high output semiconductor device, (a) arranging one or more capacitors and the high power transistor in a line within the package inner substrate; (b) disposing an input / output terminal lead wire for input / output information of the capacitor and the high output transistor on both sides of the capacitor and the high output transistor, (c) connecting the capacitor, the high output transistor, and the input / output terminal lead wires to each other using a plurality of connection lines, and connecting the capacitor and the transistor in a three-dimensional crossover manner for low input impedance matching of the high output transistor; High power semiconductor device package method comprising a. The method of claim 12, The high output transistor, A high output semiconductor device packaging method comprising a gallium nitride transistor. The method of claim 12, The input / output terminal lead wire, A method for packaging a high power semiconductor device comprising a ceramic substrate comprising alumina or a connecting substrate composed of another type of dielectric substrate. As a package method for a high output semiconductor device, (a ') disposing the first and second capacitors in a line in the package inner substrate; (b ') arranging the high output transistors in a line spaced apart from the second capacitor by a predetermined distance; (c ') disposing an input / output terminal lead wire for input / output information of the first capacitor and the high output transistor on both sides of the first capacitor and the high output transistor; (d ') connecting the first and second capacitors, the high output transistor, and the input / output terminal lead wires to each other by using a plurality of connection lines, and the first and second capacitors for low input impedance matching of the high output transistor. Connecting transistors in a three-dimensional crossover manner High power semiconductor device package method comprising a. The method of claim 15, The step (d ') may include: (d'1) connecting the input terminal lead wire and one end of the second capacitor with a first connection line; (d'2) connecting the first and second capacitors with a second connection line; (d'3) connecting one end of the first capacitor and one end of the high output transistor with a third connection line; (d'4) connecting one end of the high output transistor and an output terminal lead with a fourth connection line High power semiconductor device package method comprising a. The method of claim 15, The high output transistor, A high output semiconductor device packaging method comprising a gallium nitride transistor. The method of claim 15, The first and second capacitors and the high output transistor, A method for packaging a high power semiconductor device, characterized in that it is placed in a package inner substrate provided on a package fixing metal frame. The method of claim 15, The input / output terminal lead wire, A method of packaging a high power semiconductor device comprising a ceramic substrate comprising alumina or a connecting substrate composed of another type of dielectric substrate.

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