KR100870752B1 - Non-volatile memory device and control method therefor - Google Patents

Abstract

In the erasing operation, the first decoder groups 20 (i) and 21 (i) (i = 1 to m) of the sector to be erased are connected to the low voltage power supply terminal VL via the switches B and 50 and 51, respectively. The negative voltage supply line VM is connected, and the sub bias to the local word line is supplied. The first negative voltage supply line VM is connected to the level shift circuit 4 and is higher than the second negative voltage VMP output from the negative voltage generation circuit 3 via the second negative voltage supply line VMP. It is level shifted with the voltage. The upper decoder group 10 is connected to the low voltage power supply terminal VL via a switch A and a second negative voltage supply line VMP. All global word lines GWL0 (i) (i = 0 to m) are biased to the second negative voltage VMP by the low-level active signal ACTBO (i) input to the upper decoder group 10, and local The voltage is biased to a lower voltage level than the first negative voltage VM, which is a bias voltage to the word line.

Nonvolatile Memory, Negative Voltage Generator, Level Shifter

Description

Nonvolatile Memory and Control Method {NON-VOLATILE MEMORY DEVICE AND CONTROL METHOD THEREFOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the application of bias voltages in nonvolatile memory devices, and more particularly to a technique for efficiently applying internally generated negative bias voltages.

In Patent Document 1, as shown in FIG. 10, when the word line Xi is driven by the driver 280, a predecoder (not shown) outputs a predecoder signal VA decoded to the driver 280. do. The driver 280 includes two P-channel transistors 780 and 800 connected between the multiplex signal MUXi and the earth. The gate of the P channel transistor 780 is connected to VA, and the gate of the P channel transistor 800 is connected to a fixed voltage VN. The node 810 is connected to a word line Xi and a charge pump circuit 320, which is attached to the driver 280. When the sub bias is applied to the word line Xi, VA is set at a high level to prevent the sub bias from leaking through the P-channel transistor 780.

Patent Document 1: Japanese Unexamined Patent Publication No. Hei 7-37396

However, as the capacity increases, the word lines Xi become long wirings, and when a large number of memory cells are connected, the word lines Xi have large wiring capacitances. In order to apply a high voltage to the word line Xi at high speed, it is necessary to have sufficient current supply capability as the P-channel transistor 780, and the size of the transistor must be increased. However, this is a problem because it is contrary to the demand for high integration of nonvolatile memory devices, which are required for large capacity. In addition, an increase in the parasitic capacitance and the like accompanied by an increase in the transistor size may cause a high-speed response to be hindered.

In addition, the large-size P-channel transistor 780 has a large gate capacitance, and the driver capability of a predecoder (not shown) for driving these gates is also large. Similarly, this is a problem because it is contrary to the demand for high integration of a nonvolatile memory device which is required with a large capacity. It is also a problem because it can be a factor that hinders high-speed response.

In order to avoid the above problem, it is conceivable to have a configuration including an N-channel transistor having a higher current driving capability in place of the P-channel transistors 780 and 800. The structure is shown in FIG. FIG. 11 also shows a bias relationship during an erase operation in which a sub bias is applied to the word line WL. N-channel transistors T1 and T2 are provided in place of the P-channels 780 and 800 in Patent Document 1.

Application of a sub-bias (e.g., -9V) to the word line WL sets the gate signal GWLB to a low level (e.g., 0V), and then a sub-bias (e.g., to the source terminal XDS). For example, -9V). At this time, a sub-bias (for example, −9 V) having the same potential as that of the word line WL is applied to the gate signal GWL of the N-channel transistor T1. In this case, the drain signal VWL is at a low level (for example, 0V). The N-channel transistor T1 is biased in a non-conductive state with the gate-source voltage VGS as zero volts.

In accordance with the increase in capacity, in order to realize a faster access operation, the voltage supply capability to the word line WL must be sufficiently secured, but the size of the transistor is limited according to the necessity to improve the integration degree. Therefore, the N-channel transistor T1 is used to secure driving capability by miniaturization and low threshold voltage. For this reason, the leak current may flow even in the state of VGS = 0V. It is the so-called tailing current. Since the erase operation is performed for each sector or sector group which is a predetermined block in the memory cell array, it is conceivable that the number of word lines in a sector increases as the capacity increases. Although the tailing current flowing through the individual N-channel transistors T1 is small, the tail bias of the word line WL may increase due to the tailing current flowing through the plurality of N-channel transistors T1. Since the supply capability of the sub-bias generated by the operation of the charge pump from the positive voltage supply such as the supply voltage depends on the performance of the charge pump circuit, it may not be possible to maintain a predetermined negative voltage according to the inflow current. There is concern. A memory cell of a nonvolatile memory device which performs an erase operation on the condition that a predetermined sub bias is applied may not be completed as the voltage value of the sub bias increases. It is also a problem that normal data storage is not secured. In addition, in order to secure the ability to absorb the tailing current, the charge pump circuit must be large-scale circuit configuration, which is a problem.

In particular, when the fast chip erase (FCER) mode or the accelerated mode (ACC mode), which is a function of collectively erasing a large number of sectors, is provided, the number of word lines WL to which sub biases are applied is further increased. In addition, in a plurality of N-channel transistors T1, a tailing current flows. It is a problem that it becomes increasingly difficult to keep the sub bias at a predetermined voltage.

SUMMARY OF THE INVENTION The present invention has been made to solve at least one problem of the prior art, by reducing the leakage current and / or supplying the bias voltage when applying a negative bias voltage generated inside the nonvolatile memory device. It is an object of the present invention to provide a nonvolatile memory device and a control method thereof in which the bias voltage can be efficiently and reliably supplied by improving as necessary.

The nonvolatile memory device according to the first aspect of the present invention, which is provided to attain the above object, is provided between a first terminal and a word line, and supplies a positive voltage supplied to the first terminal to the word line by conduction. When supplying the first negative voltage to the word line with the first N-type transistor and the first N-type transistor being non-conductive, the first negative voltage having a lower voltage than that of the first negative voltage to the control terminal of the first N-type transistor. It characterized in that it comprises a negative voltage generator for supplying.

In addition, the control method of the nonvolatile memory device according to the first invention includes a first N-type transistor provided between the first terminal and the word line and conducting when supplying a constant voltage to the word line rather than the first terminal. A control method of a nonvolatile memory device, the method comprising: supplying a first negative voltage to a word line and supplying a first negative voltage to a word line, wherein the first negative voltage is lower than the first negative voltage to the control terminal of the first N-type transistor; And supplying a second negative voltage of the voltage.

In the nonvolatile memory device and control method thereof of the first aspect of the present invention, a first N-type transistor is provided between the first terminal and the word line, and is provided with a first N-type transistor that is turned on when a constant voltage is supplied from the first terminal to the word line. When supplying the first negative voltage to the line, the control terminal of the first N-type transistor is supplied with a second negative voltage having a lower voltage than the first negative voltage.

Further, the nonvolatile memory device according to the second aspect of the present invention further provides a negative voltage generator for supplying negative voltage to the word line and a predetermined load condition in which the power supply to the negative voltage generator is increased in the negative voltage generator. And a power switching unit for switching to a high voltage power source having a high voltage level.

Further, the nonvolatile memory device according to the third aspect of the invention has a charge pump circuit, and includes a negative voltage generator for supplying negative voltage to a word line, and a charge pump operation according to a predetermined load condition in the negative voltage generator. It is characterized by including a frequency switching unit for switching the operating frequency in the higher frequency.

In addition, the nonvolatile memory device according to the fourth aspect of the present invention has a negative voltage generator that supplies a negative voltage to a word line, and generates a negative voltage instead of the negative voltage generator according to a predetermined load condition in the negative voltage generator. In addition to the unit, an auxiliary negative voltage generating unit for starting the operation is provided.

Further, the control method of the nonvolatile memory device according to the second invention includes the steps of selecting a word line, supplying a negative voltage to the selected word line, and in the case where the number of selected word lines is more than a predetermined number. Increasing the supply capability of the voltage.

In the nonvolatile memory device of the second invention, when the negative voltage is supplied to the word line by the negative voltage generating unit, the negative voltage generating unit is supplied in accordance with a predetermined load condition in which the load of the negative voltage generating unit is increased by the power switching unit. The power supply is switched to the high voltage power supply compared to the normal power supply.

In the nonvolatile memory device of the third aspect of the present invention, when the negative voltage is supplied to the word line by the negative voltage generator, the negative voltage generator is provided in accordance with a predetermined load condition in which the load of the negative voltage generator increases. The operating frequency of the charged pump circuit is switched to a higher frequency than the normal frequency.

In the nonvolatile memory device of the fourth aspect of the invention, when the negative voltage is supplied to the word line by the negative voltage generator, the negative voltage generator replaces the negative voltage generator or the negative voltage generator according to a predetermined load condition in which the load of the negative voltage generator increases. In addition to this, the auxiliary negative voltage generator is activated.

In the control method of the nonvolatile memory device of the second aspect of the invention, when the word line is selected and the negative voltage is supplied, the number of word lines to be selected is increased by a predetermined number or more, thereby increasing the supply capability of the negative voltage.

Effects of the Invention

According to the nonvolatile memory device and the control method of the first aspect of the invention, the second negative voltage having a lower voltage than the first negative voltage supplied to the word line is supplied to the control terminal of the first N-type transistor. In the first N-type transistor that is conducting when a higher voltage level is supplied to the control terminal than other terminals, the reverse bias is applied to the terminal to which the word line is connected with the voltage of the control terminal being a constant voltage. The N-type transistor is surely turned off. As a result, even when a leakage current such as a tailing current flows when the first N-type transistor is a low threshold voltage and there is no voltage difference between the other terminal and the control terminal, the first N-type transistor is reliably turned off. The leakage current can be reduced. The first negative voltage of the word line can be reliably supplied.

Further, according to the nonvolatile memory devices of the second to fourth inventions, the operating frequency of the charge pump circuit provided in the negative voltage generator is set to a high voltage according to a predetermined load condition in which the load increases. By setting the high frequency and activating the auxiliary negative voltage generator, it is possible to increase the supply capacity of the negative voltage. If the state in which the leakage current such as the tailing current is increased is set as a predetermined load condition, the supply capability of the negative voltage can be increased as the leakage current increases, and the negative voltage is supplied to the word line despite the increase of the leakage current. Can be surely performed.

Further, according to the control method of the nonvolatile memory device of the second invention, since the negative voltage is supplied, when the number of selected word lines is more than a predetermined number, the supply capability of the negative voltage can be enhanced. Since there is a leak current for each word line, when the number of selected word lines becomes more than a predetermined number and the total sum of the leak currents increases, the supply capability of the negative voltage can be increased, and thus the leak currents are increased to the word lines. Supply of negative voltage can be reliably performed.

Thus, according to the present invention, it is possible to reliably supply the first negative voltage or negative voltage to the word line, and reliably perform circuit operations such as an erase operation in which the negative voltage is supplied to the word line. .

By reducing the leakage current when the negative voltage is supplied to the word line, the negative voltage supply capability of the negative voltage generating portion can be minimized, and the circuit scale can be reduced. In addition, since the negative voltage supply capability can be increased as necessary, it is not necessary to provide unnecessary voltage supply capability, the circuit current consumption can be reduced, and the circuit scale can be reduced.

1 is a diagram showing a decoder arrangement in a sector and a row direction of a nonvolatile memory device.

Fig. 2 is a circuit block diagram showing a decoder group in a row direction and a control circuit thereof in the first embodiment.

3 is a circuit diagram illustrating an upper / lower decoder.

4 is a diagram illustrating a voltage bias condition in a nonvolatile memory device.

5 is a circuit block diagram for generating first and second negative voltages.

FIG. 6 is a circuit block diagram showing a first specific example of the second embodiment. FIG.

7 is a circuit block diagram illustrating a second specific example of the second embodiment.

8 is a circuit block diagram showing a first specific example of the third embodiment.

9 is a circuit block diagram illustrating a second specific example of the third embodiment.

Fig. 10 is a circuit diagram showing a decoder in the row direction in the background art.

Fig. 11 is a circuit diagram showing a decoder in a row direction in another background art.

** Explanation of symbols for main parts of drawings **

3 negative voltage generating circuit

4 level shift circuit

5 switch (A)

6 Predecoder (A)

7 regulator circuit

10, 11 upper decoder group 10 (i), 11 (i) (i = 1 to m) upper decoder

20 (i), 21 (i), 22 (i) (i = 1 to m) lower decoder group

20 (i) (x), 21 (i) (x), 22 (i) (x) (i = 1 to m) (x = 1 to n) sub decoder

31 Auxiliary Negative Voltage Generator Circuit

50, 51 switch (B)

60, 61 predecoder (B)

81 ACC power terminal

82 VCC Power Terminal

GWL0 (i) / GWLB0 (i), GWL1 (i) / GWLB1 (i) (i = 1 to m) global word lines

NEGP low voltage supply line

PPS Ground Voltage Supply Line

SO0 to S10 sectors

VM 1st negative voltage supply line

VMP 2nd negative voltage supply line

VPX constant voltage supply line

VWL0 (x), VWL1 (x) (x = 1 to n) predecode lines

XDS0, XDS1 Low Voltage Supply Line

ACC ACC Control Signal

ACTB0 (i) (i = 1 to m) active signal

ADD_H row direction address

ADD_V column direction address

ER clear signal

ERB inverted cancellation signal

EMBODIMENT OF THE INVENTION Hereinafter, the specific embodiment which concerns on the nonvolatile memory device of this invention and its control method is demonstrated in detail, referring drawings.

In Fig. 1, in a memory cell array of a nonvolatile memory device, sectors SO0 to S10 which are memory cell regions in which a plurality of memory cells are connected to word lines every predetermined number, and row direction addresses for each sector are arranged. Indicates the arrangement of decoder groups to decode.

The decoder group includes lower decoder groups 20 (1) to 20 (m) and 21 (m) provided for each of the upper decoder groups 10 and 11 and the sectors S00, S01 and S10 provided for each sector column in the same row direction. 1) to 21 (m) and 22 (1) to 22 (m).

The upper decoder groups 10 and 11 have upper decoders 10 (1) to 10 (m) and 11 (1) to 11 (m), respectively, and each upper decoder has m sets of global word lines GWL0 (1) / GWLB0. (1) to GWL0 (m) / GWLB0 (m) and global word lines GWL1 (1) / GWLB1 (1) to GWL1 (m) / GWLB1 (m) are selected.

At this time, the two global word lines GWL and GWLB are signals output as complementary decode signals in program operations and read operations other than the erase operation.

The lower decoder groups 20 (1) to 20 (m), 21 (1) to 21 (m), and 22 (1) to 22 (m) are global in the upper decoder groups 10 and 11 arranged in the same row direction. Takes a word line and decodes it again. That is, in the lower decoder groups 20 (1) to 20 (m) and 21 (1) to 21 (m), the global word lines GWL0 (1) / GWLB0 (1) to GWL0 (m) / GWLB0 (m) are connected. have. In the lower decoder groups 22 (1) to 22 (m), the global word lines GWL1 (1) / GWLB1 (1) to GWL1 (m) / GWLB1 (m) are connected.

Each of the lower decoder groups 20 (1) to 20 (m), 21 (1) to 21 (m), and 22 (1) to 22 (m) are n lower decoders 20 (1) (1) to 20 ( 1) (n) to 20 (m) (1) to 20 (m) (n), 21 (1) (1) to 21 (1) (n) to 21 (m) (1) to 21 (m) (n), 22 (1) (1) to 22 (1) (n) to 22 (m) (1) to 22 (m) (n), and each sub decoder is arranged in the same column direction. Each sector column is selected by the n first terminals of the predecode lines VWL0 (1) to VWL0 (n) and VWL1 (1) to VWL1 (n). The lower decoder is connected with a local word line for driving the control gate terminal of the memory cell in the sector (not shown), and the global word lines GWL0 (1) / GWLB0 (1) to GWL0 (m) / GWLB0 (m), The combination of GWL1 (1) / GWLB1 (1) to GWL1 (m) / GWLB1 (m) and the predecode lines VWL0 (x) and VWL1 (x) (x = 1 to n) results in a predetermined local word line. The bias is selected and supplied.

In FIG. 2, 1st Embodiment is demonstrated taking the decoding group with respect to the sector S00, S01 in FIG. 1 as an example. Each sector (S00, S01) is provided with lower decoder groups 20 (i) and 21 (i) (i = 1 to m). The high voltage power supply terminal VH and the low voltage power supply terminal VL of each of the lower decoder groups have predecode lines VWL0 (x), VWL1 (x) (x = 1 to n), and a low voltage supply line ((XDS0, XDS1)) is connected to the predecoder (B) 60, 61 and the switch (B) 50, 51, respectively. Further, global word lines GWL0 (i) / GWLB0 (i) (i = 1 to m) are connected to the corresponding lower decoder groups 20 (i) and 21 (i) (i = 1 to m), respectively.

The predecoder (B) 60, 61 receives the column direction address ADD_V and the erase signal ER, selects either the constant voltage supply line VPX or the ground voltage supply line PPS, and predecode the line VWL0. (x) and VWL1 (x) (x = 1 to n). Similarly, the switch (B) 50, 51 receives the column direction address ADD_V and the erase signal ER, selects either the first negative voltage supply line VM or the ground voltage supply line PPS, Connect to the low voltage supply lines XDS0 and XDS1. The first negative voltage supply line VM is connected to the level shift circuit 4, and the second negative voltage VMP output from the negative voltage generator circuit 3 via the second negative voltage supply line VMP is level shifted. It is supplied.

The global word line GWL0 (i) / GWLB0 (i) (i = 1 to m) is selected by the upper decoder group 10. The constant voltage supply line VPX is connected to the high voltage power supply terminal VH of the upper decoder group 10, and the low voltage power supply terminal VL is connected to the switch A 5 through the low voltage supply line NEGP which is the third terminal. Connected. The switch A 5 receives the erase signal ER, selects either the second negative voltage supply line VMP or the ground voltage supply line PPS and connects it to the low voltage supply line NEGP.

The upper decode group 10 includes an active signal ACTB0 (i) (i =) outputted from each of the upper decoders 10 (i) (i = 1 to m) constituting the upper decoder group 10 from the predecoder (A) 6. 1 to m) and an inverted erase signal ERB, which is an inverted signal of the erase signal ER, is input. The predecoder A 6 receives a row direction address ADD_H and an erase signal ER.

When the erase signal ER is at the low level and is in the non-erased state, any active signal ACTB0 (i) selected according to the row direction address ADD_H is at the low level and the high level inverted erase signal. Together with (ERB), the corresponding global word line GWL0 (i) is set at high level and the global word line GWLB0 (i) is set at low level.

At this time, with respect to the predecoder (B) 60, 61 and the switch (B) 50, 51, the sector where the erase signal ER is at the low level is irrelevant to the column direction address ADD_V. The predecoder (B) 60, 61 and the switches (B) 50, 51 in (S00, S01) are in an unselected state. The low voltage supply line is connected to the ground voltage supply line PPS via the non-selection switch B to supply the ground potential to the corresponding lower decoder group. Further, any one of the predecode lines is connected to the constant voltage supply line VPX via the selected predecoder B to supply the positive bias voltage to the corresponding lower decoder group.

Global word line GWL0 (high / low level) selected by the row direction address ADD_H for the lower decode group selected by the column direction address ADD_V and the ER signal and supplied with the positive bias voltage and ground potential. i) / GWLB0 (i) is input, the positive bias voltage is supplied to a local word line (not shown) to select memory cells in the row direction. In this manner, the row direction is selected in the program operation or the data read operation. At the end of the selection, the active signal ACTB0 (i) is inverted to a high level, whereby the global word line GWL0 (i) is turned to a low level, and the global word line GWLB0 (i) is inverted to a high level and the local word line charged to a constant voltage. Is performed by discharging the voltage bias to ground potential supplied to the ground voltage supply line PPS via the low voltage supply line.

In this case, when the same row direction address ADD_H and the column direction address ADD_V are unselected, the predecode line VWL (x) is connected to the ground voltage supply line via the predecoder B 60 and 61. Because it is connected to (PPS), the local word line is held at ground potential. In addition, when the row direction addresses ADD_H are different, the global word line is in an unselected state, and since the low side voltage supply line is connected to the ground voltage supply line PPS via the switches B (50, 51), the local word line is Maintained at ground potential.

When the erase signal ER is at a high level and in the erased state, the negative voltage generating circuit 3 is activated to supply the second negative voltage VMP to the second negative voltage supply line VMP. The second negative voltage VMP is level shifted to the first negative voltage VM via the level shift circuit 4. The second negative voltage VMP is selected for the switch A 5 by the activated erase signal ER and the same row direction address ADD_H as the sector to be erased, and is supplied to the upper decoder group 10. At the same time, the first negative voltage VM is selected by the activated erase signal ER in the switches B 50 and 51 in all sectors S00 and S01 in the same row direction, or in the column direction. Selected by the switches B (50, 51) in the sectors S00 and S01 to be erased according to the address ADD_V, the lower decoder groups 20 (i) and 21 (i) (i = 1 to m). Is supplied. At this time, in the level shift circuit 4, the first subvoltage VM performs a level shift so as to have a higher voltage level than the second subvoltage VMP.

In addition, the predecoder (A) 6 sets all active signals ACTB0 (i) (i = 0 to m) to the low level by the activated erase signal ER. As a result, all of the global word lines GWL0 (i) (i = 0 to m) output from the upper decoder group 10 are connected to the low side voltage supply line NEGP. As a result, the global word line GWL0 (i) (i = 0 to m) is biased to the second negative voltage VMP. On the other hand, the global word line GWLB0 (i) (i = 0 to m) is held at the ground potential.

Further, the predecoder (B) 60, 61 is erased by the erase signal ER activated for all sectors S00 and S01 in the same row direction or in accordance with the column direction address ADD_V. The predecode lines VWL0 (x) and VWL1 (x) (x = 1 to n) are connected to the ground voltage supply line PPS with respect to the target sectors S00 and S01.

At this time, the predecoder (B) 60, 61 and the switch (B) 50, 51 perform the same control. In other words, the ground voltage supply line PPS is selected in the predecoder B 60 and 61 for the sector in which the first negative voltage supply line VM is selected in the switches B and 50 and 51. The batch erase is performed on the sectors in the connected state. The first word voltage VM is supplied to the low voltage power supply terminal VL of the lower decoder group arranged in the sector to be erased or a plurality of sectors in common, and is a global word connected to the lower decoder group. The second negative voltage VMP, which is lower than the first negative voltage VM, is commonly supplied to the line GWL0 (i) (i = 0 to m).

FIG. 3 relates to the decoder group of FIG. 2, wherein the upper decoder 10 (i) (i = 1 to m) constituting the upper decoder group 10 and the lower decoder 20 (1) constituting the lower decoder group 20 (1). (x) (x = 1 to n) is a circuit configuration example. The upper decoder 10 (i) (i = 1 to m) is provided in the upper decoder group 10 with m sets, and each higher decoder 10 (i) (i = 1 to m) has the same configuration as the circuit shown in FIG. Have Each of the higher decoders 10 (i) (i = 1 to m) are selectively controlled by the active signals ACTB0 (i) (i = 1 to m) in the non-erasing operation. In the erase operation, all the active signals ACTB0 are selected. (i) (i = 1 to m) are simultaneously selected by being activated at a low level. Each higher decoder 10 (i) (i = 1 to m) is provided for n sets of lower decoders 20 (i) (x) (i = 1 to m) (x = 1 to n). Among these, the global word line GWL0 (i) / GWLB0 (i) (i = 1 to m) is commonly connected to the lower decoder 20 (i) (x) (i = lm) (x = 1 to n). .

The upper decoder 10 (i) includes PMOS transistors TP1 and TP2 whose source terminals are connected to the constant voltage supply line VPX and whose drain and gate terminals are connected to each other. The drain terminal of the PMOS transistor TP1 is connected to the input terminal of the active signal ACTB0 (i) via the NMOS transistor TN1. The drain terminal of the PMOS transistor TP2 is connected to the low voltage supply line NEGP via the NMOS transistor TN2 which is the third N-type transistor. The gate terminal of the NMOS transistor TN1 is connected to the power supply voltage VCC, and the gate terminal of the NMOS transistor TN2 is connected to the input terminal of the active signal ACTB0 (i). The global word line GWL0 (i) is output from the connection point of the PMOS transistor TP2 and the NMOS transistor TN2. The active signal ACTB0 (i) and the erase signal ER are input to the NAND gate NA1, and the output signal of the NAND gate NA1 is output as the global word line GWLB0 (i) via the inverter gate I1. . At this time, the NMOS transistor TN1 has a function of limiting the bias voltage applied to the input terminal of the active signal ACTB0 (i) to the power supply voltage VCC or less. In the case of a program operation or the like, even if a boosting voltage equal to or higher than the power supply voltage VCC is applied to the constant voltage supply line VPX, the voltage applied to the input terminal of the active signal ACTB0 (i) by the NMOS transistor TN1 is equal to or lower than the power supply voltage VCC. Limited to

The lower decoder 20 (i) (x) is a first N-type bit connected to a global word line CWL0 (i) to a gate terminal and connecting a predecode line VWL0 (x) and a local word line WL (i) (x). NMOS transistor TN4, which is a second N-type transistor that connects the global word line GWLB0 (i) to the NMOS transistor TN3, which is a transistor, and the gate terminal, and connects the low side voltage supply line XDS0 and the local word line WL (i) (x). It is equipped with.

At this time, the voltage value from the ground potential to the constant voltage is supplied to the predecode line VWLO (x) according to the operating state. The power supply voltage VCC or the ground potential is supplied in the erase operation, the power supply voltage VCC is supplied in the read operation, and the boosted voltage is supplied in the program operation. The low side voltage supply lines NEGP and XDS0 are supplied with either a negative voltage or a ground potential depending on the operating state. The ground potential is supplied in the read operation and the program operation, while the negative voltage is supplied in the erase operation. Specifically, the second negative voltage VMP is supplied to the low voltage supply line NEGP, and the first negative voltage VM having a voltage level higher than the second negative voltage VMP is supplied to the low voltage supply line XDS0. do.

The circuit operation of FIG. 2 and FIG. 3 is demonstrated based on FIG. 4 illustrates a program operation as a case of non-erasing operation. In addition, the suffix is abbreviate | omitted about each signal line and described.

In the case of a program operation, first, the inversion erase signal EBR is at a high level. As a power supply voltage, it is a voltage level of 1.8V, for example. By the switches A and B (see Fig. 2), the low side voltage supply line NEGP and XDS are ground potentials. In addition, with respect to the constant voltage supply line VPX, for example, 9 V is supplied as a boost voltage to the higher-order decoder which decodes the sector SO0 having the memory cell to be programmed. For example, 1.8 V is supplied as a power supply voltage VCC to a higher decoder for a sector that is not a program target such as sector S10.

In the higher decoder which decodes the sector S00 having the memory cell to be programmed, the active signal ACTB is activated at any one of the active signals ACTB at a low level (for example, a ground potential), and the other is at a high level (for example, Is maintained at 1.8 V as the power supply voltage VCC. All active signals ACTB are held at a high level (e.g., 1.8V) for the higher decoder which decodes sector S10 having no memory cell to be programmed.

As shown in Fig. 3, in the upper decoder 10 (i), the gate terminal of the PMOS transistor TP2 becomes low level and conducts to the low level active signal ACTB0 (i) via the NMOS transistor TN1, and at the same time NMOS Transistor TN2 becomes non-conductive. The global word line GWL0 (i) is activated to the voltage level (for example 9V) of the constant voltage supply line VPX. At this time, the PMOS transistor TP1 becomes non-conductive, and this state is maintained. At this time, since the inversion erase signal EBR is at a high level, the global word line GWLB0 (i) corresponding to the low level active signal ACTB0 (i) is at a low level (for example, a ground potential). In contrast, the logic level of the global word line GWL / GWLB is inverted for the high level active signal ACTB.

On the other hand, in the lower decoder, the predecode line VWL selected according to the column direction address ADD_V is selected at a high level. The voltage level at this time is 9 V, for example by a voltage booster circuit not shown. Since the predecode line VWL is wired in the column direction, a high level is supplied to the sectors SO0 and S10 in the same column direction. The other predecode lines VWL of the sectors S00 and S01 unselected by the column direction address ADD_V and the predecode lines VWL of the sector S01 maintain the low level.

The global word line GWL / GWLB activated at the high / low level is connected to a lower decoder in sectors S00 and S01 in the same row direction. As shown in Fig. 3, the NMOS transistor TN3 of the lower decoder 20 (i) (x) is turned on and the NMOS transistor TN4 is turned off. As a result, the predecode line VWL0 (x) is connected to the local word line. On the other hand, the predecode line VWL0 (x) activated at the high level is connected to the lower decoder 20 (i) (x) in the sectors S00 and S10 in the same column direction. As a result, the local word line WL selected in the sector S00 is connected to the high level predecode line VWL0 (x), and is biased to the constant voltage corresponding to the program operation.

In the case of the erase operation, first, the inversion erase signal EBR is at a low level. Further, the column direction address ADD_V in the sector is not identified, and the predecode line VWL is kept at the low level. By the switch A (Fig. 2), the second negative voltage supply line VMP is connected to the low voltage supply line NEGP in the same row direction as the sector S00 to be erased. The second negative voltage VMP is supplied from the negative voltage generating circuit 3 to the second negative voltage supply line VMP. For example, -10V. The ground voltage supply line PPS is connected to the low voltage supply line NEGP in a row direction different from the sector SO0 to be erased.

Among the switches B (FIG. 2) provided for each sector, the 1st negative voltage supply line VM is selected by the switch B selected according to the column direction address ADD_V which shows the sector S00 to be erased, and the low side voltage is selected. It is connected to the supply line XDS. In the level shift circuit 4, the first sub-voltage VM (for example, -9 V) level-shifted from the second sub-voltage VMP is supplied to the lower decoder in the sector SO0 to be erased. The ground voltage supply line PPS is connected to the sectors S10 and SO1 which are not to be erased.

In addition, the ground potential is supplied to the upper decoder which decodes the sector S00 to be erased from the constant voltage supply line VPX. For example, 1.8 V is supplied as the power supply voltage VCC to the higher-order decoders arranged in the row direction in which there are sectors not to be erased.

In the upper decoder that decodes the sector S00 to be erased, the active signal ACTB is activated at the low level. For the higher-order decoder in the row direction different from the sector S00 to be erased, all active signals ACTB are maintained at the high level of the power supply voltage VCC (for example, 1.8V).

As for the upper decoder 10 (i) that decodes the sector to be erased, as shown in Fig. 3, since the second negative voltage (for example, -10V) is supplied to the low side voltage supply line NEGP, the constant voltage supply line VPX And the ground potential or the low level to the active signal ACTB0 (i), and high differential voltage is not applied to the PMOS transistors TP1, TP2, and the NMOS transistor TN2.

In the upper decoder 10 (i) which decodes the sector SOO to be erased, since the active signal ACTB is at the low level (for example, the ground potential), the second negative voltage (for example, -10 V is applied to the low side voltage supply line NEGP). ) Is supplied, the NMOS transistor TN2 is turned on, and the global word line GWL0 (i) is activated to the second negative voltage (for example, -10V). The PMOS transistor TP1 conducts and sets the gate terminal of the PMOS transistor TP2 to the ground potential. PMOS transistor TP2 remains non-conductive. At this time, since the inversion erase signal EBR is at the low level, the global word line GWLB0 (i) is at the low level. In contrast, in the higher decoder in a row direction different from the sector SO0 to be erased, the NMOS transistor TN2 conducts to the high level active signal ACTB, the low voltage supply line NEGP is the ground potential, and the global word line GWL is It becomes the ground potential. In addition, since the inversion erase signal is at the low level, the global word line GWLB is maintained at the low level.

Since the first negative voltage (for example, -9V) is supplied to the low side voltage supply line XDS to the sector S00 to be erased, and the voltage level of the global word line GWLB is the ground potential, the circuit diagram shown in FIG. 3 is shown. As shown, the NMOS transistor TN4 of the lower decoder 20 (i) (x) is turned on and supplies the first negative voltage VM (for example, -9V) to the input word line WL (i) (x). do. At this time, since the second negative voltage VMP (for example, -10V) is supplied to the global word line GWL0 (i), the NMOS transistor TN3 has a reverse bias state in which the gate terminal is biased to the negative voltage compared to the drain terminal. to be. Even when a low threshold voltage M0S transistor is used as the NMOS transistor TN3, a sufficient reverse bias is applied, so that leakage current such as tailing current can be sufficiently reduced.

In addition, among the sectors S10 and S01 that are not to be erased, the global word line GWL is the second negative voltage (for example, -10V) for the sector S01 that is in the same row direction as the sector SOO to be erased. Since the NMOS transistor TN3 conducts in the lower decoder, the ground potential is supplied to the predecode line VWL connected to the word line WL at this time. Thus, the word line is held at ground potential. In addition, the global word line GWL / GWLB is all at ground potential for the sector S10 in a row direction different from the sector SO0 to be erased. The NMOS transistors TN3 and TN4 are both non-conductive, and the local word line WL is in a floating state. The local word line WL in the floating state is, for example, a well potential boosted to a high voltage level such as 9 V. As a result of the voltage level being defined under the influence of capacitive coupling or current leakage, the well potential Is maintained at a potential close to. The erase operation is not performed on this word line.

FIG. 5 shows a portion of a circuit generating the second negative voltage VMP and the first negative voltage VM. The second negative voltage VMP is output from the negative voltage generating circuit 3 activated by the erase signal ER to the second negative voltage supply line VMP. The second negative voltage supply line VMP is connected to the level shift circuit 4, and the first negative voltage VM is output from the level shift circuit 4 to the first negative voltage supply line VM. The regulator circuit 7 is connected to the first negative voltage supply line VM.

The negative voltage generating circuit 3 is a charge pump circuit, for example. Charge is drawn from the second negative voltage supply line VMP by a charge pump operation to generate a negative voltage on the second negative voltage supply line VMP.

 The level shift circuit 4 is comprised with a diode element etc., for example. An anode terminal is connected to the first negative voltage supply line VM, and a cathode terminal is connected to the second negative voltage supply line VMP. In response to the negative voltage generating circuit 3 constituted by the charge pump circuit drawing charges, a voltage drop of the forward voltage, through which current flows in the forward direction of the diode element, is generated, thereby reducing the voltage from the second negative voltage VMP. A voltage level shift to one negative voltage VM is made. In this case, the forward voltage of the diode element depends on the current value flowing, but becomes a level shift of about 1V.

The regulator circuit 7 is controlled on / off by the output signals of the comparator CMP and the comparator CMP to which the feedback node FB and the reference voltage VRF are connected, and the voltage of the first negative voltage supply line VM. Compared with the level, the switch unit SW having one end connected to the high voltage voltage source VH1 and the resistance element R1 connected between the other end of the switch unit SW and the first negative voltage supply line VM are provided. Doing. In addition, the feedback node FB has a capacitor C2 connected between the capacitor C1 and the first negative voltage supply line VM between the ground potential and the voltage source VH2 of a predetermined voltage level. The PMOS transistor TP3 is connected between. The low pulse reset signal RST is supplied to the gate terminal of the PMOS transistor TP3 prior to the erase operation.

The erase operation is started after the feedback node FB is initialized by outputting the low pulse reset signal RST. When the erase signal ER becomes high and the negative voltage generating circuit 3 is activated, the charge pump operation is performed and the first negative voltage supply line (VMP) and the level shift circuit 4 are applied. The charge of VM) is drawn out. As a result, the potentials of the first and second negative voltage supply lines VM and VMP are dropped. In accordance with the capacitive coupling by the capacitor C2, the potential of the feedback node FB also drops. The potential drops of the first and second sub-voltage supply lines VM and VMP continue, so that the potential of the feedback node FB further drops the reference voltage VFB, so that the switch section SW conducts and the first portion Current flows through the voltage supply line VM, and the potentials of the first and second sub-voltages VM and VMP are raised. As a result, the potential of the feedback node FB also rises. Feedback control is made so that the potential of the feedback node FB is balanced with the reference voltage VFB, and the first and second negative voltages VM and VMP are regulated to predetermined negative voltages. For example, the voltage is -9 V as the first negative voltage VM and -10 V as the second negative voltage VMP. In this case, -9 V in the first negative voltage VM is a voltage value based on voltage bias specifications of the local word line in the erase operation, and -10 V in the second negative voltage VMP is It is the voltage value which carried out the voltage drop of the forward voltage of the diode element which comprises the level shift circuit 4. As shown in FIG.

The negative voltage of the first negative voltage supply line VM is monitored and the current is supplied when the negative voltage is lowered than the predetermined voltage. The supplied current is drawn out from the charge pump circuit constituting the negative voltage generating circuit 3 via the diode element constituting the level shift circuit 4. Since the current supply by the regulator circuit 7 is controlled within the range of the current drawing capability of the charge pump circuit, the first negative voltage VM and the second negative voltage VMP are maintained at a predetermined voltage level.

6 and 7 are circuit block diagrams of the second embodiment. In the second embodiment, when the erasing operation is performed in the FCER mode (or ACC mode), the supply power to the negative voltage generating circuit 3 is a voltage source having a higher voltage than the normal power supply voltage VCC. It is a method of absorbing the leakage current which increases by increasing the driving capability of the voltage generating circuit 3.

6 is a first embodiment. In accordance with the ACC control signal ACC indicating the FCER mode (or ACC mode), the power supply switching unit 8 replaces the supply power. For example, in the non-ACC mode, the positive bias voltage (for example, 9V) to the well can be sufficiently supplied by using a boost circuit inside the nonvolatile memory device, but in the ACC mode, the erase range is increased as the erase range increases. As a result, the internal boosting circuit cannot be processed. In response to this, the ACC power supply terminal 81, which is a dedicated power supply terminal, is prepared and a positive bias voltage is supplied directly from the ACC power supply terminal 81 to the well as it enters the ACC mode. In the first embodiment, the positive bias voltage supplied from the ACC power supply terminal 81 is supplied to the negative voltage generating circuit 3 by the power supply switching section 8. For example, when the normal power supply voltage VCC is 1.8 V and 9 V is supplied as the positive bias power supply, when the charge pump circuit is used as the negative voltage generating circuit 3, in one pump operation, Therefore, the voltage amplitude can be greatly increased, and the desired negative voltage can be generated with a small number of pumping times. The circuit configuration of the negative voltage generating circuit 3 can be simplified, and the current consumption can be reduced.

In addition, the ACC power supply terminal 81 can be used as a control terminal, an address terminal, etc. which are not used in FCER mode, and can also reduce the number of terminals of a package.

7 is a second embodiment. In the first embodiment, when treating the positive bias voltage input from the ACC power supply terminal 81 as a direct supply voltage, it is necessary to design the element breakdown voltage of the negative voltage generating circuit 3 together with the positive bias voltage. Therefore, the power supply voltage VCC in normal operation is provided with an excessive element breakdown voltage, and there are many unnecessary parts in the circuit configuration. Accordingly, when switching the power supply in the ACC mode, instead of using the positive bias voltage input from the ACC power supply terminal 81 as it is, by providing a step-down circuit inside, the device breakdown voltage of the negative voltage generating circuit 3 is secured. In the meantime, sufficient driving capability can be realized regardless of the ACC mode.

The positive bias voltage supplied from the ACC power supply terminal 81 is divided by the resistor elements R2 and R3, and the divided divided bias voltage (for example, 5V) is secured through the buffer circuit BUF to secure the current supply capability. Input to the power switching unit 8. As a result, for example, a high bias voltage of 9 V is not directly applied to the negative voltage generating circuit 3. It is not necessary to configure the negative voltage generating circuit 3 by a high voltage endurance element, and the negative voltage generating circuit 3 can always be provided with sufficient driving capability regardless of the ACC mode.

8 and 9 are circuit block diagrams of the third embodiment. In the erase operation in the non-ACC mode, the power supply voltage VCC (for example, 1.8 V) is supplied from the VCC power supply terminal 82 in place of the negative voltage generating circuit 3 used (FIG. 8), Alternatively, in addition to the negative voltage generating circuit 3 (FIG. 9), the positive bias voltage (for example, 9 V) higher than the power supply voltage VCC (for example, 1.8 V) from the ACC power supply terminal 81. Auxiliary negative voltage generating circuit 31 is energized. The auxiliary negative voltage generating circuit 31, which is activated by the positive bias voltage higher than the power supply voltage VCC, has a higher driving capability than the negative voltage generating circuit 3, and collectively erases more sectors. Also in the ACC mode in which the leakage current is increased, the predetermined second negative voltage VMP can be supplied to the second negative voltage supply line VMP.

In FIG. 8, the enable terminal EN of the negative voltage generating circuit 3 and the auxiliary negative voltage generating circuit 31 is controlled by the AND gates A1 and A2. The inverted signal of the erase signal ER and the ACC control signal ACC is input to the AND gate A1. The negative voltage generating circuit 3 is activated in accordance with the high level erase signal ER indicating the erasing operation and the low level ACC control signal ACC indicating the non-ACC mode state. The erase signal ER and the ACC control signal ACC are input to the AND gate A2. The auxiliary negative voltage generation circuit 31 is activated in accordance with the high level erase signal ER indicating the erase operation and the high level ACC control signal ACC indicating the ACC mode state. That is, in each of the ACC mode and the non-ACC mode, the negative voltage generating circuit 3 and the auxiliary negative voltage generating circuit 31 are activated, and the second negative voltage supply line VMP is applied to the second negative voltage supply line VMP. Supply.

In FIG. 9, the enable terminal EN of the negative voltage generating circuit 3 and the auxiliary negative voltage generating circuit 31 is controlled by the erase signal ER and the AND gate A3. The erase signal ER and the ACC control signal ACC are input to the AND gate A3. Since the negative voltage generating circuit 3 can be always activated, the auxiliary negative voltage generating circuit 31 is further activated in accordance with the high level ACC control signal ACC indicating the ACC mode state in the erasing operation. As the ACC mode is entered, the auxiliary negative voltage generating circuit 31 is activated in addition to the negative voltage generating circuit 3, and the second negative voltage VMP is supplied to the second negative voltage supply line VMP.

In the case where the negative voltage generating circuit 3 is provided with the charge pump circuit, it is conceivable to make the operating frequency for performing the charge pump operation higher in the ACC mode than in the non-ACC mode. . By increasing the operating frequency of the charge pump operation, it is possible to increase the supply capability of the negative voltage.

For the control circuit, the control part of FIG. 8 can be used as it is. In the charge pump circuit, the circuit configuration of the oscillator for determining the operating frequency is well known. A well-known technique can be applied also to the high frequency of an operating frequency. For example, when a ring oscillator is used, high frequency can be achieved by increasing the power supply capability to each gate circuit constituting the ring oscillator. At this time, the power supply capability is determined by the supply current and the supply voltage. By increasing the current supplied or increasing the supply voltage, the power supply capability can be increased. In addition, when a divider circuit is provided, high frequency can be achieved by reducing the division ratio. In addition, when it is comprised by analog circuits, such as charge / discharge of a capacitor | capacitance component, it is high frequency by the time constant of each gate circuit by changing an analog quantity, such as reducing a capacitance value and increasing a charge / discharge current value. Sign language can be realized. By changing these settings, a frequency switching unit for switching the frequency in accordance with the output signal of the AND gate A2 can be provided. In the ACC mode, the operating frequency in the charge pump operation can be high frequency.

As can be seen from the above description, according to the first embodiment, as illustrated in FIGS. 2 to 4, the lower decoder 20 (i) (x) (i = 1 to m) (x = 1 to n) In the control terminal of the NMOS transistor TN3, which is an example of the first N-type transistor, that is, the gate terminal, the first negative voltage VM is supplied from the NMOS transistor TN4 to the local word line WL (i) (x). The low voltage second negative voltage VMP is supplied. The NMOS transistor TN3 is applied in reverse bias to be surely turned off. Since the reverse bias is applied between the gate and the source even when the leakage current such as the tailing current flows even when the gate-source voltage is zero volts and the gate-source voltage is zero volts, the leakage current can be reliably reduced. The first negative voltage VM can be reliably supplied to the local word line WL (i) (x).

In addition, according to the second or third embodiment, the number of sectors to be collectively erased is increased by, for example, the ACC mode, or the number of local word lines biased to the negative voltage is increased. The supply current of the negative voltage is increased in accordance with a predetermined load condition in which the leakage current increases and the load of the negative voltage generating circuit increases.

That is, in 2nd Embodiment, the high voltage positive bias voltage supplied to the ACC power supply terminal 81 from the normal power supply voltage VCC (for example, 1.8V) is supplied to the negative voltage generation circuit 3 from the normal power supply voltage VCC (for example, 1.8V). (E.g., 9V) (Fig. 6), and a divided bias voltage (e.g., 5V) divided by the internal circuit from the positive bias voltage (e.g., 5V) (Fig. 7).

In the third embodiment, the high voltage supplied from the ACC power supply terminal 81 in place of the negative voltage generating circuit 3 in which the normal power supply voltage VCC is supplied and activated in the non-ACC mode in the ACC mode. By switching to the supplied auxiliary negative voltage generation circuit 31 (Fig. 8), or in addition to the negative voltage generation circuit 3, by activating the auxiliary negative voltage generation circuit 31 (Fig. 9), The supply ability of the voltage VMP can be improved.

In addition, when the negative voltage generation circuit is provided with the charge pump circuit, the supply frequency of the negative voltage can be increased by increasing the operating frequency in the charge pump operation.

Thereby, the supply of the first negative voltage VM of the local word line can be reliably supplied, and the circuit operation such as the erase operation of supplying the negative voltage of the local word line can be reliably performed.

In addition, since the leakage current is reduced, the negative voltage supply capability of the negative voltage generating circuit can be minimized, and the circuit scale can be reduced.

In addition, since the negative voltage supply capability can be increased as necessary, the unnecessary current supply operation can be eliminated, the circuit current consumption can be reduced, and the circuit scale can be reduced.

In addition, this invention is not limited to the said embodiment, Needless to say that various improvement and modification are possible in the range which does not deviate from the meaning of this invention.

For example, in the first embodiment, the configuration of the upper decoder and the lower decoder shown in FIGS. 1 to 3 has been described as an example, but the method of configuring the decoder is not limited to this. Also in other configurations, it goes without saying that the same effects and effects are provided.

In addition, in this embodiment, the case where the word line structure of a hierarchy of a global word line and a local word line is provided as a structure of a word line was described as an example, but this invention is not limited to this. The same applies to the case where the word line structure is one layer or the multi-layer having three or more layers.

In addition, although the level shift circuit 4 was demonstrated as being comprised by the diode element in FIG. 5, this invention is not limited to this. If the configuration of the negative voltage step-down means capable of flowing a current with a substantially constant voltage transition can be applied.

In addition, in FIG. 5, it is also possible to set it as the structure which regulates the 2nd negative voltage VMP by the regulating circuit 7. As shown in FIG.

Claims (18)

A first N-type transistor provided between the first terminal and the word line and supplying the constant voltage supplied to the first terminal to the word line by conduction; Supplying a second negative voltage which is lower than the first negative voltage to the control terminal of the first N-type transistor when the first negative voltage is supplied to the word line with the first N-type transistor being non-conductive. And a negative voltage generator. The method of claim 1, And an erase operation is performed on the memory cells connected to the word line in accordance with the first negative voltage supplied to the word line. The method of claim 1, And a level shift section for level shifting the second subvoltage to generate the first subvoltage. The method of claim 1, A second N-type transistor provided between the second terminal and the word line and discharging the constant voltage supplied to the word line by conduction, and supplying the first negative voltage to the word line. And the second N-type transistor is conductive and the first negative voltage is supplied to the second terminal. The method of claim 4, wherein A third N-type transistor provided between the third terminal and the control terminal of the first N-type transistor, the third N-type transistor configured to discharge the bias voltage supplied to the control terminal by conduction, The supply of the second negative voltage to the control terminal is performed by the conduction of the third N-type transistor and the supply of the second negative voltage to the third terminal. A negative voltage generator supplying a negative voltage to the word line; A power switching unit for switching the power supply to the negative voltage generating unit to a high voltage power having a higher voltage level in accordance with a predetermined load condition in the negative voltage generating unit; Here, the negative voltage is supplied to the word line when an erase operation is performed on the memory cell connected to the word line, And the predetermined load condition is a case where a predetermined number or more of the memory cells are erased at the same time. delete The method of claim 6, And the high voltage power source is a power source supplied from outside according to the predetermined load condition. The method of claim 8, The predetermined load condition is a fast chip erase (FCER) mode, which is an operation mode for collectively erasing a plurality of sectors. And the externally supplied power is power input from a power terminal for the FCER mode. The method of claim 6, And the high voltage power source is generated based on the power supplied from the outside according to the predetermined load condition. A negative voltage generator having a charge pump circuit and supplying a negative voltage to a word line; And a frequency switching unit for switching the operating frequency in the charge pump operation to a higher frequency in accordance with a predetermined load condition in the negative voltage generating unit. A negative voltage generator supplying a negative voltage to the word line; An auxiliary negative voltage generator for starting operation in addition to the negative voltage generator or in addition to the negative voltage generator according to a predetermined load condition in the negative voltage generator; The negative voltage generator and the auxiliary negative voltage generator include a charge pump circuit, and an operating frequency of the charge pump circuit of the auxiliary negative voltage generator is higher than an operating frequency of the charge pump circuit of the negative voltage generator. Nonvolatile memory. The method of claim 12, And the power supply to the auxiliary negative voltage generator is higher than that of the power supply to the negative voltage generator. delete A control method of a nonvolatile memory device having a first N-type transistor provided between a first terminal and a word line, and electrically conducting when a constant voltage is supplied from the first terminal to the word line. Supplying a first negative voltage to the word line; And when supplying the first negative voltage to the word line, supplying a second negative voltage which is lower than the first negative voltage to the control terminal of the first N-type transistor. Control method of volatile memory. Selecting a word line; Supplying a negative voltage to the selected word line; Increasing the supply capability of the negative voltage when the number of selected word lines is greater than or equal to a predetermined number, Here, the increase in the capability of supplying the negative voltage is performed by setting the operating frequency in the charge pump operation for supplying the negative voltage to a higher frequency than the normal frequency. The method of claim 16, The increase in the supply capability of the negative voltage is performed by setting the voltage level of the supply power supply higher than the normal supply power supply. delete

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