KR100870010B1 - Thin film transistor array panel - Google Patents

Abstract

A thin film transistor substrate according to the present invention is a thin film transistor substrate including a gate wiring, a data wiring, a pixel electrode, and a thin film transistor connected thereto, wherein one end of a metal line or a metal line is formed on the same layer as the data wiring or the gate wiring. An electrostatic protection pattern including a metal cap formed on the substrate is formed at a distance from the thin film transistor.

Thin Film Transistor, Substrate, Static Electricity, Prevention

Description

Thin film transistor array panel

1A is a schematic layout view of a thin film transistor substrate according to a first exemplary embodiment of the present invention.

FIG. 1B is a cross-sectional view taken along line Ib-Ib 'of FIG. 1A.

2A is a schematic layout view of a thin film transistor substrate according to a second exemplary embodiment of the present invention.

FIG. 2B is a cross-sectional view taken along line IIb-IIb ′ of FIG. 2A.

3 and 4 are schematic layout views of a thin film transistor substrate according to third and fourth embodiments of the present invention, respectively.

※ Explanation of code for main part of drawing ※

110: substrate 181, 182, 183: contact hole

600: guard ring 610, 610a, 610b: metal wire

620, 620a, 629b: metal cap 630: electrostatic induction pattern

640a, 640b: Metal piece A: display area

B: Undercut portion C: Corner

D1, D2: Eggplant

The present invention relates to a thin film transistor substrate on which an antistatic pattern is formed.

The thin-film transistor substrate (TFT) is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic electroluminescence (EL) display device, or the like. The thin film transistor substrate includes a scan signal line or a gate line for transmitting a scan signal and an image signal line or data line for transmitting an image signal, a thin film transistor connected to the gate line and a data line, and a pixel connected to the thin film transistor. A gate insulating layer covering and insulating an electrode, a gate wiring, and an interlayer insulating layer covering and insulating a thin film transistor and a data wiring.

The thin film transistor includes a semiconductor layer forming a gate electrode and a channel which are part of a gate wiring, a source electrode and a drain electrode which is a part of the data wiring, a gate insulating layer, an interlayer insulating layer, and the like. The thin film transistor is a switching device that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line.

Since such a TFT substrate is an insulator, a transparent insulating substrate on which gate wirings, data wirings, etc. are formed, static electricity generated during the manufacturing process flows into these wirings to exist locally. Therefore, even if a small amount of static electricity flows in, the voltage is increased by being present locally in the flowed portion, thereby causing damage to devices such as TFTs and causing disconnection of wiring.

Therefore, a shorting bar or guard ring connecting each gate wiring and data wiring inside and outside of the gate pad and the data pad to reduce the defect caused by static electricity, the gate wiring and the data wiring, respectively The static electricity is blocked or prevented by using a method of electrically neutralizing the static electricity generated from the substrate by using an antistatic circuit or an ionization device formed on the substrate.

Among these methods, however, the ionizer and the antistatic circuit are less effective in blocking static electricity than the shorting bar, and the shorting bar is very effective in preventing the damage caused by static electricity, but the short circuit is shorter when the distance from the thin film transistor is close. The static electricity introduced into the ring bar flows into a site susceptible to static electricity, such as an undercut portion formed in the gate wiring of the adjacent thin film transistor, thereby causing a failure in disconnecting the wiring. And since the antistatic circuit is located inside the gate pad or the data pad, the pad cannot be protected from the static electricity flowing in.

The present invention provides a thin film transistor substrate including an antistatic pattern for blocking or dissipating static electricity flowing from the outside to solve the above problems.

The present invention relates to a thin film transistor substrate including an antistatic pattern.

Specifically, in a thin film transistor substrate including a gate wiring, a data wiring, a pixel electrode, and a thin film transistor connected thereto, a metal formed on one end of a metal line or a metal line formed on the same layer as the data line or the gate wiring. An electrostatic protection pattern including a cap is formed at a distance from the thin film transistor. Here, the metal cap may be formed to have a plurality of branches.

Another thin film transistor substrate includes a thin film transistor substrate including a gate wiring, a data wiring, a pixel electrode, and a thin film transistor connected thereto, wherein the thin film transistor substrate is formed at one end of the first metal line and the first metal line which are formed in the same layer as the data line. The thin film transistor includes an electrostatic protection pattern including a first metal cap formed thereon, a second metal line parallel to the first metal line, and formed on the same layer as the gate line, and a second metal cap formed at one end of the second metal line. It is formed a certain distance away from. Here, the first and second metal caps may be formed to have a plurality of branches, and the first and second metal caps may be formed to cross each other.

The thin film transistor substrates may form a triangular pattern on the outer circumference of the metal line, or may further include an insulating layer covering the static electricity protection pattern, and the insulating layer may further form contact holes exposing the metal line. The metal wire may be formed in a plurality of layers to form an undercut portion under the contact hole or further form a metal piece connected to the metal wire through the contact hole.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

Now, a thin film transistor substrate including an antistatic pattern according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[First Embodiment]

1A is a schematic layout view illustrating a thin film transistor substrate according to the present invention, and FIG. 1B is a cross-sectional view taken along line Ib-Ib ′ of FIG. 1A.

As shown in FIGS. 1A and 1B, a display area A is formed on a substrate, and a guard ring 600 is formed to surround the display area A. FIG.

The display area A is a region in which thin film transistors are formed in a matrix form. A thin film transistor (not shown) is formed on a transparent insulating substrate and includes a gate wiring including a gate line, a gate electrode, and a gate pad, and a gate wiring on the gate wiring. A gate insulating layer formed, a semiconductor layer formed of a semiconductor material such as amorphous silicon in a predetermined region of the gate insulating layer, an ohmic contact layer formed of a semiconductor material such as amorphous silicon doped with n-type impurities, An insulating layer having a data wiring including a source electrode, a drain electrode, a data line, a data electrode, and a data pad formed on the ohmic contact layer and the gate insulating layer, and a contact hole formed on the data wiring; And a pixel electrode connected to the drain electrode through the contact hole.

An antistatic pattern is formed between the display area A and the guard ring 600. The antistatic pattern is formed of a metal wire 610 formed long and a metal cap 620 formed at one end of the metal wire 610.

The metal wire 610 carries static electricity flowing from the outside to the metal cap 620, and the metal cap 620 stores the charged electric charges.

The metal line 610 and the metal cap 620 are formed on the same layer as the data line, but may be formed on the gate line. In this case, since the metal line 610 and the metal cap 610 are formed by patterning at the same time when forming the data line or the gate line, a separate process for forming the metal line 610 and the metal cap 620 is not added.

Herein, an electrostatic induction pattern 603 for inducing static electricity is further formed at one end of the metal wire 610 not connected to the metal cap 620. The pattern 630 may be formed in a triangular shape so that the pointed portion faces a path through which static electricity flows. This uses the principle of lightning rods where static electricity is concentrated in pointed areas.

In addition, the metal wire 610 is further formed with a means for inducing spark (Spark). Means B for inducing sparks are possible by forming contact holes 181. Specifically, the metal wire 610 is formed of a plurality of layers having a resistance difference, and the metal wire 610 under the contact hole 181 has an undercut portion B. FIG.

In the present embodiment, the metal wire is illustrated as a double layer, but may be formed as a triple layer or a plurality of layers. Therefore, the undercut portion B is naturally formed when the uppermost layer of the metal wire is removed during the wet etching for forming the contact hole 181. The undercut portion B is a structure that is susceptible to static electricity, and when static electricity is induced, sparks are generated by the induced static electricity to become a place where static electricity disappears.

The flow of static electricity in the antistatic pattern described above is as follows. First, when static electricity flows into the metal wire 610 from the outside, the static electricity is moved and stored along the metal wire 610 to the metal cap 620. If the contact hole 181 including the undercut portion B is formed in the metal wire 610, the static electricity first flows into the undercut portion B, and sparks are generated by the introduced static electricity to dissipate the static electricity by heat. At this time, the static electricity that is not extinguished is moved to the metal cap 620 along the metal wire 610 and stored.

Second Embodiment

2A is a schematic layout view illustrating a thin film transistor substrate according to the present invention, and FIG. 2B is a cross-sectional view taken along line IIb-IIb ′ of FIG. 2A.

The second embodiment is to dissipate more static electricity than the first embodiment, and provides an antistatic pattern in which a path for distributing static electricity is further formed.

As shown in FIG. 2, in the antistatic pattern according to the second embodiment, the first metal line 610a and the first metal cap 620a are formed on the same layer as the data line, and the antistatic pattern according to the second embodiment is formed on the same layer as the gate line. The second metal wire 610b and the second metal cap 620b are formed. A first metal piece 640a connected to the first metal wire 610a and a second metal piece 640b connected to the second metal wire 610b are formed.

The first metal wire 610a and the second metal wire 610b are formed to have a parallel planar pattern, and the first metal piece 640a and the second metal piece 640b are formed at a predetermined distance apart from each other. This is to allow the static electricity to move in only one direction and prevent the static electricity from flowing back.

In addition, an electrostatic induction pattern formed in the first embodiment may be further formed on one end of the first metal wire 610a or the second metal wire 610b.

The operation of the antistatic pattern according to the second embodiment is as follows. First, static electricity is introduced through the static electricity induction pattern 630 formed in the first metal wire 610a, and the static electricity flows into the undercut portion B formed under the contact hole, and sparks according to the static electricity introduced. Is generated and static electricity disappears by heat. Then, the static electricity that is not dissipated is moved to the first metal cap 620a along the first metal wire 610a or to the second metal piece 640b through the first metal piece 640a.

Thereafter, the static electricity moved to the second metal piece 640b flows into the undercut portion B formed under the contact hole 182 connected to the second metal wire 610b, and sparks are generated by the static electricity introduced. Occurs and disappears. In order to generate more sparks, a contact hole 183 may be further formed in a predetermined region of the second metal wire 610b. At this time, the static electricity that is not dissipated is moved and stored along the second metal wire 610b to the second metal cap 620b.

When the electrostatic induction pattern 630 is formed on the second metal wire 610b, since the second metal wire 610b forms a higher voltage than the first metal wire 610a, the flow of static electricity is increased from the second metal wire 610b to the first metal wire ( 610a).

[Examples 3 and 4]

3 and 4 are schematic layout views illustrating a thin film transistor substrate according to the present invention.

Unlike the metal caps 620, 621a and 621b of the third and fourth embodiments, the metal caps 620, 621a and 621b are formed to be dissipated after the static electricity is stored, unlike the metal caps 620, 620a and 620b of the first and second embodiments. That is, as shown in Fig. 3 or 4, the metal caps (620, 620a, 620b) is formed to have a plurality of branches (D1, D2).

As shown in FIG. 4, when the first and second metal caps 621a and 621b are formed, the first metal cap 621a and the second metal cap 621b cross each other.

These branches (D1, D2) is to provide a corner (C) vulnerable to static electricity and when a plurality of such structures are formed, the static electricity is induced to the corner (C) and disappears while sparking occurs. Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, the present invention forms a structure for blocking or disappearing in several steps to dissipate or block the static electricity so that the static electricity is completely disappeared or prevented. Therefore, the defect of the thin film transistor generated by the inflow of static electricity to the thin film transistor can be minimized.

Claims (9)

A thin film transistor substrate comprising a gate wiring, a data wiring, a pixel electrode, and a thin film transistor connected thereto, A metal line formed on the same layer as the data line or gate line, The thin film transistor substrate of claim 1, wherein an electrostatic protection pattern including a metal cap formed at one end of the metal line is separated from the thin film transistor by a predetermined distance. A thin film transistor substrate comprising a gate wiring, a data wiring, a pixel electrode, and a thin film transistor connected thereto, A first metal wire formed long in the same layer as the data wire, A first metal cap formed at one end of the first metal wire, A second metal wire parallel to the first metal wire and long in the same layer as the gate wire; A second metal cap formed at one end of the second metal wire The thin film transistor substrate, wherein the electrostatic protection pattern comprising a predetermined distance away from the thin film transistor. In claim 1, The metal cap is a thin film transistor substrate is formed to have a plurality of branches. In claim 2, The first and second metal caps are formed to have a plurality of branches and the first and second metal caps are formed to cross each other. In claim 1, The thin film transistor substrate comprising a triangular pattern on the outer circumference of the metal line. The method of claim 1 or 2, The thin film transistor substrate further comprising an insulating layer covering the electrostatic protection pattern, the insulating layer having a contact hole exposing the metal line. In claim 6, The metal line is formed of a plurality of layers, the thin film transistor substrate having an undercut portion formed under the contact hole. In claim 7, A thin film transistor substrate comprising a metal piece connected to the metal line through the contact hole. In claim 2, The thin film transistor substrate comprising a triangular pattern on the outer circumference of the first metal line and the second metal line.

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