KR100866131B1 - A sense amplifier layout method - Google Patents

A sense amplifier layout method Download PDF

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KR100866131B1
KR100866131B1 KR1020060132015A KR20060132015A KR100866131B1 KR 100866131 B1 KR100866131 B1 KR 100866131B1 KR 1020060132015 A KR1020060132015 A KR 1020060132015A KR 20060132015 A KR20060132015 A KR 20060132015A KR 100866131 B1 KR100866131 B1 KR 100866131B1
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region
type junction
well
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well region
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KR20080058004A (en
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김종수
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Abstract

본 발명은 반도체 메모리 소자에 관한 것으로, 특히, 백바이어스를 인가하는 센스 앰프의 레이아웃 방법에 관하여 개시한다. 개시된 본 발명은 반도체 기판의 소정 영역에 형성되는 P웰 영역, 반도체 기판의 소정 영역에 상기 P웰 영역과 이격되어 형성되는 N웰 영역, P웰 영역의 일측면으로부터 이격되어 형성되는 제1 N형 접합영역, N웰 영역의 일측면으로부터 이격되어 형성되는 제2 N형 접합영역, 및 N웰 영역을 제외한 P웰 영역과 제1 및 제2 N형 접합영역을 감싸며 형성되는 DN웰 영역을 포함하여 형성되어, N웰을 DN웰과 분리하여 N웰의 백바이어스 전압을 조절함으로써 센스앰프의 센싱 감도를 증가시키는 효과가 있다.

Figure R1020060132015

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a layout method of a sense amplifier applying a back bias. The disclosed invention includes a P well region formed in a predetermined region of a semiconductor substrate, an N well region formed spaced apart from the P well region in a predetermined region of the semiconductor substrate, and a first N type formed spaced apart from one side of the P well region. A junction region, a second N-type junction region formed to be spaced apart from one side of the N well region, and a DN well region formed to surround the P well region and the first and second N-type junction regions except for the N well region. The N well is separated from the DN well, thereby adjusting the back bias voltage of the N well, thereby increasing the sensing sensitivity of the sense amplifier.

Figure R1020060132015

Description

센스 앰프의 레이아웃 방법{A sense amplifier layout method}A sense amplifier layout method

도 1은 종래의 센스 앰프의 웰 구조를 나타내는 평면도.1 is a plan view showing a well structure of a conventional sense amplifier.

도 2는 도 1을 A1-A2선으로 절단한 단면도.2 is a cross-sectional view taken along the line A1-A2 in FIG. 1.

도 3은 본 발명의 실시예에 따른 센스 앰프의 웰 구조를 나타내는 평면도.3 is a plan view showing a well structure of a sense amplifier according to an embodiment of the present invention.

도 4는 도 3을 B1-B2선으로 절단한 단면도.4 is a cross-sectional view taken along the line B1-B2 in FIG. 3.

본 발명은 반도체 메모리 소자에 관한 것으로, 특히, 백바이어스를 인가하는 센스 앰프의 레이아웃 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a layout method of a sense amplifier applying a back bias.

반도체 메모리 소자는 크게 셀영역(cell region), 코어영역(core region) 및 주변영역(periphery region)으로 구분된다. 셀영역에는 다수의 셀들이 배치되고, 코어영역에는 서브 워드라인 드라이버(sub word line drive ; SWD) 및 센스앰프(sense amplifier; SA) 등이 배치된다.The semiconductor memory device is largely divided into a cell region, a core region, and a peripheral region. A plurality of cells are disposed in the cell region, and a sub word line driver (SWD), a sense amplifier (SA), and the like are disposed in the core region.

최근 반도체 메모리 소자는 고집적화로 인해 트랜지스터의 채널길이(channel length)가 감소하고 있으며, 채널길이 감소로 인한 누설 전류(leakage current) 증가를 줄이기 위해 트랜지스터의 문턱전압(threshold voltage, Vt)를 높이는 방법을 사용한다. 즉, 트래지스터의 백바이어스(back bias) 전압을 높게 인가하여 문턱전압을 높이고 있다. Recently, the semiconductor memory device has been decreasing the channel length of the transistor due to the high integration, and the method of increasing the threshold voltage (Vt) of the transistor in order to reduce the leakage current caused by the decrease in the channel length. use. That is, the threshold voltage is increased by applying a high back bias voltage of the transistor.

도 1 및 도 2을 참조하여 종래의 센스앰프 웰 구조를 살펴보면, 센스앰프는 상호 래치를 이룬 NMOS 트랜지스터와 PMOS 트랜지스터가 각각 P웰(P well), N웰(N well) 내에 형성되며, DN웰이 이들 P웰과 N웰을 감싸고 있다. Referring to FIGS. 1 and 2, a conventional sense amplifier well structure is described. In the sense amplifier, an NMOS transistor and a PMOS transistor that are latched with each other are formed in a P well and an N well, respectively, and a DN well. These P and N wells are enclosed.

구체적으로는, 반도체 기판(100)의 소정 영역에 DN웰(110)이 형성되고, DN웰(110) 내에는 P웰(120)과 N웰(130)이 서로 분리되어 나란히 형성되며, DN웰(110) 내의 가장자리 영역에 웰 바이어스(well bias)를 인가하기 위한 N형 접합영역(N-Junction; 140, 150)이 형성된다. Specifically, the DN well 110 is formed in a predetermined region of the semiconductor substrate 100, and the P well 120 and the N well 130 are separated from each other and formed side by side in the DN well 110. N-junctions (N-Junction) 140 and 150 for applying a well bias to the edge region within 110 are formed.

P웰(120) 내에는 센스앰프의 NMOS 트랜지스터가 형성될 N형 접합영역(N-Junction; 122)과, NMOS 트랜지스터의 백 바이어스를 인가하기 위한 P형 접합영역(P-Junction; 124)이 형성된다. An N-type junction region (N-Junction) 122 in which the NMOS transistor of the sense amplifier is to be formed and a P-type junction region (P-Junction) 124 for applying a back bias of the NMOS transistor are formed in the P well 120. do.

N웰(130) 내에는 PMOS 트랜지스터가 형성될 P형 접합영역(132)과, PMOS 트랜지스터의 백 바이어스를 인가하기 위한 N형 접합영역(134)이 형성된다.In the N well 130, a P-type junction region 132 in which a PMOS transistor is to be formed and an N-type junction region 134 for applying a back bias of the PMOS transistor are formed.

그리고, P웰(120)의 상부는 절연막, 게이트 도전막 및 하드 마스크막의 적층막으로 이루어진 링(ring) 형태의 NMOS형 게이트들(126, 128)이 형성되고, N웰(130)의 상부는 링 형태의 PMOS형 게이트들(136, 138)이 형성된다. The upper portion of the P well 120 is formed with ring-shaped NMOS gates 126 and 128 formed of an insulating film, a gate conductive film, and a stacked layer of a hard mask film. Ring-shaped PMOS gates 136 and 138 are formed.

P웰(120) 상부에 형성된 콘택(a1 내지 a3)에 의해 제1 NMOS 트랜지스터가 형성되고, 콘택(a3 내지 a5)에 의해 제2 NMOS 트랜지스터가 형성되며, 콘택(a6)은 P접합영역(124)에 배치되어 백바이어스 전압 VBB와 연결된다. The first NMOS transistor is formed by the contacts a1 to a3 formed on the P well 120, the second NMOS transistor is formed by the contacts a3 to a5, and the contact a6 is the P junction region 124. Is connected to the back bias voltage VBB.

N웰(130) 상부에 형성된 콘택(a7 내지 a9)에 의해 제1 PMOS 트랜지스터가 형성되고, 콘택(a9 내지 a11)에 의해 제2 PMOS 트랜지스터가 형성되며, 콘택(a12)은 N접합영역(134)에 배치되어 백바이어스 전압 VPP와 연결된다. The first PMOS transistor is formed by the contacts a7 through a9 formed on the N well 130, the second PMOS transistor is formed by the contacts a9 through a11, and the contact a12 is an N junction region 134. Is connected to the back bias voltage VPP.

N형 접합영역(140, 150) 내에 형성된 콘택(a14, a15)은 DN웰(110)과 서브 워드라인 드라이브의 백바이어스 전압인 VPP와 연결된다. The contacts a14 and a15 formed in the N-type junction regions 140 and 150 are connected to the DN well 110 and VPP, which is a back bias voltage of the sub word line drive.

상기와 같이, 종래의 센스앰프는 PMOS 트랜지스터가 형성되는 N웰(130)의 백바이어스 전압을 DN웰(110)의 백바이스 전압 VPP로 제공함으로써 상승된 문턱 전압(Vt)이 인가된다. As described above, in the conventional sense amplifier, the raised threshold voltage Vt is applied by providing the back bias voltage of the N well 130 in which the PMOS transistor is formed to the back bias voltage VPP of the DN well 110.

한편, 센스앰프의 문턱전압 상승은 전류 전달 능력(current driveability)을 감소시켜 센싱 감도를 저하시켜 tRCD(ras to cas delay time) 특성이 나빠질 수 있다. 따라서, N웰(130)에 인가되는 백바이어스 전압을 낮추어야 한다.On the other hand, an increase in the threshold voltage of the sense amplifier may reduce current driveability, thereby lowering the sensing sensitivity, thereby degrading a ras to cas delay time (tRCD) characteristic. Therefore, the back bias voltage applied to the N well 130 must be lowered.

그러나, 종래의 센스앰프는 N웰(130)이 DN웰(110)에 의해 감싸여지 구조이므로, DN웰(110)과 다른 백바이어스를 N웰(130)에 인가하기 위해서는 N웰(130)을 DN웰(110)로부터 분리시켜야 하지만, 반도체 메모리 소자의 설계에 관한 디자인 규칙(desgin rule)에서 요구되는 웰과 웰 사이의 마진(margin)을 확보가 어려운 문제가 있다. However, in the conventional sense amplifier, since the N well 130 is structured to be surrounded by the DN well 110, the N well 130 may be applied to apply the back well different from the DN well 110 to the N well 130. Although it should be separated from the DN well 110, there is a problem that it is difficult to secure a margin between the well and the well required by a design rule for designing a semiconductor memory device.

따라서, 본 발명의 목적은 센스앰프의 DN웰과 N웰을 분리하는 마진을 확보하는 센스앰프 레이아웃 방법을 제공하는 데 있다. Accordingly, an object of the present invention is to provide a sense amplifier layout method for securing a margin separating the DN well and the N well of the sense amplifier.

본 발명의 다른 목적은 상기한 센스앰프의 N웰의 백바이어스 전압을 조절함 으로써 센싱 감도를 개선하는 데 있다. Another object of the present invention is to improve the sensing sensitivity by adjusting the back bias voltage of the N well of the sense amplifier.

상기한 바와 같은 목적을 달성하기 위한 본 발명의 센스앰프 레이아웃 방법은 반도체 기판의 소정 영역에 형성되는 P웰 영역; 상기 반도체 기판의 소정 영역에 상기 P웰 영역과 이격되어 형성되는 N웰 영역; 상기 P웰 영역의 일측면으로부터 이격되어 형성되는 제1 N형 접합영역; 상기 N웰 영역의 일측면으로부터 이격되어 형성되는 제2 N형 접합영역; 및 상기 N웰 영역을 제외한 상기 P웰 영역과 상기 제1 및 제2 N형 접합영역을 감싸며 형성되는 DN웰 영역;을 포함하여 형성됨을 특징으로 한다.
상기 P웰 영역은 NMOS 트랜지스터가 형성되는 제3 N형 접합영역; 및 상기 제3 N형 접합영역과 소정 간격 이격거리를 두고 형성되는 백바이어스 전압이 인가되는 제1 P형 접합영역;을 포함하여 형성됨이 바람직하다.
상기 NMOS 트랜지스터는, 상기 P웰 영역과 상기 제3 N형 접합영역에 걸쳐 링게이트가 형성되고, 상기 링게이트의 내부 영역의 상기 제3 N형 접합영역 상에 드레인이 형성되며, 상기 링게이트의 외부 영역의 상기 제3 N형 접합영역 상에 의해 소스가 형성된다.
상기 제1 P형 접합영역은 접지전원 전원과 연결됨이 바람직하다.
상기 N웰 영역은 PMOS 트랜지스터가 형성되는 제2 P형 접합영역; 및 상기 제2 P형 접합영역과 인접하여 형성되는 백바이어스 전압이 인가되는 제4 N형 접합영역; 을 포함하여 형성된다.
상기 PMOS 트랜지스터는, 상기 N웰 영역과 상기 제2 P형 접합영역에 걸쳐 링게이트가 형성되고, 상기 링게이트의 내부 영역의 상기 제2 P형 접합영역 상에 드레인이 형성되며, 상기 링게이트의 외부 영역의 상기 제2 P형 접합영역 상에 의해 소스가 형성된다.
상기 제4 N형 접합영역은 상기 링게이트와 오버랩되지 않은 상기 제2 P형 접합영역과 맞닿게 형성됨이 바람직하다.
상기 제4 N형 접합영역은 상기 제2 P형 접합영역과 공통으로 연결된 콘택을 통해 상기 PMOS 트랜지스터의 드라이브 전압에 연결됨이 바람직하다.
상기 제1 및 제2 N형 접합영역은 전원 전압에 연결됨이 바람직하다.According to another aspect of the present invention, there is provided a sense amplifier layout method including: a P well region formed in a predetermined region of a semiconductor substrate; An N well region spaced apart from the P well region in a predetermined region of the semiconductor substrate; A first N-type junction region spaced apart from one side of the P well region; A second N-type junction region spaced apart from one side of the N well region; And a DN well region formed to surround the P well region except for the N well region and the first and second N-type junction regions.
The P well region may include a third N-type junction region in which an NMOS transistor is formed; And a first P-type junction region to which a back bias voltage formed at a predetermined distance from the third N-type junction region is applied.
In the NMOS transistor, a ring gate is formed over the P well region and the third N-type junction region, and a drain is formed on the third N-type junction region in an inner region of the ring gate. A source is formed on the third N-type junction region in the outer region.
The first P-type junction region is preferably connected to a ground power source.
The N well region may include a second P-type junction region in which a PMOS transistor is formed; And a fourth N-type junction region to which a back bias voltage formed adjacent to the second P-type junction region is applied. It is formed to include.
In the PMOS transistor, a ring gate is formed over the N well region and the second P-type junction region, and a drain is formed on the second P-type junction region in an inner region of the ring gate. A source is formed on the second P-type junction region of the outer region.
The fourth N-type junction region is preferably formed to be in contact with the second P-type junction region not overlapping the ring gate.
The fourth N-type junction region is preferably connected to the drive voltage of the PMOS transistor through a contact connected in common with the second P-type junction region.
Preferably, the first and second N-type junction regions are connected to a power supply voltage.

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이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

도 3 및 도 4을 참조하여 본 발명의 실시예에 따른 센스앰프 웰 구조를 살펴보면, 센스앰프는 상호 래치를 이룬 NMOS 트랜지스터와 PMOS 트랜지스터가 각각 P웰(P well, 320), N웰(N well, 330) 내에 형성되며, N웰(330)이 DN(310)웰과 분리되어 형성된다. Referring to FIGS. 3 and 4, a sense amplifier well structure according to an exemplary embodiment of the present invention may be described in which a sense amplifier includes a P well transistor (P well, 320) and an N well each having an NMOS transistor and a PMOS transistor that are latched with each other. 330 is formed, and the N well 330 is formed separately from the DN 310 well.

구체적으로는, 반도체 기판(300) 내의 소정 영역에 P웰 영역(320)과 N웰 영역(330)이 서로 소정 거리 이격되어 나란히 형성되고, 이들 P웰 영역(320)과 N웰 영역(330)의 일측면으로부터 이격되어 제1 및 제 2 N형 접합영역(340, 350)이 형성되며, N웰 영역(330)을 제외한 P웰 영역(320)과 제1 및 제2 N형 접합영역(340, 350)을 감싸며 DN웰 영역(310)이 형성된다. 즉, N웰(330)은 DN웰(310) 사이에 분리되어 형성된다. Specifically, the P well region 320 and the N well region 330 are formed side by side at a predetermined distance from each other in the semiconductor substrate 300, and the P well region 320 and the N well region 330 are formed side by side. The first and second N-type junction regions 340 and 350 are formed to be spaced apart from one side of the P-well region 320 and the first and second N-type junction regions 340 except for the N well region 330. And 350, a DN well region 310 is formed. That is, the N well 330 is formed to be separated between the DN well 310.

P웰(320) 내에는 센스앰프의 NMOS 트랜지스터가 형성될 N형 접합영역(322) 과, NMOS 트랜지스터의 백 바이어스를 인가하기 위한 P형 접합영역(324)이 소정 간격 이격되어 형성된다. In the P well 320, an N-type junction region 322 in which an NMOS transistor of a sense amplifier is to be formed, and a P-type junction region 324 for applying a back bias of the NMOS transistor are formed at predetermined intervals.

N웰(330) 내에는 PMOS 트랜지스터가 형성될 P형 접합영역(332)이 형성되고, P형 접합영역(332)의 일측면과 맞닿아 PMOS 트랜지스터의 백 바이어스를 인가하기 위한 N형 접합영역(334)이 형성된다. 이로써, 종래의 P형 접합영역(도 2의 132)과 N형 접합영역(도 2의 134) 사이의 이격 거리 D1을 웰 분리 마진 D2 + D3으로 확보한다. 여기서, D2, D3는 N웰(330)을 DN웰(310) 사이의 마진으로 각각 0.6um 이상이다. In the N well 330, a P-type junction region 332 to be formed with a PMOS transistor is formed, and the N-type junction region for contacting one side of the P-type junction region 332 to apply a back bias of the PMOS transistor ( 334 is formed. Thus, the separation distance D1 between the conventional P-type junction region 132 in FIG. 2 and the N-type junction region 134 in FIG. Here, D2 and D3 are the margins between the N wells 330 and the DN wells 310, respectively, of 0.6 μm or more.

P웰(320)의 상부는 절연막, 게이트 도전막 및 하드 마스크막의 적층막으로 이루어진 링 형태의 NMOS형 게이트들(326, 328)이 형성되고, N웰(330)의 상부는 링 형태의 PMOS형 게이트들(336, 338)이 형성된다. Ring-shaped NMOS gates 326 and 328 formed of an insulating film, a gate conductive film, and a hard mask film are formed on the upper portion of the P well 320, and a ring-shaped PMOS type is formed on the upper portion of the N well 330. Gates 336 and 338 are formed.

P웰(320) 상부에 형성된 콘택(c1 내지 c3)에 의해 제1 NMOS 트랜지스터가 형성되고, 콘택(c3 내지 c5)에 의해 제2 NMOS 트랜지스터가 형성되며, 콘택(c6)은 P형 접합영역(324)에 배치되어 백바이어스 전압 VBB와 연결된다. The first NMOS transistor is formed by the contacts c1 through c3 formed on the P well 320, the second NMOS transistor is formed by the contacts c3 through c5, and the contact c6 has a P-type junction region ( Disposed at 324 and connected to the back bias voltage VBB.

다시말해, 콘택(c1)은 P웰(320) 상부에 형성된 링 게이트(326)와 비트라인 /BL을 연결하고, 콘택(c2)은 링 게이트(326) 내부의 N형 접합영역(322)과 비트라인 BL을 연결한다. 그리고, 콘택(c3)은 링 게이트(326) 외부의 N형 접합영역(322)와 접지전압 VSS를 연결하고, 콘택(c4)은 링 게이트(328) 내부의 N형 접합영역(322)과 비트라인 /BL을 연결하며, 콘택(c5)은 P웰(320) 상부에 형성된 링 게이트(328)와 비트라인 BL을 연결한다.In other words, the contact c1 connects the ring gate 326 formed on the P well 320 and the bit line / BL, and the contact c2 is connected to the N-type junction region 322 inside the ring gate 326. The bit line BL is connected. The contact c3 connects the N-type junction region 322 outside the ring gate 326 and the ground voltage VSS, and the contact c4 is a bit connected to the N-type junction region 322 inside the ring gate 328. The line / BL is connected, and the contact c5 connects the ring gate 328 formed on the P well 320 and the bit line BL.

N웰(330) 상부에 형성된 콘택(c7 내지 c9)에 의해 제1 PMOS 트랜지스터가 형성되고, 콘택(c9 내지 c11)에 의해 제2 PMOS 트랜지스터가 형성되며, 콘택(c12, c13)은 P형 접합영역(332)와 N형 접합영역(334) 양측에 걸쳐서 배치되어 백바이어스 전압 VCORE와 연결된다. The first PMOS transistor is formed by the contacts c7 to c9 formed on the N well 330, the second PMOS transistor is formed by the contacts c9 to c11, and the contacts c12 and c13 are P-type junctions. The region 332 and the N-type junction region 334 are disposed on both sides thereof and are connected to the back bias voltage VCORE.

다시말해, 콘택(c7)은 N웰(330) 상부에 형성된 링 게이트(338)와 비트라인 BL을 연결하고, 콘택(c8)는 링 게이트(338) 내부의 P형 접합영역(332)과 비트라인 /BL을 연결한다. 그리고, 콘택(c9)은 링 게이트(338) 외부의 P형 접합영역(332)와 PMOS 트랜지스터의 드라이브 전압 VCORE를 연결하고, 콘택(c10)은 링 게이트(336) 내부의 P형 접합영역(332)과 비트라인 BL을 연결하며, 콘택(c11)은 N웰(330) 상부에 형성된 링 게이트(336)와 비트라인 /BL을 연결한다. In other words, the contact c7 connects the ring gate 338 formed on the N well 330 and the bit line BL, and the contact c8 is connected to the P-type junction region 332 and the bit inside the ring gate 338. Connect the line / BL. The contact c9 connects the P-type junction region 332 outside the ring gate 338 and the drive voltage VCORE of the PMOS transistor, and the contact c10 is the P-type junction region 332 inside the ring gate 336. ) And the bit line BL, and the contact c11 connects the ring gate 336 formed on the N well 330 and the bit line / BL.

여기서, N형 접합영역(334)은 오버레이 마진을 확보하기 위해 링 게이트(336)가 형성된 N웰(330) 이외의 P형 접합영역(332)과 맞닿게 형성된다. Here, the N-type junction region 334 is formed to be in contact with the P-type junction region 332 other than the N well 330 in which the ring gate 336 is formed to secure the overlay margin.

그리고, 콘택(c12, c13)은 P형 접합영역(332) 상부와 N형 접합영역(334) 상부에 걸쳐서 형성되며, PMOS 트랜지스터 드라이브 전압 VCORE과 연결된다. 이에 따라, 종래의 VPP 백바이어스 라인을 제거할 수 있다. The contacts c12 and c13 are formed over the P-type junction region 332 and the N-type junction region 334 and are connected to the PMOS transistor drive voltage VCORE. Thus, the conventional VPP back bias line can be eliminated.

상술한 바와 같이, N웰(330)의 P형 접합영역(332)와 N형 접합영역(334)을 맞닿게 형성하여, 이들 사이의 이격 거리를 N웰(330)과 DN웰(310)의 분리 마진으로 확보하고, N웰(330)의 백바이어스로 PMOS 트랜지스터 드라이브 전압 VCORE을 인가함으로써, 트랜지스터의 문턱전압을 조절한다. 그 결과, 센스앰프의 전류 전달 능령이 개선되어 센싱 감도를 향상시킨다. As described above, the P-type junction region 332 and the N-type junction region 334 of the N well 330 are formed to abut, and the separation distance therebetween is defined by the N well 330 and the DN well 310. The isolation margin is secured, and the threshold voltage of the transistor is controlled by applying the PMOS transistor drive voltage VCORE to the back bias of the N well 330. As a result, the current transfer capability of the sense amplifier is improved to improve the sensing sensitivity.

따라서, 본 발명에 의하면, 센스앰프의 웰 분리를 통해 백바이어스 전압을 조절함으로써 센스앰프의 센싱 감도를 증가시키는 효과가 있다.Therefore, according to the present invention, there is an effect of increasing the sensing sensitivity of the sense amplifier by adjusting the back bias voltage through the well separation of the sense amplifier.

또한, 본 발명의 목적은, 상기의 웰을 분리하기 위한 마진을 반도체 메모리의 면적 변경 없이 확보하는 센스앰프 레이아웃 방법을 제공하는 효과가 있다. It is also an object of the present invention to provide a sense amplifier layout method for securing a margin for separating the wells without changing the area of the semiconductor memory.

Claims (9)

반도체 기판의 소정 영역에 형성되는 P웰 영역;A P well region formed in a predetermined region of the semiconductor substrate; 상기 반도체 기판의 소정 영역에 상기 P웰 영역과 이격되어 형성되는 N웰 영역;An N well region spaced apart from the P well region in a predetermined region of the semiconductor substrate; 상기 P웰 영역의 일측면으로부터 이격되어 형성되는 제1 N형 접합영역;A first N-type junction region spaced apart from one side of the P well region; 상기 N웰 영역의 일측면으로부터 이격되어 형성되는 제2 N형 접합영역; 및A second N-type junction region spaced apart from one side of the N well region; And 상기 N웰 영역을 제외한 상기 P웰 영역과 상기 제1 및 제2 N형 접합영역을 감싸며 형성되는 DN웰 영역;A DN well region formed to surround the P well region excluding the N well region and the first and second N-type junction regions; 을 포함하여 형성됨을 특징으로 하는 센스앰프 레이아웃 방법.A sense amplifier layout method characterized in that it is formed, including. 제 1 항에 있어서, The method of claim 1, 상기 P웰 영역은 The P well region is NMOS 트랜지스터가 형성되는 제3 N형 접합영역; 및A third N-type junction region in which an NMOS transistor is formed; And 상기 제3 N형 접합영역과 소정 간격 이격거리를 두고 형성되는 백바이어스 전압이 인가되는 제1 P형 접합영역;A first P-type junction region to which a back bias voltage formed at a predetermined distance from the third N-type junction region is applied; 을 포함하여 형성됨을 특징으로 하는 센스앰프 레이아웃 방법.A sense amplifier layout method characterized in that it is formed, including. 제 2 항에 있어서, The method of claim 2, 상기 NMOS 트랜지스터는,The NMOS transistor, 상기 P웰 영역과 상기 제3 N형 접합영역에 걸쳐 링게이트가 형성되고, A ring gate is formed over the P well region and the third N-type junction region, 상기 링게이트의 내부 영역의 상기 제3 N형 접합영역 상에 드레인이 형성되며, A drain is formed on the third N-type junction region of the inner region of the ring gate, 상기 링게이트의 외부 영역의 상기 제3 N형 접합영역 상에 의해 소스가 형성됨을 특징으로 하는 센스엠프 레이아웃 방법.And a source is formed on the third N-type junction region in an outer region of the ring gate. 제 2 항에 있어서, The method of claim 2, 상기 제1 P형 접합영역은 접지전원 전원과 연결됨을 특징으로 하는 센스앰프 레이아웃 방법.And the first P-type junction region is connected to a ground power source. 제 1 항에 있어서, The method of claim 1, 상기 N웰 영역은 The N well region is PMOS 트랜지스터가 형성되는 제2 P형 접합영역; 및A second P-type junction region in which a PMOS transistor is formed; And 상기 제2 P형 접합영역과 인접하여 형성되는 백바이어스 전압이 인가되는 제4 N형 접합영역;A fourth N-type junction region to which a back bias voltage is formed adjacent to the second P-type junction region; 을 포함하여 형성됨을 특징으로 하는 센스앰프 레이아웃 방법.A sense amplifier layout method characterized in that it is formed, including. 제 5 항에 있어서, The method of claim 5, wherein 상기 PMOS 트랜지스터는,The PMOS transistor, 상기 N웰 영역과 상기 제2 P형 접합영역에 걸쳐 링게이트가 형성되고,A ring gate is formed over the N well region and the second P-type junction region, 상기 링게이트의 내부 영역의 상기 제2 P형 접합영역 상에 드레인이 형성되며,A drain is formed on the second P-type junction region of the inner region of the ring gate, 상기 링게이트의 외부 영역의 상기 제2 P형 접합영역 상에 의해 소스가 형성됨을 특징으로 하는 센스엠프 레이아웃 방법.And a source is formed on the second P-type junction region in an outer region of the ring gate. 제 6 항에 있어서, The method of claim 6, 상기 제4 N형 접합영역은 상기 링게이트와 오버랩되지 않은 상기 제2 P형 접합영역과 맞닿게 형성됨을 특징으로 하는 센스앰프 레이아웃 방법.And the fourth N-type junction region is in contact with the second P-type junction region not overlapping the ring gate. 제 6 항에 있어서, The method of claim 6, 상기 제4 N형 접합영역은 상기 제2 P형 접합영역과 공통으로 연결된 콘택을 통해 상기 PMOS 트랜지스터의 드라이브 전압에 연결됨을 특징으로 하는 센스앰프 레이아웃 방법. And the fourth N-type junction region is connected to the drive voltage of the PMOS transistor through a contact connected in common with the second P-type junction region. 제 1 항에 있어서, The method of claim 1, 상기 제1 및 제2 N형 접합영역은 전원 전압에 연결됨을 특징으로 하는 센스앰프 레이아웃 방법.And the first and second N-type junction regions are connected to a power supply voltage.
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JPH07142605A (en) * 1993-11-22 1995-06-02 Fujitsu Ltd Semiconductor device and manufacturing method thereof
KR20000001163A (en) * 1998-06-09 2000-01-15 김영환 Sense amplifier lay out structure of semiconductor memory
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* Cited by examiner, † Cited by third party
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