KR100863024B1 - Circuit for compensating equaliation and semiconductor memory apparatus using the same - Google Patents

Abstract

A circuit for compensating for equalization and a semiconductor memory device using the same are provided to enhance reliability thereof by ensuring an equalize timing margin according to characteristic variation or resistance of word lines. A circuit for compensating for equalization of a semiconductor memory device includes a word line detection unit(100) and an equalize signal controller(200). The word line detection unit detects the level of word lines and generates a detection signal. The equalize signal controller compensates for timing of equalization signals in response to the detection signal and outputs an equalize compensation signal. The word line detection unit outputs the detection signal by detecting a reference voltage and the level of the word line.

Description

Equalization Correction Circuit and Semiconductor Memory Device Using the Same

The present invention relates to a semiconductor integrated circuit, and more particularly, to an equalization correction circuit for securing an equalization timing margin of a bit line and a semiconductor memory device using the same.

In general, a memory cell includes a plurality of memory cells including one transistor and one capacitor, and the memory cell is selected by a word line SWL connected to a gate terminal of the transistor, and the voltage of the selected memory cell is applied to the bit line. When applied, the sensing process is achieved by amplifying them.

1 is a circuit diagram illustrating a driving of a semiconductor memory device according to the related art.

Referring to FIG. 1, when the equalization signal BLEQ of the bit line sense amplifier is disabled to a 'low' level in the semiconductor memory device, the first to third NMOS transistors N1, N1, of the equalization execution unit 10 are disabled. N2 and N3 are turned off to stop equalization of the bit lines BL and BLB. At this time, when the word line SWL is enabled and the fourth NMOS transistor N4 is turned on, the voltage of the selected cell is transferred to the bit lines BL and BLB, and the data stored in the capacitor is charged sharing. Sharing) is started. When the voltage of the cell is applied to the bit lines BL and BLB, the sense amplifier 30 performs a sensing operation to amplify the data. If the word line SWL is disabled during the precharge and the fourth NMOS transistor N4 of the memory cell 20 is turned off, the bit lines BL and BLB are floated. Subsequently, the equalization execution unit 10 operates to disable the equalization signal BLEQ to a 'high' level to equalize the bit lines BL and BLB to the bit line precharge voltage VBLP. In this case, the semiconductor memory device receives an equalization signal BLEQ before the word line SWL is completely closed due to a change in characteristics due to a resistance value of the word line SWL or loading depending on the size of the mat MAT. Therefore, the bit line precharge voltage VBLP is supplied to the cell, thereby storing the wrong data in the cell, thereby causing the cell to be defective.

2 is a driving timing diagram of a semiconductor memory device according to the related art.

Referring to FIG. 2, in the semiconductor memory device, in general, the equalization timing of the word line SWL and the bit lines BL and BLB is equal to the bit line BL and BLB after the word line SWL is completely turned off. Equalize must be enabled. However, since the resistance value of the word line SWL is different, the characteristics of the word line SWL may be changed in the same device, and the loading of the word line SWL varies according to the size of the mat MAT. The slope of the SWL is increased. Therefore, before the word line SWL is completely closed, the bit lines BL and BLB equalization are enabled, thereby changing the data value of the cell, thereby causing a failure. That is, as the slope of the word line SWL increases when precharging, the equalization timing of the bit lines BL and BLB should be adjusted.

In the semiconductor memory device according to the related art, after the equalization signal BLEQ is disabled from the 'high' level to the 'low' level, the word line SWL is enabled to the 'high' level. When the word line SWL is enabled, charge sharing is started and data is amplified and loaded on the bit lines BL and BLB. In order to precharge the data on the bit lines BL and BLB, the word line SWL is disabled to a 'low' level, but the equalization signal BLEQ is enabled before the word line SWL is completely closed. In this case, the bit line precharge voltage VBLP is supplied to the cell to change data stored in the memory cell 20, thereby causing a defect. Here, the bit line precharge voltage VBLP is a voltage at an intermediate level between the core voltage VCORE and the ground voltage VSS. The bit lines BL and BLB have the equalization signal BLEQ enabled when the word line SWL is enabled, that is, while the fourth NMOS transistor N4 is turned on, thereby causing the bit line precharge voltage VBLP. Is equalized. Therefore, when the slope of the word line SWL is increased by the resistance value, the characteristic change of each device, or the loading due to the mat size, the bit line BL and BLB equalizes before the word line SWL is completely closed. There is a problem that the cell may be defective due to the rise enable and the data value of the memory cell 20 is changed.

The equalization correction circuit of a semiconductor memory device according to the present invention has an object to implement a reliable semiconductor memory device by controlling the bit line equalization timing according to the change of the word line characteristics.

An equalization correction circuit according to the present invention includes a word line detection unit for generating a detection signal by detecting a level of a word line, and an equalization outputting an equalization compensation signal by correcting a timing of the equalization signal in response to the detection signal. It includes a signal controller.

In an embodiment, a semiconductor memory device includes a memory cell selected at a word line enable state,

A bit line pair connected to the memory cell,

A sense amplifier for amplifying the data of the bit line pair, and

And an equalization unit for adjusting a timing for equalizing the bit line pairs according to the level of the word line.

The equalization correction circuit and the semiconductor memory device using the same according to the present invention secure an equalization timing margin according to a change in a resistance value or a characteristic of a word line, thereby implementing a reliable semiconductor memory device.

3 shows an equalization correction circuit of a semiconductor memory device according to the present invention.

Conventional semiconductor memory devices have a display of word lines (SWL) according to resistance values of word lines (SWLs) used in DRAM (Dynamic Random Access Memory), characteristics of each device, or mat size. The equalization signal BLEQ is enabled before the word timing SWL is completely turned off to equalize the bit lines BL and BLB to the precharge voltage VBLP. In this case, a problem occurs that data of a cell fails. In the present invention, in order to adjust the equalization timing of the word line SWL and the bit lines BL and BLB, the resistance value according to the slope of the word line SWL is sensed and thus the equalization signal BLEQ is detected. It is possible to delay the timing of the Able.

Referring to FIG. 3, the equalization control circuit of the semiconductor memory device may include a word line detector 100 configured to output a word line detection signal SWL_DET by comparing the reference voltage Vref and the word line voltage SWL_V, and the The equalization signal controller 200 receives the word line detection signal SWL_DET and the equalization signal BLEQ and outputs an equalization compensation signal BLEQ_C.

As shown in FIG. 1, the equalization compensation signal BLEQ_C is input to the equalizer 10 for performing an equalization operation of the bit lines BL and BLB connected to the sense amplifier 30.

4 illustrates the word line detector illustrated in FIG. 3.

Referring to FIG. 4, the word line detector 100 is a differential amplification type, and includes third to fourth PMOS transistors P3 and P4 having a current mirror structure, and seventh and eighth NMOS transistors having a differential input structure. N7 and N8, a ninth NMOS transistor N9 for enabling the differential amplified word line detector 100, and first to fourth resistors R1 to R4 for distributing the word line voltage SWL_V. It includes. The third PMOS transistor P3 includes a gate connected to the gate of the fourth PMOS transistor P4, a source connected to the pumping voltage VPP terminal, and a drain. The fourth PMOS transistor P4 includes a gate and a drain which are commonly connected to each other, and a source connected to the pumping voltage VPP. The seventh NMOS transistor N7 includes a gate connected to the reference voltage Vref, a drain connected to the drain of the third PMOS transistor P3, and a source. The eighth NMOS transistor N8 includes a gate connected to the second node S2, a drain connected to the first node S1, and a source connected to the source of the seventh NMOS transistor N7. The ninth NMOS transistor N9 includes a gate configured to receive an enable signal EN, a drain connected to the source of the eighth NMOS transistor N8, and a source connected to the ground voltage VSS terminal. The first to fourth resistors R1 to R4 are connected in series between a word line voltage SWL_V terminal and a ground voltage VSS terminal. Here, the pumping voltage VPP is a voltage output from the pumping voltage generating circuit and is a voltage having a potential higher than the power supply voltage VDD. In addition, the first to fourth resistors R1 to R4 may vary the word line voltage SWL_V from the ground voltage VSS to the pumping voltage VPP.

When the enable signal EN is enabled, the word line detector 100 operates to generate a word line detection signal SWL_DET by comparing the reference voltage Vref with the word line voltage SWL_V. .

When the reference voltage Vref is greater than the divided voltage VA obtained by dividing the word line voltage SWL_V into a resistor, the word line detection signal SWL_DET is at a 'high' level. When the reference voltage Vref is smaller than the division voltage VA, the word line detection signal SWL_DET is at a low level.

FIG. 5 illustrates the equalized signal controller shown in FIG. 3.

Referring to FIG. 5, the equalization signal controller 200 outputs a word line detection signal SWL_DET and an equalization compensation signal BLEQ_C having a timing margin in response to the equalization signal BLEQ.

The equalization signal controller 200 may include a signal combination unit 201 for outputting an equalization combination signal BLEQB in response to a word line detection signal SWL_DET and an equalization signal BLEQ, and the equalization combination signal ( And an output unit 203 for outputting the equalization compensation signal BLEQ_C in response to the delayed signal BLEQD, which delays the BLEQB by the delay time of the delay unit 202, and the equalized combination signal BLEQB. .

The signal combination unit 201 includes a NAND gate ND that receives the word line detection signal SWL_DET and the equalization signal BLEQ and outputs an equalization combination signal BLEQB.

The output unit 203 includes a noar gate NR for receiving the equalization combination signal BLEQB and the delay signal BLEQD and outputting the equalization compensation signal BLEQ_C.

When the word line detection signal SWL_DET is at the 'high' level and the equalization signal BLEQ is at the 'high' level, the equalization signal controller 200 is set to 'low'. A 'low' level equalization combination signal BLEQB and a 'low' level delay signal BLEQD are input to output the equalization compensation signal BLEQ_C at a 'high' level.

Further, when the word line detection signal SWL_DET is at the 'high' level and the equalization signal BLEQ is at the 'low' level, the equalization combination signal BLEQB is at the 'high' level, and the ' The equalization compensation signal BLEQ_C is input to the 'low' level by receiving the equalized combination signal BLEQB and the delay signal BLEQD having the high level.

When the equalization signal controller 200 has a low level, either the word line detection signal SWL_DET or the equalizing signal BLEQ, the equalization compensation signal BLEQ_C has a low level. do. Meanwhile, when the word line detection signal SWL_DET and the equalization signal BLEQ have a 'high' level, the equalization compensation signal BLEQ_C becomes a 'high' level.

6 is a timing diagram of an equalization correction circuit of the semiconductor memory device according to the present invention.

Referring to FIG. 6, after the equalization signal BLEQ is disabled, the word line SWL is enabled. However, in the conventional case, the equalization signal BLEQ is enabled before the word line SWL is completely closed, thereby causing a cell to fail. To correct this, when the word line voltage SWL_V is higher than the reference voltage Vref by comparing the reference voltage Vref and the word line voltage SWL_V, the word line detection signal SWL_DET is at the 'high' level. Transition to the 'low' level. The equalization signal BLEQ is output by logically combining the equalization signal BLEQ and the word line detection signal SWL_DET. The equalization combination signal BLEQB becomes a 'low' level when the word line detection signal SWL_DET and the equalization signal BLEQ are at a 'high' level, and when any one is at a 'low' level. Becomes a 'high' level. The delay signal BLEQD is a signal obtained by delaying the equalization combined signal BLEQB by a predetermined value. The equalization compensation signal BLEQ_C transitions to a low level when the equalization compensation signal BLEQB transitions to a high level, and when the delay signal BLEQD transitions to a low level. , Is a signal to transition to the 'high' level.

Accordingly, in the equalization correction circuit of the semiconductor memory device according to the present invention, when the equalization compensation signal BLEQ_C is disabled at the 'low' level, the word line SWL is enabled at the 'high' level. After the word line SWL is disabled at the 'low' level, the equalization compensation signal BLA_C is enabled at the 'high' level. That is, the equalization correction circuit of the semiconductor memory device senses the level of the word line voltage SWL_V and secures a margin equal to a predetermined value delay, so that the equalization time of the bit lines BL and BLB is set to the word line SWL. By operating after this is completely closed, the data of the cell can be prevented from being bad.

7 is a driving circuit diagram of a semiconductor memory device to which an equalization correction circuit according to an embodiment of the present invention is applied.

Referring to FIG. 7, the semiconductor memory device may charge-share the memory cell 20 selected when the word line SWL is enabled and the cell information when the memory cell 20 is selected. The timing of equalizing the bit lines BL and BLB according to the level of the sense amplifier 30 loaded on the BLB and amplifying the data of the bit lines BL and BLB and the word line SWL. Equalizer 40 to equalize by adjusting the.

The equalizer 40 compares the level of the reference voltage Vref with the level of the word line SWL to generate a detection signal SWL_DET, and responds to the detection signal SWL_DET. An equalization signal controller 200 which outputs an equalization compensation signal BLEQ_C by delaying the enable timing of the equalization signal BLEQ, and an equalization execution unit that receives and equalizes the equalization compensation signal BLEQ_C. (10).

When the word line SWL is enabled, the memory cell 20 is selected, and information stored in the memory cell 20 is charged shared to be loaded on the bit lines BL and BLB. At this time, the sense amplifier 30 is driven to amplify the data of the bit lines BL and BLB. Subsequently, when the word line SWL is disabled, the memory cell 20 is closed. However, the slope of the word line SWL becomes smooth due to the resistance value or loading of the word line SWL before the cell 20 is closed, so that the equalization signal before the word line SWL is closed. BLEQ) may be enabled. Therefore, when the word line SWL is disabled to solve the above problem, the word line detector 100 compares the reference voltage Vref with the word line voltage SWL_V to detect the detected word line SWL. Generate the signal SWL_DET. When the reference voltage Vref is higher than the word line voltage SWL_V, the sensing signal SWL_DET is enabled, and when the reference voltage Vref is lower than the word line voltage SWL_V, the detection signal. Disable The sensing signal SWL_DET is input to the equalized signal controller 200. The equalization signal controller 200 disables the equalization compensation signal BLEQ when the detection signal SWL_DET or the equalization signal BLEQ is disabled, and the detection signal SWL_DET and the equalization signal ( BLEQ is enabled, and the equalization compensation signal BLEQ_C is delayed for a predetermined time to be enabled. The equalization execution unit 10 receives the equalization compensation signal BLEQ_C and equalizes the bit lines BL and BLB.

Therefore, in the semiconductor memory device, the word line SWL is enabled, the cell information of the memory cell 20 is loaded on the bit lines BL and BLB and amplified by the sense amplifier 30, and then the word line SWL is used. ) Is disabled, it is possible to implement a more reliable semiconductor memory device by correcting the timing of equalizing by detecting the potential level of the word line (SWL).

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all respects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a circuit diagram for driving a semiconductor memory device according to the prior art;

2 is a driving timing diagram of a semiconductor memory device according to the related art;

3 is a block diagram of an equalization correction circuit of a semiconductor memory device according to the present invention;

4 is a circuit diagram of a word line detector of FIG. 3;

5 is a circuit diagram of an equalization signal controller shown in FIG. 3, and

6 is a timing diagram of an equalization correction circuit of the semiconductor memory device according to the present invention.

<Explanation of symbols for main parts of the drawings>

10: equalization execution unit 20: memory cell

30: sense amplifier 40: equalizing unit

100: word line detector 200: equalized signal controller

Claims (10)

A word line detector for detecting a level of the word line and generating a detection signal; And an equalization signal controller configured to output an equalization compensation signal by correcting a timing of the equalization signal in response to the sensed signal. The method of claim 1, The word line detector, And detecting a reference voltage and a level of the word line and outputting a sensed signal. The method of claim 2, The equalized signal controller, When any one of the detection signal or the equalization signal is disabled, the equalization compensation signal is disabled, And when the sensing signal and the equalizing signal are enabled, enabling the equalization compensation signal. The method of claim 3, wherein The equalized signal controller, And outputting the equalization compensation signal which is enabled after a predetermined time delay from the enable timing of the detection signal when the detection signal and the equalization signal are enabled. The method of claim 4, wherein The equalized signal controller, A signal combination unit configured to receive the detected signal and the equalized signal and generate an equalized combination signal; And an output unit configured to receive a delay signal having a predetermined time delay and output the equalization compensation signal. A memory cell selected at word line enable, A bit line pair connected to the memory cell, A sense amplifier for amplifying the data of the bit line pair, and And an equalizer unit for adjusting timing of equalizing the pair of bit lines according to the level of the word line. The method of claim 6, The equalizer part, And equalizing the equalized signal by a predetermined time delay when the word line is disabled. The method of claim 7, wherein The equalizer part, A word line detector for outputting a detection signal by comparing the reference voltage with a level of the word line; An equalization signal controller for outputting an equalization compensation signal by delaying the equalization signal by the predetermined time in response to the detection signal; And an equalization execution unit configured to receive the equalization compensation signal and equalize the bit line pair. The method of claim 8, The word line detector, If the reference voltage is higher than the word line voltage, enable the detection signal, And disabling the sensing signal when the reference voltage is lower than the word line voltage. The method of claim 9, The equalized signal controller, And when the detection signal and the equalization signal are enabled, output the equalization compensation signal that is enabled after a predetermined time delay from the timing at which the detection signal is enabled.

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