KR101163045B1 - Word-line Driving Circuit and a Method thereof - Google Patents

Abstract

The word line driver circuit of the present invention is characterized in that the word line is deactivated for a predetermined time in the sense amplification section of the bit line sense amplifier.

Description

Word-line driving circuit and method

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a word line driving circuit.

1 is a schematic circuit diagram of a general bit line sense amplifier.

The bit line sense amplifier 1 is connected to the bit line BL and the bit bar line BLB. Before the word line WL is activated, the bit line BL and the bit bar line BLB are precharged with a precharge voltage. When the precharge operation is stopped and the word line WL is activated, charge sharing occurs between the storage capacitor C and the bit line BL. When charge sharing occurs, the voltage of the bit line BL increases or decreases according to the amount of charge stored in the storage capacitor C. Thereafter, when the bit line sense amplifier 1 is activated, the bit line sense amplifier 1 amplifies the voltage difference between the bit line BL and the bit bar line BLB to divide the bit line BL and the bit bar line BLB. Change to high and low levels or low and high levels. The bit line sense amplifier 1 is activated so that the bit line sense amplifier 1 amplifies the bit line BL and the bit bar line BLB to a high and low level or a low level and a high level. The change to is referred to as sensing amplification, and the bit line sense amplifier 1 sets the bit line BL and the bit bar line BLB high and low from the time when the bit line sense amplifier 1 is activated. ) Or the point of changing to a low level and a high level is called a sensing amplification period.

As shown in FIG. 1, the bit line sense amplifier 1 is connected to a bit line BL and a bit bar line BLB. The voltage level of the bit line BL and the bit bar line BLB is the same level as the precharge voltage, and the voltage levels are slightly different after the charge sharing, and the bit line sense amplifier 1 Detect and amplify voltage levels. Therefore, in order to normally sense and amplify this minute difference voltage level, the impedance on the bit line BL side and the impedance on the bit bar line BLB side viewed from the bit line sense amplifier 1 should be designed to be the same. However, when the bit line sense amplifier 1 is activated after charge sharing, the impedances of the bit line BL side and the bit bar line BLB side are different from each other. Comparing the capacitance values of both sides, the capacitance value of the bit bar line (BLB) is the line capacitance value (BL capacitance, Cb) of the bit bar line (BLB), whereas the capacitance value of the bit line (BL) side is It is the sum Cb + Cs of the cell capacitance value Cs of the storage capacitor C which is seen as the line capacitance value BL capacitance Cb of the bit line BL and the word line WL are activated. That is, the capacitance value of the bit line BL side is Ctotal_bl = Cb + Cs, and the capacitance value of the bit bar line BLB side is Ctotal_blb = Cb. Accordingly, both impedances compared by the bit line sense amplifier 1 are mismatched by Cs. This mismatch lowers the sensing sensitivity of the bit line sense amplifier 1 and reduces the sensing margin such as causing an offset of the bit line sense amplifier 1. For example, when the lowest comparison voltages delta V and ΔV of the bit line sense amplifier 1 are 200 mV, the offset voltage according to the mismatched capacitance value Cs mentioned above is about 30 mV. Since the lowest comparison voltage ΔV of the bit line sense amplifier 1 is a very important factor in determining the sensing sensitivity, the offset voltage generated according to the mismatched capacitance value Cs is a malfunction of the bit line sense amplifier 1. May cause. As the semiconductor memory device becomes smaller, the ratio of impedance mismatches (Cb + Cs: Cb) between both ends of the bit line sense amplifier 1 is increasing, and as the semiconductor memory device becomes lower power, the lowest comparison of the bit line sense amplifier 1 is achieved. Since the magnitude of the voltage DELTA V decreases, the sensing margin of the bit line sense amplifier 1 decreases due to impedance mismatch.

2 is a circuit diagram of a word line driving circuit according to the prior art. The word line driver circuit shown in FIG. 2 includes an inverter IV, a first PMOS transistor P1, a first NMOS transistor N1, and a second NMOS transistor N2. In the word line driving circuit shown in FIG. 2, the sub word line activation signal is activated through the first PMOS transistor P1 which is activated when the main word line selection signal MWLB is activated and the sub word line selection signal FXB is activated. When the main word line select signal MWLB is deactivated or the sub word line select signal FXB is deactivated, one of the first NMOS transistor N1 and the second NMOS transistor N2 is generated. In this manner, the sub word line activation signal SWL is inactivated and generated. The activation of the sub word line activation signal SWL and the amplification of the bit line sense amplifier according to the signals FXB and MWLB applied to the word line driving circuit shown in FIG. 2 will be described with reference to the waveform diagram of FIG. 4A.

SUMMARY OF THE INVENTION The present invention has a technical problem to provide a word line driving circuit for allowing a bit line sense amplifier to have a high sensing margin.

The word line driver circuit according to an embodiment of the present invention deactivates the word line for a predetermined time in the sense amplification section of the bit line sense amplifier.

In addition, the word line driving circuit according to an embodiment of the present invention includes a waveform determination signal generator and a main word line selection signal, a waveform adjustment signal, and a sub word line that generate a waveform adjustment signal in response to the sub word line selection signal and the adjustment signal. And a sub word line active signal generator configured to generate a sub word line active signal in response to a selection signal, wherein the waveform control signal is deactivated for a predetermined time in the sense amplification section of the bit line sense amplifier.

In addition, the word line driving method according to an embodiment of the present invention includes the steps of activating a word line in response to an active command, deactivating the word line for a predetermined period, and activating the word line until a precharge command is input. Include.

The present invention creates an effect of improving the sensing margin by compensating for impedance mismatches at both ends of the bit line sense amplifier.

In addition, according to the present invention, the unit mat size increases, thereby creating an effect of reducing a required area of the semiconductor memory device.

In addition, the present invention reduces the overall sensing time of the bit line sense amplifier to create an effect that allows the semiconductor memory device to operate at high speed.

1 is a schematic circuit diagram of a general bit line sense amplifier;
2 is a circuit diagram of a word line driving circuit according to the prior art;
3 is a circuit diagram of a word line driving circuit according to an embodiment of the present invention;
4A is a waveform diagram of signals input and output to a word line driver circuit according to the related art shown in FIG.
FIG. 4B is a waveform diagram of signals input and output to a word line driver circuit according to an embodiment of the present invention shown in FIG. 3.

In the word line driving circuit according to an embodiment of the present invention, after the charge sharing for the bit line BL, the bit line sense amplifier is activated to sense the bit line BL and the bit bar line BLB. By deactivating the word line for a predetermined time period during the amplification, the bit line BL side impedance and the bit bar line BLB side impedance seen in the bit line sense amplifier may be kept the same. Accordingly, the sensing sensitivity of the bit line sense amplifier may be prevented from falling due to impedance mismatch. In the deactivation period of the word line, since the connection between the bit line BL and the storage capacitor C is cut off, the capacitance value of the bit line BL side becomes Cb and thus the side of the bit bar line BLB side. It is equal to the capacitance value, Cb. The time at which the word line is deactivated is determined in consideration of the sensing sensitivity of the bit line sense amplifier and the difference between the bit line BL side impedance and the bit bar line BLB side impedance seen in the bit line sense amplifier. desirable. In particular, the bit line sense amplifier senses that the voltage difference between the bit line BL and the bit bar line BLB is greater than the minimum comparison voltage ΔV, and the bit line BL and the bit bar line It is preferable to deactivate the word line in the period where the BLB) starts to be sensed and amplified, to prevent the sensing sensitivity of the bit line sense amplifier from falling. After the bit line BL and the bit bar line BLB are sufficiently amplified by the bit line sense amplifier, the word line is activated, and thus an influence on the operation of the bit line sense amplifier occurs even if an impedance mismatch occurs again. Because this is not big.

3 is a circuit diagram of a word line driver circuit according to an embodiment of the present invention.

The word line driver circuit includes a waveform determination signal generator 100 and a sub wordline signal generator 200.

The waveform determination signal generator 100 generates a waveform determination signal FX1 in response to the sub word line selection signal FXB and the adjustment signal CTRL. The sub word line selection signal FXB is a signal output from a PIX driver of a semiconductor memory device and is a signal for selecting and activating a specific sub word line.

The sub wordline signal generator 200 may respond to the main wordline selection signal MWLB, the subwordline selection signal FXB, and the waveform determination signal FX1 in response to the subwordline activation signal SWL. Create

The word line driving circuit illustrated in FIG. 3 is an example in which the sub word line activation signal SWL is deactivated for a predetermined time in the sense amplification section of the bit line sense amplifier by adjusting the waveform determination signal FX1.

As mentioned above, since the word line driving circuit shown in FIG. 3 adjusts the waveform of the sub word line activation signal SWL by adjusting the waveform determination signal FX1, the sub word line signal generator 200 ) May be configured identically to the corresponding part of the word line driving circuit according to the prior art shown in FIG. The sub word line signal generator 200 may include a first PMOS transistor P1 and first and second NMOS transistors N1 and N2 as shown in FIG. 2. The first PMOS transistor P1 is connected in series with the first NMOS transistor N1 and is connected between the output terminal and the ground terminal of the waveform determination signal FX1. The first PMOS transistor P1 and the first NMOS transistor N1 receive the main word line selection signal MWLB in common. The second NMOS transistor N2 is connected between the first node n1, which is a node to which the first PMOS transistor P1 and the first NMOS transistor N1 are connected, and a ground terminal, so as to be connected to the sub word line. The selection signal FXB is input. The sub word line signal generator 200 outputs the sub word line activation signal SWL through the first node n1. The main word line selection signal MWLB is a signal output from an address decoder of a semiconductor memory device and is a signal for activating a specific main word line.

The sub word line signal generator 200 may activate the first word line when the main word line selection signal MWLB is activated as a low level and the waveform determination signal FX1 is activated as a high level. The MOS transistor P1 is turned on to perform a charge operation from the output terminal of the waveform determination signal FX1 to the first node n1 through the first PMOS transistor P1. Accordingly, the first node n1 rises to a high level, and the sub word line activation signal SWL is activated to a high level and output. In this case, the first NMOS transistor N1 is turned off by receiving the main word line selection signal MWLB having a low level and the second NMOS transistor N2 is activated at a low level. The sub word line selection signal FXB is turned on and turned off.

In addition, when the main word line selection signal MWLB is activated at a low level and the waveform determination signal FX1 is deactivated at a low level, the sub word line signal generator 200 may activate the first PMOS transistor P1. Is turned on to perform a discharge operation from the first node n1 to the output terminal of the waveform determination signal FX1 through the first PMOS transistor P1. Accordingly, the first node n1 drops to a low level and the sub word line activation signal SWL is deactivated to a low level and output. In this case, the first NMOS transistor N1 is turned off by receiving the main word line selection signal MWLB having a low level and the second NMOS transistor N2 is activated at a low level. The sub word line selection signal FXB is turned on and turned off.

In addition, when the main word line selection signal MWLB is inactivated as a high level, the sub word line signal generator 200 may turn off the first PMOS transistor P1 and the first NMOS transistor N1. Is turned on to perform a discharge operation from the first node n1 to the ground terminal via the first NMOS transistor N1. Accordingly, the first node n1 drops to a low level and the sub word line activation signal SWL is deactivated to a low level and output.

In summary, when the main word line selection signal MWLB is activated, the sub word line signal generator 200 activates the sub word line activation signal SWL according to the waveform determination signal FX1. Or create it by deactivating it. That is, the word line driving circuit illustrated in FIG. 3 may adjust the sub word line activation signal SWL by adjusting the waveform determination signal FX1.

As mentioned above, in the word line driving circuit according to an embodiment of the present invention, the bit line sense amplifier is activated to sense and amplify the bit line BL and the bit bar line BLB. Deactivate the word line for a predetermined time. The word line driver circuit may deactivate the word line in the sense amplification period of the bit line sense amplifier by adjusting the waveform determination signal FX1 through the waveform determination signal generator 100. As illustrated in FIG. 3, the waveform determination signal generator 100 receives the sub word line selection signal FXB and the adjustment signal CTRL to generate a NOR gate NR for generating a waveform determination signal FX1. It can be configured to include. By using the signal activated in the sense amplification section of the bit line sense amplifier as the control signal CTRL, the waveform determination signal generator 100 uses the waveform determination signal FX1 as the sub word line selection signal FXB. ) May be deactivated in the sense amplification section of the bit line sense amplifier and activated in the remaining section. As mentioned above, the control signal CTRL may preferably use a signal activated in the sense amplification period of the bit line sense amplifier. Since the overdrive signal (see FIGS. 4A and 4B) is a signal activated in the sense amplification section of the bit line sense amplifier, the overdrive signal is suitable to be used as the control signal CTRL. The overdrive signal is a signal that controls the overdrive operation used to increase the initial sense amplification speed of the bit line sense amplifier in the semiconductor memory device. The overdrive operation is to increase the initial sense amplification speed of the bit line sense amplifier by temporarily amplifying a pair of bit lines amplified to a core voltage level (Vcore) to a power supply voltage (VDD) level higher than the core voltage.

FIG. 4A is a waveform diagram of signals input and output to the wordline driver circuit according to the related art shown in FIG. 2, and FIG. 4B is input and output to the wordline driver circuit according to an embodiment of the present invention shown in FIG. 3. A waveform diagram of the signals.

In the semiconductor memory device including the word line driver circuit according to the related art, when the active command ACT is input, the precharge operation on the bit line BL and the bit bar line BLB is terminated. The sub word line activation signal SWL is activated as the main word line selection signal MWLB and the sub word line selection signal FXB generated by the active command ACT are simultaneously activated. Accordingly, the word line driving circuit according to the related art shown in FIG. 2 activates the sub word line activation signal SWL. When the word line activation signal SWL is activated, the bit line BL is changed in voltage level through charge sharing a. 4A illustrates that the bit line BL increases in voltage through charge sharing a. After the charge sharing (a) is finished, the sense amplifier enable signal SAN is activated. The sense amplifier enable signal SAN is a signal that manages to activate the bit line sense amplifier. When the sense amplifier enable signal SAN is activated, the bit line sense amplifier is activated to amplify the voltages of the bit line BL and the bit bar line BLB (b). The overdrive signal ovd is activated at the beginning of the period in which the sense amplifier enable signal SAN is activated. As the overdrive signal ovd is activated, the bit line sense amplifier accelerates the sense amplification operation. Thereafter, the main word line selection signal MWLB and the sub word line selection signal FXB are deactivated. Accordingly, the sub word line activation signal SWL is inactivated to deactivate the word line. When the sense amplifier enable signal SAN is deactivated, an amplification operation for the bit line BL and the bit bar line BLB is ended, and the bit line BL and the bit are precharged by a precharge command PCG. A precharge operation on the BLB is performed. FIG. 4A shows that the sub word line activation signal SWL is activated in the sense amplification section b of the bit line sense amplifier. As described above, in the period in which the word line activation signal SWL is activated, the bit line BL side impedance and the bit bar line BLB side impedance seen by the bit line sense amplifier are mismatched, thereby causing the bit line sense. The amplifier may malfunction. In particular, since the voltage difference between the bit line BL and the bit bar line BLB is not large in the sense amplification period b of the bit line sense amplifier, the impedance in the sense amplification period b of the bit line sense amplifier is not large. The adverse effect of mismatching is relatively larger than the adverse effect after the sensing amplification section (b).

Referring to FIG. 4B, the waveform control signal FX1 generated from a combination of the sub word line selection signal FXB and the overdrive signal ovd, which is the control signal CTRL, is illustrated. When the active command ACT is input, the precharge operation on the bit line BL and the bit bar line BLB is terminated. In addition, the main word line selection signal MWLB and the sub word line selection signal FXB generated by the active command ACT are simultaneously activated. In addition, the waveform determination signal generator 100 generates the waveform adjustment signal FX1. Accordingly, as shown in FIG. 4, the sub word line activation signal SWL is activated by the sub word line selection signal FXB and the waveform control signal FX1. When the word line activation signal SWL is activated, the voltage level of the bit line BL is changed through charge sharing c. 4B illustrates that the bit line BL increases in voltage through the charge sharing c as shown in FIG. 4A. After the charge sharing c is completed, the sense amplifier enable signal SAN is activated. The overdrive signal ovd is also activated. In this section, the sub word line activation signal SWL is inactivated by the waveform control signal FX1 in a predetermined section. The bit line sense amplifier is activated to amplify the voltages of the bit line BL and the bit bar line BLB (d). As the overdrive signal ovd is activated, the bit line sense amplifier accelerates the sense amplification operation. Subsequently, when the overdrive signal ovd is deactivated, the sub word line activation signal SWL is activated again by the waveform control signal FX1. The sub word line activation signal SWL remains activated until the main word line selection signal MWLB and the sub word line selection signal FXB are inactivated to deactivate the waveform control signal FX1. When the main word line activation signal SWL is deactivated, the sense amplifier enable signal SAN is subsequently deactivated, and the amplification operation for the bit line BL and the bit bar line BLB is terminated. When the precharge command PCG is input, a precharge operation on the bit line BL and the bit bar line BLB is performed. FIG. 4B shows that the sub word line activation signal SWL is inactivated in the sense amplification period d of the bit line sense amplifier. Accordingly, in the sense amplification period d of the bit line sense amplifier, the bit line BL side impedance and the bit bar line BLB side impedance seen in the bit line sense amplifier match each other.

The word line driving circuit according to an embodiment of the present invention temporarily improves the sensing margin in the sense amplification section of the bit line sense amplifier by temporarily supplementing impedance mismatches at both ends of the bit line sense amplifier. To create an effect. When the sensing margin is improved, the lowest comparison voltage ΔV can be lowered compared to the prior art, and thus, Cb, which is a capacitance value determined by the length of the bit line BL and the bit bar line BLB, can be reduced. Since the margin may be larger, the length of the bit line BL and the bit bar line BLB may be longer. As the length of the bit line BL and the bit bar line BLB becomes longer, a unit mat size increases, which is an advantage in reducing the area of a semiconductor memory device.

In addition, the word line driving circuit according to an embodiment of the present invention can reduce the overall sensing time of the bit line sense amplifier through an improved sensing margin, which is an advantage in high speed operation of a semiconductor memory device.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1: bit line sense amplifier 100: waveform determination signal generator
200: sub word line active signal generator

Claims (14)

delete delete delete delete A waveform determination signal generator configured to generate a waveform adjustment signal in response to the sub word line selection signal and the adjustment signal; And
A sub word line activation signal generator configured to generate a sub word line activation signal in response to the main word line selection signal, the waveform control signal, and the sub word line selection signal,
The waveform control signal is a word line driver circuit, characterized in that for a predetermined time in the sense amplification period of the bit line sense amplifier. Claim 6 was abandoned when the registration fee was paid. The method of claim 5, wherein
And said control signal is an overdrive signal. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 5, wherein
And the sub word line activation signal generation unit activates and generates the sub word line activation signal according to the waveform control signal when the main word line selection signal is activated. Claim 8 was abandoned when the registration fee was paid. The method of claim 7, wherein
And the sub word line activation signal generator is configured to deactivate the sub word line activation signal according to the sub word line selection signal. delete delete delete delete delete delete

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