KR100862995B1 - Circuit of Generating Column Selection Signal for Semiconductor Memory Apparatus - Google Patents

Abstract

The present invention provides a first column selection signal generator for generating and outputting a first column selection signal having a first width according to a read signal, and a second column selection signal having a second width according to a write signal. And a column select signal output unit configured to output a third column select signal combining the first column select signal and the second column select signal.

Column select signal, read, write, column address strobe

Description

Circuit of Generating Column Selection Signal for Semiconductor Memory Apparatus

1 is a block diagram of a general semiconductor memory device;

2 is a block diagram of a column selection signal generation circuit according to the prior art;

3 is a waveform diagram of a column selection signal according to a read operation and a write operation;

4 is a block diagram of a column select signal generation circuit of a semiconductor memory device according to the present invention;

5 is a circuit diagram of a column select signal generation circuit of a semiconductor memory device according to the present invention;

6 is a circuit diagram of a first control unit of FIG. 5;

FIG. 7 is a circuit diagram of the second controller of FIG. 5.

<Description of Symbols for Main Parts of Drawings>

200: first column selection signal generator 210: first latch

220: first determination unit 230: first delay unit

240: first control unit 250: second delay unit

260: second control unit 300: second column selection signal generation unit

310: second latch 320: second determination unit

330: third delay unit 340: third control unit

350: fourth delay unit 360: fourth control unit

400: column selection signal output unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a column select signal generation circuit of a semiconductor memory device.

In a typical semiconductor memory device, as illustrated in FIG. 1, a bit line BLT and BLB and a word line WL are formed in a matrix form and are connected to the bit line BLT and BLB and the word line WL. And a bit line sense amplifier (BLSA) 20 for sensing and amplifying data of the cell core 10 formed with cells and capacitors, the bit lines BLT and BLB, and the input / output signal lines IOT and IOB. ), Switching transistors M1 and M2 for connecting the bit lines BLT and BLB to the bit line sense amplifier 20, and data transmitted through a data input / output bus IO from outside a semiconductor memory device. Write data (WDRV) 30 for transmitting to the bit line sense amplifier 20 through lines IOT and IOB, and data output from the cell core 10 through the bit line sense amplifier 20. IO sense for transferring to the data input / output bus (IO) Profile is provided with a (IOSA) (40) or the like.

The semiconductor memory device configured as described above activates a column select signal YS to write data input from the outside of the semiconductor memory device to the cell core 10 or to read data written to the cell core 10. The operation of turning on (M1, M2) must be inevitable.

In the semiconductor memory device according to the related art, as shown in FIG. 2, a column select signal generation circuit 100 is provided.

The column selection signal generation circuit 100 according to the related art has a column selection signal having a predetermined pulse width when any one of the read signal IRDP, the write signal IWTP, and the column address strobe signal ICASP is activated. Produces YS.

The pulse width of the column selection signal YS generated by the column selection signal generation circuit 100 according to the related art is correlated with the read signal IRDP, the write signal IWTP, and the column address strobe signal ICASP. It is constant without.

The read signal IRDP is a read signal generated inside the semiconductor memory device according to a read command outside the semiconductor memory device.

The write signal IWTP is a write signal generated inside the semiconductor memory device according to a write command outside the semiconductor memory device.

The column address strobe signal ICASP is a signal generated with a predetermined time difference from the read signal IRDP and the write signal IWTP so that an additional data read or write operation according to a burst length BL is performed. .

Referring to FIG. 3, each signal waveform including a column selection signal during read and write operations in a semiconductor memory device will be described.

In the case of the read operation, since the wiring load of the signal transmitted to the input / output signal lines IOT and IOB is greater than the data signal sensed and amplified by the bit line sense amplifier 20 of FIG. Small amount To increase the amount of this signal, the pulse width of the column select signal YS must be increased. However, if the pulse width of the column select signal YS is increased too much, the IAS sense amplifier 40 needs to be enabled after the column select signal YS is disabled. Can be. Therefore, in the read operation, the pulse width of the column selection signal YS should be determined to match the sensing capability of the IO sense amplifier 40.

On the other hand, in the case of the write operation, since the driving capability of the write driver 30 is basically larger than the sensing capability of the IO sense amplifier 40, the pulse width of the column selection signal YS can be shorter than the read operation. have. A difference occurs in the time required for data to be stored in the cell according to the driving capability of the write driver 30. When the driving capability is low, it is preferable to widen the pulse width of the column select signal YS, but the increase in the pulse width is limited due to the precharge signal IOPCG enabled after the column select signal YS is disabled. The precharge signal IOPCG is a signal for performing a precharge operation to make the voltage levels of the input / output signal lines IOT and IOB the same. If the precharge operation is not performed correctly, an error may occur during the next read operation. . Therefore, the pulse width of the column selection signal YS during the write operation should be determined according to the driving capability of the write driver 30.

However, since the column selection signal generation circuit of the semiconductor memory device according to the related art generates a column selection signal having the same pulse width without distinguishing read / write operations, there is a problem of degrading read or write operation performance.

SUMMARY OF THE INVENTION An object of the present invention is to provide a column selection signal generation circuit of a semiconductor memory device capable of preventing performance degradation of a read or write operation of the semiconductor memory device.

In an embodiment, a column selection signal generation circuit of a semiconductor memory device may include a first column selection signal generation unit configured to generate and output a first column selection signal having a first width according to a read signal; A second column selection signal generator configured to generate and output a second column selection signal having a second width according to the write signal; And a column select signal output unit configured to output a third column select signal combining the first column select signal and the second column select signal.

The column selection signal generation circuit of the semiconductor memory device according to the present invention generates and outputs a first column selection signal having a first width according to a read signal, a column address strobe signal, and an operation mode determination signal. ; A second column selection signal generation unit configured to generate and output a second column selection signal having a second width according to the write signal, the column address strobe signal, and the operation mode determination signal; And a column select signal output unit configured to output a third column select signal generated by combining the first column select signal and the second column select signal.

Hereinafter, a preferred embodiment of a column selection signal generation circuit of a semiconductor memory device according to the present invention will be described with reference to the accompanying drawings.

As shown in FIG. 4, the column selection signal generation circuit of the semiconductor memory device according to the present invention has a first width according to the read signal IRDP, the column address strobe signal ICASP, and the operation mode determination signal IWTS. A second width according to the first column selection signal generator 200 for generating and outputting the first column selection signal YS_R, the write signal IWTP, the column address strobe signal ICASP, and the operation mode determination signal IWTS. A second column selection signal generation unit 300 which generates and outputs a second column selection signal YS_W having a predetermined value and a combination of the first column selection signal YS_R and the second column selection signal YS_W And a column select signal output unit 400 for outputting a third column select signal YS.

As shown in FIG. 5, the first column selection signal generator 200 may generate the first column selection signal according to the read signal IRDP, the column address strobe signal ICASP, and the operation mode determination signal IWTS. A first determination unit 220 for outputting a first determination signal for determining whether to generate YS_R, a first latch 210 for generating the first column selection signal YS_R according to the first determination signal, A first delay unit 230 and a first test mode signal TM1 configured to determine an enable timing of the first column select signal YS_R by delaying and outputting the first column select signal YS_R for a first delay time; <0: N>) or the first control unit 240 for varying the first delay time according to at least one of the fuse set signal, and after the second delay time from the timing of generation of the first column selection signal YS_R. The first column selection signal YS_R by resetting the first latch 210. The second delay unit 250 is configured to vary the second delay time according to at least one of the second delay unit 250 and the second test mode signal TM2 <0: N> or the fuse set signal such that the pulse width becomes the first width. The second control unit 260 is provided.

The first determination unit 220 may include an inverter IV21 receiving the operation mode determination signal IWTS, an AND gate AND21 receiving an output of the inverter IV21 and the column address strobe signal ICASP, And a NOR gate NR21 that receives the read signal IRDP and the output of the AND gate AND21.

The first latch 210 is an SR latch and includes a set terminal (/ S), a reset terminal (/ R), an output terminal (Q), and an inverted output terminal (/ Q). When the input signal level of the set terminal / S is low, the first latch 210 becomes high in the output signal level of the output terminal Q, and the input signal level of the reset terminal / R increases. When low, the output signal level of the output terminal Q becomes low.

The first delay unit 230 is a delay line configured by linking a plurality of delay elements, and the delay time of the input signal is increased by adjusting the number of delay elements passed through the input signal according to the timing control signals DTC1 <0: N>. Is variable. The first delay unit 230 delays the output signal of the first latch 210 by a delay time corresponding to the timing control signal DTC1 <0: N>, thereby allowing the first column selection signal YS_R to be input. Adjust the timing of the enable.

As illustrated in FIG. 6, the first controller 240 may include a fuse set 241 for outputting a fuse set signal having a level corresponding to a connection state of the fuse, and the fuse set signal and the first test mode signal ( And a configuration including a logic circuit for outputting at least one of TM1 <0: N> by the number of bits of the first test mode signal TM1 <0: N> The fuse set 241 includes a power supply terminal VDD. The first transistor (M41) connected to the fuse (F41) connected to the gate, the reset signal (Reset) is input to the gate, the source is connected to the power supply terminal (VDD), the source is the first transistor A second transistor M42 connected to the drain of M41 and a drain connected to a ground terminal, a series inverter IV41 to IV43 connected to an input node of the fuse F41 and the first transistor M41, and a gate; Is connected to the output terminal of the inverter IV41 and the source is the inverter ( And a latch transistor M43 connected to an input terminal of IV41 and a drain thereof connected to a ground terminal, wherein the logic circuit is configured to receive the fuse set signal and the first test mode signal TM1 <0: N>. And an inverter IV44 which receives the output of the NOR gate NR41 and outputs the timing control signals DTC1 <0: N>.

The second delay unit 250 is a delay line in which a plurality of delay elements are linked to each other, and the delay time of the input signal is adjusted by adjusting the number of delay elements via the input signal according to the pulse width control signal PWM1 <0: N>. Is variable. The basic configuration is the same as that of the first delay unit 230, and the number of delay elements or the basic delay time of the delay elements may be different. The second delay unit 250 delays the output signal of the inverted output terminal / Q of the first latch 210 by a delay time corresponding to the pulse width control signal PWM1 <0: N>. The pulse width of the first column selection signal YS_R is adjusted by inputting to the reset terminal / R of the first latch 210.

As illustrated in FIG. 7, the second control unit 260 outputs a fuse set 261 for outputting a fuse set signal having a level corresponding to a connection state of the fuse, and the fuse set signal and the second test mode signal ( And a configuration including a logic circuit for outputting at least one of TM2 <0: N> by the number of bits of the second test mode signal TM2 <0: N> The fuse set 261 includes a power supply terminal VDD. The first transistor M51 connected to the fuse F51 and the gate and the source connected to the fuse F51, the gate is connected to the power supply terminal VDD, and the source is connected to the first transistor. A second transistor M52 connected to a drain of M51 and a drain connected to a ground terminal, a series inverter IV51 to IV53 connected to an input node of the fuse F51 and the first transistor M51, and a gate; Is connected to the output terminal of the inverter IV51 and the source is the inverter I And a latch transistor M53 connected to an input terminal of V51 and a drain thereof connected to a ground terminal, wherein the logic circuit is configured to receive the fuse set signal and the second test mode signal TM2 <0: N>. And an inverter IV54 which receives the output of the NOR gate NR51 and outputs the pulse width control signal PWM1 <0: N>.

As shown in FIG. 5, the second column select signal generator 300 may generate the second column select signal according to the write signal IWTP, the column address strobe signal ICASP, and the operation mode determination signal IWTS. A second determination unit 320 for outputting a second determination signal for determining whether to generate YS_W, a second latch 310 for generating the second column selection signal YS_W according to the second determination signal, A third delay unit 330 and a third test mode signal TM3 configured to determine an enable timing of the second column select signal YS_W by delaying and outputting the second column select signal YS_W for a third delay time; <0: N> or the third control unit 340 for varying the third delay time according to at least one of the fuse set signal and the fourth delay time after the fourth delay time from the generation timing of the second column selection signal YS_W. The second column selection signal YS_ by resetting the second latch 310. According to at least one of the fourth delay unit 350 and the fourth test mode signal TM4 <0: N> or the fuse set signal such that the pulse width of W) becomes the second width, the fourth delay time may be adjusted. The fourth control unit 360 to be variable is provided.

The second determiner 320 receives an AND gate AND31 that receives the operation mode determination signal IWTS and the column address strobe signal ICASP, and the write signal IWTP and the AND gate AND31. A NOR gate NR31 for receiving an output is provided.

The second latch 310 may use the same configuration as the first latch 210.

The basic configuration of the third delay unit 330 is the same as the first delay unit 230, and the number of delay elements or the basic delay time of the delay elements may be different. The third delay unit 330 enables the second column selection signal YS_W by delaying the output signal of the second latch 310 by a delay time corresponding to the timing control signal DTC2 <0: N>. Adjust the timing.

The third controller 340 may have the same configuration as that of the first controller 240 illustrated in FIG. 6, as many as the number of bits of the third test mode signals TM3 <0: N>, and the third test. The timing control signal DTC2 <0: N> is output in accordance with the mode signal TM3 <0: N> or the fuse set signal.

The basic configuration of the fourth delay unit 350 is the same as the first delay unit 230, and the number of delay elements or the basic delay time of the delay elements may be different. The output signal of the inverted output terminal / Q of the second latch 310 is delayed by a delay time corresponding to the pulse width control signal PWM2 <0: N> to reset the terminal (/ R) of the second latch 310. ), The pulse width of the second column selection signal YS_W is adjusted.

The fourth controller 360 may have the same configuration as that of the second controller 260 illustrated in FIG. 7 as many bits as the fourth test mode signal TM4 <0: N>, and the fourth test mode. The pulse width control signal PWM2 <0: N> is output in accordance with the signal TM4 <0: N> or the fuse set signal.

The column select signal output unit 400 includes a logic circuit for ORing the first column select signal YS_R and the second column select signal YS_W, and the logic circuit includes the first column select signal YS_R. ) And the output of the NOA gate NR61 and the NOA gate NR61 receiving the second column selection signal YS_W and used for the third column selection signal YS, that is, the actual read or write operation. Inverter IV61 outputs a column select signal output to the column select signal generation circuit.

The read signal IRDP is a read signal generated inside the semiconductor memory device according to a read command outside the semiconductor memory device. The write signal IWTP is a write signal generated inside the semiconductor memory device according to a write command external to the semiconductor memory device. The column address strobe signal ICASP is a signal generated with a predetermined time difference from the read signal IRDP and the write signal IWTP so that an additional data read or write operation according to a burst length BL is performed. . The operation mode determination signal IWTS is a signal having different levels according to the write operation and the read operation of the semiconductor memory device. For example, the operation mode determination signal IWTS may be a high level during the write operation and a low level during the read operation.

Since the first test mode signal and the third test mode signal are signals that are used for the same purpose, that is, for enabling timing adjustment of the column selection signal, the first test mode signal and the third test mode signal may be identical to each other and may be identical. A separate signal can also be used.

Since the second test mode signal and the fourth test mode signal are also signals used for the same purpose, that is, the pulse width adjustment test of the column selection signal, only the names thereof may be different from each other, and may be the same signal. You can also use the signal of.

Hereinafter, an operation of the column selection signal generation circuit of the semiconductor memory device according to the present invention will be described.

First, in order to generate a column selection signal YS having an enable timing and a pulse width suitable for stable and accurate read and write operations, the first to fourth delay units 230 to 350 of FIG. 5 are generated. The task of adjusting the delay time should be preceded.

The operation of adjusting the delay times of the first to fourth delay units 230 to 350 of FIG. 5 may be performed by changing a delay time of the first to fourth delay units 230 to 350 through a test mode. And finding a suitable delay time at which the column selection signal YS having a pulse width is output, and then cutting the fuse of the fuse set inside the first to fourth controllers 240 to 360 accordingly.

The test mode is performed for each of the read operation and the write operation.

The test mode for the read operation is performed as follows.

First, the first test mode signal TM1 <0: N> and the second test mode signal TM2 <0: N> are input to the first control unit 240 and the second control unit 260, respectively, and the read signal Enable (IRDP). Since the read signal IRDP is enabled to perform a read operation, the operation mode determination signal IWTS is at a low level.

The first control unit 240 of FIG. 6 has a first test mode signal TM1 <0: N> since the fuse F41 is connected to the power supply terminal VDD and the fuse set signal output from the fuse set 241 is at a low level. ) Is output as the timing control signal DTC1 <0: N>. Meanwhile, in the normal operation, the bit corresponding to the cut fuse among the bits of the timing control signal DTC1 <0: N> is maintained at a high level according to the reset signal Reset generated during the initial operation of the semiconductor memory device. Replaces the first test mode signal TM1 <0: N> that is disabled at the time.

The second control unit 260 of FIG. 7 has a second test mode signal TM2 <0: N since the fuse F51 is connected to the power supply terminal VDD and the fuse set signal output from the fuse set 261 is at a low level. &Gt;) is output as the pulse width control signal (PWC1 <0: N>). Meanwhile, in the normal operation, the bit corresponding to the cut fuse among the bits of the pulse width control signal PWM1 <0: N> is maintained at a high level according to the reset signal Reset generated during the initial operation of the semiconductor memory device. In operation, replaces the disabled second test mode signals TM2 <0: N>.

The first determiner 220 inputs a low level signal to the set terminal / S of the first latch 210 according to the read signal IRDP enabled to the high level, so that the first latch 210 receives the first latch 210. Set the output signal of the output terminal Q at the high level.

The first delay unit 230 delays the output signal of the output terminal Q of the first latch 210 by a delay time corresponding to the timing control signal DTC1 <0: N>, so that the first column selection signal is delayed. Output as (YS_R).

The second delay unit 260 delays the output signal of the inverted output terminal / Q of the first latch 210 by a delay time corresponding to the pulse width control signal PWM1 <0: N>. 1 is input to the reset terminal (/ R) of the latch 210.

Since the output signal of the inverted output terminal / Q of the first latch 210 is at the low level, the output signal of the inverted output terminal / Q is input to the reset terminal / R through the second delay unit 250. In this case, the output signal of the output terminal Q of the first latch 210 is reset to a low level.

The section in which the output signal of the output terminal Q of the first latch 210 maintains the high level corresponds to the pulse width of the first column selection signal YS_R.

During the period in which the read signal IRDP is enabled, the write signal IWTP is in a disabled state, and the operation mode determination signal IWTS is at a low level so that the second column selection signal generator 300 operates. Therefore, the second column selection signal YS_W maintains a low level. Therefore, the third column selection signal YS output from the column selection signal output unit 400 is the same as the first column selection signal YS_R.

The read operation using the third column selection signal YS generated by changing the first test mode signal TM1 <0: N> and the second test mode signal TM2 <0: N> is monitored. The fuses inside the first control unit 240 and the second control unit 260 are cut by selecting the first test mode signal TM1 <0: N> and the second test mode signal TM2 <0: N>. As a result, the delay time setting operation of the first delay unit 230 and the second delay unit 260 is completed.

The test mode for the write operation is performed in the same manner as the test mode for the read operation. However, since the read signal IRDP is disabled, the write signal IWTP is enabled, and the write operation is performed, the operation mode determination signal IWTS is at a high level. Therefore, since the first column selection signal generator 200 does not operate, the first column selection signal YS_W maintains a low level.

In the above test mode, the first test mode signal TM1 <0: N> and the third test mode signal TM3 <0: N> have the same purpose, that is, for enabling timing adjustment of the column selection signal. The signals are used, and they are used at different times, so one of them can be used in common. Of course, if necessary, a separate signal may be used.

In addition, the second test mode signal TM2 <0: N> and the fourth test mode signal TM4 <0: N> may also be used for the same purpose, that is, a pulse width adjustment test of a column selection signal. They are used at different times, so one of them can be used in common. Of course, if necessary, a separate signal may be used.

In the meantime, the normal mode operation is performed instead of disabling the first to fourth test mode signals TM1 <0: N>, TM2 <0: N>, TM3 <0: N>, and TM4 <0: N>. The test mode is performed in the same manner as the test mode except that the delay time of the first to fourth delay units 230 to 350 is set according to the fuse set signal.

When the read signal IRDP is enabled according to the external read command or the column address strobe signal ICASP according to the read command is enabled, the first column select signal generator 200 operates to operate the first column select signal YS_R. ) Is generated and output as the third column selection signal YS through the column selection signal output unit 400.

When the write signal IWTP is enabled according to the external write command or the column address strobe signal ICASP is enabled according to the write command, the second column select signal generator 300 operates to operate the second column select signal YS_W. ) Is generated and output as the third column selection signal YS through the column selection signal output unit 400.

The column address strobe signal ICASP is simultaneously input to the first and second column select signal generators 200 and 300. However, since the operation mode determination signal IWTS has a different level at the read operation and the write operation, whether the column address strobe signal ICASP is generated according to the read operation or the write operation is determined. The column selection signal generators 200 and 300 determine and operate.

According to the present invention, when the read and write operations are possible using only the read signal IRDP and the write signal IWTP, or the column address strobe signal ICASP is not required regardless of the burst length BL, the following embodiments are described. It is also possible.

5, the set terminal (/) of the first latch 210 is removed by removing the first determiner 220 of the first column select signal generator 200 of FIG. 5 and inverting the read signal IRDP. S), the second determination unit 320 of the second column selection signal generator 300 is removed, and the write signal IWTP is inverted to be input to the set terminal / S of the second latch 310. The circuit may be configured.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The column selection signal generation circuit of the semiconductor memory device according to the present invention generates a column selection signal having a timing and a pulse width suitable for each of the read operation and the write operation, thereby making the read and write operations stable and accurate, thereby operating performance of the semiconductor memory device. There is an effect to improve.

Claims (21)

delete delete A first column selection signal generation unit which is enabled after a first delay time according to the read signal and generates and outputs a first column selection signal having a first width corresponding to the second delay time; A second column selection signal generation unit which is enabled after a third delay time according to the write signal and generates and outputs a second column selection signal having a second width corresponding to the fourth delay time; And A column select signal output unit configured to output a third column select signal combining the first column select signal and the second column select signal; The first column select signal generator A first latch generating the first column selection signal according to the read signal; A first delay unit configured to determine an enable timing of the first column select signal by delaying and outputting the first column select signal for the first delay time; A second delay unit configured to reset the first latch after the second delay time from the generation timing of the first column select signal so that the pulse width of the first column select signal becomes the first width; A first controller configured to vary the first delay time according to at least one of a first test mode signal and a fuse set signal, and A second controller configured to vary the second delay time according to at least one of a second test mode signal and a fuse set signal, And wherein the first to fourth delay times are independently variable. The method of claim 3, wherein The second column select signal generator A second latch generating the second column selection signal according to the write signal; A third delay unit configured to determine an enable timing of the second column select signal by delaying and outputting the second column select signal for the third delay time; and And a fourth delay unit configured to reset the second latch after the fourth delay time from the generation timing of the second column select signal so that the pulse width of the second column select signal becomes the second width. And a column select signal generation circuit of the semiconductor memory device. The method of claim 4, wherein The second column select signal generator A third controller configured to vary the third delay time according to at least one of the third test mode signal and the fuse set signal, and And a fourth controller configured to vary the fourth delay time according to at least one of a fourth test mode signal and a fuse set signal. delete delete delete A first column selection signal which is enabled after a first delay time according to a read signal, a column address strobe signal, and an operation mode determination signal, and generates and outputs a first column selection signal having a first width corresponding to the second delay time; Generation unit; A second column selection signal which is enabled after a third delay time according to the write signal, the column address strobe signal, and the operation mode determination signal, and generates and outputs a second column selection signal having a second width corresponding to the fourth delay time; Generation unit; And A column select signal output unit configured to output a third column select signal generated by combining the first column select signal and the second column select signal, The first column select signal generator A first determination unit outputting a first determination signal for determining whether to generate the first column selection signal according to the read signal, the column address strobe signal, and the operation mode determination signal; A first latch generating the first column selection signal according to the first determination signal; A first delay unit configured to determine an enable timing of the first column select signal by delaying and outputting the first column select signal for the first delay time; A second delay unit configured to reset the first latch after the second delay time from the generation timing of the first column select signal so that the pulse width of the first column select signal becomes the first width; A first controller configured to vary the first delay time according to at least one of a first test mode signal and a fuse set signal, and And a second controller configured to vary the second delay time according to at least one of a second test mode signal and a fuse set signal.  And wherein the first to fourth delay times are independently variable. The method of claim 9, The second column select signal generator A second determination unit outputting a second determination signal for determining whether to generate the second column selection signal according to the write signal, the column address strobe signal, and the operation mode determination signal; A second latch generating the second column selection signal according to the second determination signal; A third delay unit configured to determine an enable timing of the second column select signal by delaying and outputting the second column select signal for the third delay time; and And a fourth delay unit configured to reset the second latch after the fourth delay time from the generation timing of the second column select signal so that the pulse width of the second column select signal becomes the second width. And a column select signal generation circuit of the semiconductor memory device. The method of claim 10, The second determination unit A first logic element receiving the operation mode determination signal and the column address strobe signal; And a second logic element configured to receive the write signal and an output of the first logic element. The method of claim 10, The second column select signal generator A third controller configured to vary the third delay time according to at least one of a third test mode signal and a fuse set signal, and And a fourth controller configured to vary the fourth delay time according to at least one of a fourth test mode signal and a fuse set signal. The method of claim 5, wherein The column select signal output unit And a logic circuit for logically combining the first column selection signal and the second column selection signal. The method of claim 5, wherein And the first test mode signal and the third test mode signal are the same signal. The method of claim 3, wherein The first control unit A fuse set for outputting a fuse set signal of a level corresponding to the connection state of the fuse, and And a logic circuit for outputting at least one of the fuse set signal and the first test mode signal. The method of claim 15, The fuse set is A fuse connected to the power stage, A first switching element connected between the fuse and the ground terminal, An inverting element connected to a connection node of the fuse and the first switching element, and And a second switching element for maintaining the input signal level of the inverting element at a specific level. The method of claim 3, wherein And the second controller is configured in the same way as the first controller. The method of claim 5, wherein And the second test mode signal and the fourth test mode signal are the same signal. The method of claim 5, wherein The third control unit A fuse set for outputting a fuse set signal of a level corresponding to the connection state of the fuse, and And a logic circuit for outputting at least one of the fuse set signal and the third test mode signal. The method of claim 19, The fuse set is A fuse connected to the power stage, A first switching element connected between the fuse and the ground terminal, An inverting element connected to a connection node of the fuse and the first switching element, and And a second switching element for maintaining the input signal level of the inverting element at a specific level. The method of claim 5, wherein And the fourth control unit is configured in the same way as the third control unit.

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