KR100859838B1 - Semiconductor memory device having power-up signal generator - Google Patents

Abstract

A semiconductor memory device having a power-up signal generator is provided to prevent operation error not enabling a power-up signal due to a noise resulting from a long interconnection line. A global power-up signal generation unit(100) generates a global power-up signal in response to a certain level of external voltage, and drives the global power-up signal with external voltage or ground voltage in response to a test signal. A level conversion unit(200) outputs an internal power-up signal by changing or maintaining the level of the global power-up signal in response to the test signal. An internal block(300) performs initialization driving in response to the internal power-up signal. The global power-up signal generation unit is physically apart from the level conversion unit and the internal block.

Description

Semiconductor memory device having a power-up signal generating device {SEMICONDUCTOR MEMORY DEVICE HAVING POWER-UP SIGNAL GENERATOR}

1 is a block diagram of a power-up signal generating apparatus of a semiconductor memory device according to the prior art.

FIG. 2 is an operational waveform diagram of a power up signal generator of the prior art shown in FIG.

3 is a block diagram illustrating a semiconductor memory device including a power-up signal generation device according to an embodiment of the present invention.

4 is an internal circuit diagram of the global power-up signal generator of FIG. 3.

5 is an operation waveform diagram of the global power-up signal generator shown in FIG. 4.

6 is an internal circuit diagram of the level converter shown in FIG. 3;

* Explanation of symbols for the main parts of the drawings

100: global power-up signal generator

200: level conversion unit

300: internal block

400: local power-up signal generator

500: test signal generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly, to an apparatus for generating power up signals.

The semiconductor memory device performs a normal operation when the system is stabilized after applying power from the outside and initializing the memory. In order to ensure the stability and normal operation of the internal circuit, a high enough voltage is applied to the memory from the outside, and the internal circuit must operate when the internal circuit clearly recognizes the states of logic levels 'H' and 'L'. The power-up circuit can be seen as a circuit for controlling this operating point. Therefore, when the power-up signal PWRUP is activated, the memory goes through an initialization process and enters a normal operation mode.

1 is a block diagram of an apparatus for generating a power-up signal of a semiconductor memory device according to the prior art.

Referring to FIG. 1, a power up signal generating apparatus according to the related art includes a voltage divider 10 for dividing an external voltage VDD and outputting the split voltage, and a level detector for detecting a level of the divided voltage. 20 and a signal output unit 30 for generating a power-up signal PWRUP in response to the output signal DET of the level detector 20.

The voltage divider 10 includes resistors R1 and R2 connected in series between the supply terminal of the external voltage VDD and the supply terminal of the ground voltage, so that the voltage across the connection node a of the resistors R1 and R2 is applied. Outputs as the divider voltage.

The level sensing unit 20 has a ground voltage as a gate input, a PMOS transistor PM1 having a source-drain path between a supply terminal of the external voltage VDD and the node DET, and a distribution voltage as a gate input. The NMOS transistor NM1 having a drain-source path between the DET) and the supply terminal of the ground voltage and the voltage applied to the node DET are output as sense signals.

The signal output unit 30 includes first to third inverters I1, I2, and I3 connected in series to invert the sensing signal to output the power-up signal PWRUP.

FIG. 2 is an operation waveform diagram of the power up signal generating apparatus of the related art shown in FIG.

First, the voltage divider 10 divides the level of the external voltage VDD and outputs the divided voltage. During the initial driving of the semiconductor memory device, as the level of the external voltage VDD gradually increases, the level of the distribution voltage also gradually increases.

Subsequently, since the ground voltage is connected to the gate terminal of the PMOS transistor PM1 in the level sensing unit 20, as the level of the external voltage VDD increases in the PMOS transistor PM1, the gate-source voltage is greater than or equal to the threshold voltage. Ascends to turn on. Therefore, the node DET is driven to the external voltage VDD level by the turned-on PMOS transistor PM1.

Subsequently, when the level of the external voltage VDD rises above the logic determination level, the signal output unit 30 maintains the power-up signal PWRUP at the logic level 'L'.

Subsequently, the level of the divided voltage of the voltage divider 10 rises as the level of the external voltage VDD rises, and rises above the threshold voltage of the NMOS transistor NM1.

Next, the NMOS transistor NM1 is turned on by the distribution voltage to drive the node DET to the ground voltage VSS level. Accordingly, the signal output unit 30 inverts the voltage applied to the node DET to transition the power-up signal PWRUP to the logic level 'H'.

On the other hand, although not shown in the drawing, as the power-up signal PWRUP transitions to the logic level 'H', the semiconductor memory device drives initial power-up.

However, in order for the power-up signal to be delivered to the inner block, it has a substantially long line wiring. As such, due to the long wiring, noise may be applied to the power-up signal. In addition, the power-up signal is a signal rising along the level of the external voltage VDD, and the external voltage VDD is relatively vulnerable to noise.

Therefore, when using the power-up signal generating device according to the prior art, the noise is applied to the power-up signal due to the long wiring, it is determined that the power-up signal is not activated in the internal block using the actual problem is malfunctioning Occurs.

The present invention has been proposed to solve the above problems of the prior art, and has a semiconductor memory device having a power-up signal generation device that can prevent the malfunction of the power-up signal is not activated due to noise due to long wiring The purpose is to provide.

The semiconductor memory device according to an aspect of the present invention for achieving the above technical problem is to generate a global power-up signal in response to a predetermined level of the external voltage, and to drive it to an external voltage or ground voltage in response to the test signal Global power-up signal generating means; Level conversion means for converting or maintaining the level of the global power-up signal in response to the test signal and outputting the internal power-up signal; And an internal block configured to perform initialization driving in response to the internal power up signal.

According to another aspect of the present invention, a method of driving a semiconductor memory device may include driving a global power-up signal to an external voltage when the external voltage is below a predetermined level, and driving the global power-up signal to a ground voltage after the predetermined level or more. ; Inverting the global power-up signal to drive an internal power-up signal to the external voltage; And an internal block is initially powered up in response to the internal power up signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3 is a block diagram of a semiconductor memory device including a power-up signal generating device according to an embodiment of the present invention.

Referring to FIG. 3, the semiconductor memory device according to the present invention generates the global power-up signal GL_PWRUP in response to a predetermined level of the external voltage VDD, and in response to the test signals TM1 and TM2, the external voltage ( Internal power-up by converting or maintaining the level of the global power-up signal GL_PWRUP in response to the test signals TM1 and TM2 and the global power-up signal generation unit 100 for outputting to the VDD or the ground voltage VSS. A level converter 200 for outputting the signal INT_PWRUP, an internal block 300 for initializing driving in response to the internal power-up signal INT_PWRUP, and initialized in response to the local power-up signal LC_PWRUP. The test signal generator 500 for generating the signals TM1 and TM2 and the test signal generator 500 are disposed adjacent to the test signal generator 500 to generate the local power-up signal LC_PWRUP in response to a predetermined level of the external voltage VDD. The local power-up signal generator 400 for generating .

For reference, the global power-up signal generator 100 is physically remote from the level converter 200 and the internal block 300. Therefore, the physical wiring for transmitting the global power-up signal GL_PWRUP from the global power-up signal generator 100 to the level converter 200 is relatively longer than the wiring for transmitting other signals.

Therefore, the semiconductor memory device according to the present invention described above drives the level of the global power-up signal GL_PWRUP transmitted through a long wiring to the ground voltage VSS as needed, and before using it in the internal block 300, The inversion is driven to the external voltage VDD and applied to the internal block 300. At this time, since the ground voltage VSS is relatively stronger to noise than the external voltage VDD, even if the global power-up signal GL_PWRUP is transmitted through a long wiring, failure due to noise as in the past does not occur.

Meanwhile, the following describes the circuit diagram and driving of each internal block.

4 is an internal circuit diagram of the global power-up signal generator 100 of FIG. 3.

Referring to FIG. 4, the global power-up signal generator 100 divides the external voltage VDD into a voltage divider 120 for outputting a divided voltage, and senses positive and negative by sensing a level of the divided voltage. Signal output unit 140 for outputting signals C and D, and positive or negative detection signals C and D in response to the test signals TM1 and TM2 to be output as global power-up signals PWRUP. It has a selection unit 160 for.

The voltage divider 120 includes resistors R3 and R4 connected in series between the supply terminal of the external voltage VDD and the supply terminal of the ground voltage, so that the voltage across the connection node B of the resistors R3 and R4 is applied. Outputs as the divider voltage.

The signal output unit 140 includes a detection unit 142 for detecting the level of the external voltage VDD and an inversion delay for inverting and delaying the output signal of the detection unit 142 and outputting the positive detection signal C. The unit 144 and a delay unit 146 for delaying the output signal of the detector 142 and outputting the delayed signal as the sub-detection signal D are included.

The sensing unit 142 has a ground voltage VSS as a gate input, a PMOS transistor PM2 having a source-drain path between a supply terminal of the external voltage VDD and the node DET2, and a distribution voltage as a gate input. And an NMOS transistor NM2 having a drain-source path between the node DET2 and the supply terminal of the ground voltage, and a voltage applied to the node DET2.

The inversion delay unit 144 includes three inverters connected in series, and inverts and delays the output signal of the detection unit 142 to output the positive detection signal C.

The delay unit 146 includes two inverters connected in series and delays an output signal of the detection unit 142 to output the negative detection signal D.

The selector 160 outputs the transfer gate TG1 for outputting the positive sensing signal C as the global power-up signal PWRUP in response to the test signal TM1, and the sub-sensing signal D in response to the test signal TM2. And a transfer gate TG2 for outputting the global power-up signal PWRUP.

FIG. 5 is an operation waveform diagram of the global power-up signal generator shown in FIG. 4, and a brief description will be made of driving of the global power-up signal generator. In particular, the levels of the positive and negative sensing signals C and D according to the level variation of the external voltage VDD are shown.

First, the voltage divider 120 divides the level of the external voltage VDD and outputs the divided voltage. During the initial driving of the semiconductor memory device, as the level of the external voltage VDD gradually increases, the level of the distribution voltage also gradually increases.

Subsequently, since the ground voltage is connected to the gate terminal of the PMOS transistor PM2 in the sensing unit 142, the PMOS transistor PM2 has the gate-source voltage higher than the threshold voltage as the level of the external voltage VDD increases. Ascends to turn on. Therefore, the node DET2 is driven to the external voltage VDD level by the turned-on PMOS transistor PM2.

Subsequently, the inversion delay unit 144 and the delay unit 146 invert and delay the voltages applied to the output node DET2 of the detection unit 142 and output the positive and negative detection signals C and D, respectively. As shown in the figure, the positive sensing signal C maintains the level of the ground voltage VSS, and the negative sensing signal D rises along the level of the external voltage D.

Subsequently, the selector 160 outputs the positive sensing signal as the global power-up signal GL_PWRUP in response to the logic level 'H' of the test signal TM1. That is, the global power-up signal GL_PWRUP maintains the level of the ground voltage VSS like the positive sensing signal C.

Subsequently, the level of the divided voltage of the voltage divider 120 rises as the level of the external voltage VDD rises and rises above the threshold voltage of the NMOS transistor NM2.

Subsequently, the NMOS transistor NM2 in the detector 142 is turned on by the distribution voltage to drive the node DET2 to the ground voltage VSS level.

Subsequently, the inversion delay unit 144 and the delay unit 146 increase the positive sense signal C along the level of the external voltage VDD, and the negative sense signal D increases the level of the ground voltage VSS. Keep it. That is, the positive sensing signal C maintains the level of the ground voltage VSS. When the level of the external voltage VDD rises above the threshold voltage, the positive sensing signal C rises along the level of the external voltage VDD. In addition, the negative sensing signal D maintains the level of the initial external voltage VDD. When the negative sensing signal D is above the threshold voltage, the negative sensing signal D has the level of the ground voltage VSS.

Subsequently, the selector 160 outputs the positive sensing signal as the global power-up signal GL_PWRUP in response to the logic level 'H' of the test signal TM1. That is, the global power-up signal GL_PWRUP rises along the level of the external voltage VDD like the positive sensing signal C.

Therefore, when the test signal TM1 has the logic level 'H', the global power-up signal GL_PWRUP initially maintains the level of the ground voltage VSS, and the level of the external voltage VDD rises above the threshold voltage. If you have this level.

On the other hand, when the test signal TM2 has a logic level 'H' and the test signal TM1 has a logic level 'L', the test signal TM2 has the same driving as described above, and the sub-detection signal D is generated by the selection unit 160. It is output as the global power-up signal GL_PWRUP. Therefore, when the test signal TM2 is activated, the global power-up signal GL_PWRUP initially rises along the level of the external voltage VDD. When the test signal TM2 is activated, the global power-up signal GL_PWRUP is driven to the ground voltage VSS when the threshold voltage is higher than the threshold voltage.

Therefore, in the case of the present invention, the global power-up signal GL_PWRUP, which is driven to the ground voltage through the test signal, may be transmitted to the internal block actually used through the long wiring.

FIG. 6 is an internal circuit diagram of the level converter 200 shown in FIG. 3.

Referring to FIG. 6, the level converter 200 transmits the global power-up signal GL_PWRUP as the internal power-up signal INT_PWRUP in response to the test signal TM1, and responds to the test signal TM2. The inverter includes a transfer gate TG4 for transmitting the global power-up signal GL_PWRUP, and an inverter I4 for inverting the output signal of the transfer gate TG4 and outputting the internal power-up signal INT_PWRUP.

In operation, when the test signal TM1 is activated at the logic level 'H', the level converting unit 200 transmits the global power-up signal GL_PWRUP as the internal power-up signal INT_PWRUP.

When the test signal TM2 is activated at the logic level 'H', the global power up signal GL_PWRUP is inverted and output as the internal power up signal INT_PWRUP. This is because when the test signal TM2 is activated, the global power-up signal GL_PWRUP is driven to the ground voltage VSS, and thus is supplied back to the level of the external voltage VDD to the internal block 300 using the same. .

Meanwhile, the driving of the semiconductor memory device according to the present invention shown in FIGS. 3 to 6 will be briefly described.

First, the case of the initial setting in which the test signal TM1 has a logic level 'H' and the test signal TM2 has a logic level 'L' will be described.

The global power-up signal generator 100 maintains the global power-up signal GL_PWRUP at the level of the ground voltage in response to the activation of the test signal TM1. When the level of the external voltage VDD rises above the predetermined level, the global power-up signal GL_PWRUP is driven to the external voltage VDD in response to this. Therefore, the global power up signal GL_PWRUP rises along the level of the external voltage VDD. The global power-up signal GL_PWRUP is transmitted to the level converter 200 through a long wiring.

Subsequently, the level converter 200 transmits the global power-up signal GL_PWRUP as the internal power-up signal INT_PWRUP in response to the activation of the test signal TM1.

Through this process, when the level of the external voltage VDD is maintained above a certain level, the global power-up signal GL_PWRUP rises along the level of the external voltage VDD and is recognized as being activated at the logic level 'H'. . However, even when the global power-up signal GL_PWRUP is recognized as activated, the internal power-up signal INT_PWRUP may not be recognized as the logic level 'H'. This is because, as mentioned above, when the global power-up signal GL_PWRUP is transmitted through a long wiring, noise is introduced to destabilize the level of the global power-up signal GL_PWRUP.

In this case, the test signal TM2 may be changed to a logic level 'H' and the test signal TM1 may be changed to a logic level 'L' by changing a metal option or a fuse option in the test signal generator 500. At this time, the test signal generator 500 is stably initialized to change the test signals TM1 and TM2 because the test signal generator 500 receives the local power-up signal LC_PWRUP supplied from the adjacent local power-up signal generator 400. have. This is because the local power-up signal generation unit 400 is disposed adjacent to each other, thereby eliminating the possibility of noise introduced by a long wiring such as the global power-up signal GL_PWRUP.

Next, the test signal TM2 is activated.

The global power-up signal generator 100 maintains the global power-up signal GL_PWRUP at the level of the external voltage VDD in response to the activation of the test signal TM2. When the level of the external voltage VDD rises above the predetermined level, the global power-up signal GL_PWRUP is driven to the ground voltage VSS in response to this. The global power-up signal GL_PWRUP is transmitted to the level converter 200 through a long wiring.

Subsequently, in response to the activation of the test signal TM2, the level converter 200 inverts the global power up signal GL_PWRUP and transmits it to the internal power up signal INT_PWRUP. That is, the internal power up signal INT_PWRUP is a signal driven by an external voltage.

Subsequently, the internal block performs initial driving in response to the internal power-up signal INT_PWRUP.

As described above, in the semiconductor memory device according to the present invention, when the internal block cannot be powered up stably due to the long wiring, the test drive applies the test signal and drives to the ground voltage while passing the long wiring. Invert to drive to external voltage. For reference, the global power-up signal driven to the ground voltage has a smaller noise effect than the external voltage even through the long wiring.

Accordingly, the present invention eliminates the influence of noise caused by long wirings and performs stable power-up driving, thereby improving the reliability of the device.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The present invention described above eliminates the influence of noise due to long wirings and performs stable power-up driving, thereby improving the reliability of the device.

Claims (14)

Global power-up signal generation means for generating a global power-up signal in response to a predetermined level of an external voltage, and driving the power-up signal to an external voltage or a ground voltage in response to a test signal; Level conversion means for converting or maintaining the level of the global power-up signal in response to the test signal and outputting the internal power-up signal; And An internal block for initializing driving in response to the internal power-up signal A semiconductor memory device having a. The method of claim 1, The global power-up signal generating means is physically remote from the level converting means and the inner block; A semiconductor memory device characterized in that. The method of claim 2, The level converting means, A first transfer gate for transmitting the global power-up signal to the internal power-up signal in response to a first test signal; A second transfer gate for transmitting the global power-up signal in response to a second test signal; And a first inverter for inverting the output signal of the second transfer gate and outputting the internal power up signal. A semiconductor memory device characterized in that. The method of claim 3, The global power-up signal generating means, A voltage divider for dividing the external voltage and outputting the divided voltage; A signal output unit for sensing the level of the divided voltage and outputting the positive and negative sense signals; And a selector configured to select the positive or negative sense signal in response to the first and second test signals and to output the global power up signal. A semiconductor memory device characterized in that. The method of claim 4, wherein The signal output unit, A sensing unit for sensing the level of the external voltage; An inversion delay unit for inverting and delaying the output signal of the detection unit to output the positive detection signal; And a delay unit for delaying an output signal of the detection unit and outputting the output signal as the sub detection signal. A semiconductor memory device characterized in that. The method according to any one of claims 2 to 5, Test signal generating means for initializing in response to a local power-up signal to generate the first and second test signals; Disposed adjacent to the test signal generating means, further comprising a local power up signal generating means for generating the local power up signal in response to a predetermined level of the external voltage; A semiconductor memory device characterized in that. The method of claim 6, The detection unit, A PMOS transistor having the ground voltage as a gate input and having a source-drain path between a supply terminal of the external voltage and a node; An NMOS transistor having the divided voltage as a gate input and having a drain-source path between the node and a supply terminal of the ground voltage; Outputting the voltage across the node to its output A semiconductor memory device characterized in that. The method of claim 7, wherein The selection unit, A third transfer gate configured to output the positive detection signal as the global power-up signal in response to the first test signal; And a fourth transfer gate configured to output the negative sensing signal as the global power-up signal in response to the second test signal. A semiconductor memory device characterized in that. The method of claim 8, The voltage divider, First and second resistors connected in series between the supply terminal of the external voltage and the supply terminal of the ground voltage; Outputting the voltage across the connection node of the first and second resistors as the divided voltage; A semiconductor memory device characterized in that. The method of claim 9, The inversion delay unit includes three inverters connected in series A semiconductor memory device characterized in that. The method of claim 10, The delay unit includes two inverters connected in series A semiconductor memory device characterized in that. The method of claim 11, The test signal generating means includes a metal option or a fuse option A semiconductor memory device characterized in that. Driving a global power-up signal to an external voltage when the external voltage is below a predetermined level, and driving the global power-up signal to a ground voltage above the predetermined level; Inverting the global power-up signal to drive an internal power-up signal to the external voltage; And Initial power-up of an internal block in response to the internal power-up signal A method of driving a semiconductor memory device having a. The method of claim 13, The global power up signal is transmitted through a long distance wiring A method of driving a semiconductor memory device, characterized in that.

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