KR100851994B1 - Semiconductor memory apparatus and semiconductor integrated circuit using the same - Google Patents

Abstract

A semiconductor memory apparatus and a semiconductor integrated circuit using the same are provided to enable the semiconductor memory apparatus to start a test mode under mounting environment of the semiconductor memory apparatus. An input signal conversion unit(10) generates parallel data and a dividing clock by receiving an external clock and serial data inputted from the outside. A test mode entry signal output unit(20) comprises a decoder, a synchronization part and a signal output part. The decoder outputs one enabled decoding signal among a plurality of decoding signals generated by decoding the parallel data. The synchronization part outputs a synchronization signal by synchronizing the enabled decoding signal to the dividing clock. The signal output part outputs a corresponding test mode entry signal by inputting the synchronization signal and a power up signal. The input signal conversion unit includes a data conversion part and a clock dividing part.

Description

Semiconductor Memory Apparatus and Semiconductor Integrated Circuit Using The Same

1 is a block diagram of a semiconductor integrated circuit to which a semiconductor memory device according to the present invention is applied;

2 is a circuit diagram of the input signal conversion means of FIG.

3 is a circuit diagram of the test mode entry signal output means of FIG.

<Description of the symbols for the main parts of the drawings>

10: input signal conversion means 20: test mode entry signal output means

The present invention relates to a semiconductor memory device, and more particularly, to a circuit capable of entering a test mode in a mounting environment for failure analysis of a semiconductor memory device.

In the development process, even a semiconductor memory device that normally passes wafer and package tests may be defective according to various mounting environments.

In general, when a defect occurs during the wafer test or the package test process, the test mode is entered through a mode register set (MRS). When the semiconductor memory device enters the test mode, failure analysis of the semiconductor memory device may be performed by various test commands.

However, the conventional semiconductor memory device does not enter the test mode in the mounting environment. Therefore, the test command is not applied, and thus, the test command cannot be performed in the mounting environment of the semiconductor memory device.

Conventionally, the cause of the defect is found by directly applying an input signal input to the semiconductor memory device when the failure occurs in the mounting test process, but it is difficult to find the cause of the defect in the mounting environment. Therefore, as the failure cause analysis period increases, the development delay of the semiconductor memory device occurs.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problem, and an object thereof is to provide a semiconductor memory integrated circuit in which a semiconductor memory device may enter a test mode in a mounting environment of the semiconductor memory device.

The semiconductor memory device according to the present invention includes an input signal conversion means for generating parallel data and a divided clock by inputting external data and an external clock, and an activated one of a plurality of decoding signals generated by decoding the parallel data. A decoder for outputting a decoded signal of a signal, a synchronizer for synchronizing the activated decoded signal with the divided clock and outputting the signal as a synchronization signal, and a signal output for outputting a corresponding test mode entry signal with the synchronization signal and a power-up signal as inputs; And a test mode entry signal output means having a portion.

A semiconductor integrated circuit according to the present invention includes semiconductor memory control means for outputting serial data in response to an external input signal, and a semiconductor memory device, wherein the semiconductor memory device converts the serial data into parallel data and divides a clock into a divided clock. An input signal conversion means for converting the parallel data, a decoder for decoding the parallel data, a synchronizer for outputting the output signal of the decoder in synchronization with the divided clock, and a signal initialized in response to a power-up signal and synchronized with the divided clock. And a signal output unit outputting the test mode entry signal.

Hereinafter, an embodiment of a semiconductor memory device and a semiconductor integrated circuit using the same according to the present invention will be described in detail with reference to the accompanying drawings. In this case, the present invention will be described using, but not limited to, two-bit serial data and a divided clock divided by two for an external clock to select and output one of four test mode entry signals. The external clock clk shown in the accompanying drawings is a clock for a nonvolatile memory device input to the nonvolatile memory device.

1 is a block diagram of a semiconductor integrated circuit to which the semiconductor memory device according to the present invention is applied.

The semiconductor memory device control means 30 is a nonvolatile memory device that stores information of a semiconductor memory device, that is, information such as a memory module, a data rate, and the like. In this case, the semiconductor memory device control means 30 may use, for example, an electrically erasable and programmable read only memory (EEPROM), and a storage space capable of reading and writing a plurality of bits of serial data (data_s <0: 1>). This exists. The external clock clk is a clock for controlling the EEPROM, which is an EEPROM clock.

The input signal converting means 10 receives 2-bit serial data (data_s <0: 1>) and an external clock clk as inputs to 2-bit parallel data (data_p <0: 1>) and the external clock clk. Generates a divided clock (clk_df) divided by two.

The test mode entry signal output means 20 decodes the 2-bit parallel data data_p <0: 1> and tests one of the first to fourth test mode entry signals TM <0: 3> corresponding thereto. The mode entry signal TM <i> is output. At this time, the test mode entry signal output means 20 is initialized by a power-up signal pwrup. At this time, the number of bits of the serial data (data_s <0: 1>) and the parallel data (data_p <0: 1>) is 2 bits for convenience of description and a semiconductor memory device capable of selecting four test modes will be described. However, it should be noted that the semiconductor device and the semiconductor integrated circuit using the same according to the present invention can select four or more test modes using two or more bits of data.

FIG. 2 is a circuit diagram of the input signal conversion means of FIG. 1.

The input signal converting means 10 inputs 2-bit serial data data_s <0: 1> and an external clock clk to input 2-bit parallel data data_p <0: 1> and the external clock clk. Outputs the divided clock (clk_df) divided by two.

The input signal converting means 10 converts the 2-bit serial data data_s <0: 1> into the 2-bit parallel data data_p <0: 1>, and the external clock. and a clock divider 12 which divides clk into two and outputs the divided clock as clk_df.

The data converter 11 outputs the 2-bit serial data (data_s <0: 1>) sequentially input as the 2-bit parallel data (data_p <0: 1>).

The data converter 11 receives a first flip-flop 11-1 that receives 2-bit serial data data_s <0: 1> as an input signal, and an output signal of the first flip-flop 11-1. It includes a second flip-flop (11-2) receiving the input. In this case, the first and second flip-flops 11-1 and 11-2 are D flip-flops which output an input signal input thereto as an output signal in response to the external clock clk. In addition, the first flip-flop 11-1 outputs data_p <1> of the 2-bit parallel data data_p <0: 1>, and the second flip-flop 11-2 outputs data_p <0>. do. Therefore, the two-bit parallel data data_p <0: 1> are all output when two cycles of the external clock clk pass.

The clock divider 12 outputs the divided clock clk_df obtained by dividing the external clock clk by two. In this case, the clock divider 12 may be simply implemented using a counter, and thus detailed description thereof will be omitted.

3 is a circuit diagram of the test mode entry signal output means of FIG.

The test mode entry signal output means 20 selectively decodes the 2 bit parallel data data_p <0: 1> and outputs the first to fourth test entry mode signals TM <0: 3>. At this time, the test mode entry signal output means 20 is initialized by receiving a power-up signal pwrup.

The test mode entry signal output means 20 decodes the 2-bit parallel data data_p <0: 1> to generate first to fourth decoded signals dec1 to dec4, and the first A synchronization unit 22 for synchronizing the fourth to fourth decoding signals dec1 to dec4 with the divided clock clk_df and outputting the first to fourth synchronization signals dec_clk1 to dec_clk4, and responding to the power-up signal pwrup. And a signal output unit 23 configured to output the first to fourth test entry signals TM1 to TM4 by inputting the first to fourth synchronization signals dec_clk1 to dec_clk4. At this time, the divided clock clk_df is an external clock obtained by dividing the external clock clk by two.

The decoder 21 may include a first inverter IV1 that receives data_p <0> of the 2-bit parallel data data_p <0: 1>, a second inverter IV2 that receives data_p <1>, and the first inverter. A first AND gate AND1 that receives the output signals of the first and second inverters IV1 and IV2 and outputs the first decoding signal dec1, an output signal of the first inverter IV1 and the data_p <1 A second AND gate AND2 for receiving > and outputting the second decoding signal dec2, and receiving the output signal of the data_p <0> and the second inverter IV2 and receiving the third decoding signal dec3. And a fourth AND gate AND4 for outputting the fourth decoded signal dec4 by inputting the two-bit parallel data data_p <0: 1> as an input. . Accordingly, the decoder 21 activates and outputs one of the first to fourth decoding signals dec1 to dec4 according to each bit level of the 2-bit parallel data data_p <0: 1>.

The synchronization unit 22 outputs the first to fourth decoding signals dec1 to dec4 as the first to fourth synchronization signals dec_clk1 to dec_clk4 in synchronization with the divided clock clk_df.

Accordingly, the synchronization unit 22 corresponds to a synchronization signal corresponding to one activated decoding signal dec <i> of the first to fourth decoding signals dec1 to dec4 in response to the division clock clk_df. dec_clk <i>).

The synchronization unit 22 receives a fifth end gate AND5 and the second decoding signal outputting the first synchronization signal dec_clk1 by inputting the first decoding signal dec1 and the divided clock clk_df. The sixth AND gate AND6 outputting the second synchronization signal dec_clk2 by inputting dec2 and the divided clock clk_df, and the third decoded signal dec3 and the divided clock clk_df. The fourth synchronization signal dec_clk4 is inputted as a seventh AND gate AND7 for outputting the third synchronization signal dec_clk3, and the fourth decoding signal dec4 and the divided clock clk_df are inputted. And an eighth AND gate AND8 for outputting.

The signal output unit 23 is initialized in response to the power-up signal pwrup and outputs the first synchronization signal dec_clk1 as the first test entry signal TM1. A fourth flip-flop 23-2 initialized in response to the power-up signal pwrup and outputting the second synchronization signal dec_clk2 as the second test entry signal TM2 and the power-up signal pwrup A fifth flip-flop 23-3 that is initialized in response to the power up signal pwrup and is initialized in response to the third sync signal dec_clk3 as the third test entrance signal TM3. And a sixth flip-flop 23-4 outputting a fourth sync signal dec_clk4 as the fourth test entrance signal TM4. In this case, the third to sixth flip-flops 23-1, 23-2, 23-3, and 23-4 receive the power-up signal pwrup to the R input terminal and correspond to a corresponding synchronization signal dec_clk <i>. ) Is an SR flip-flop that receives S input.

Accordingly, the signal output unit 23 outputs a test entry signal TM <i> corresponding to the activated synchronization signal dec_clk <i> of the first to fourth synchronization signals dec_clk1 to dec_clk4.

The operation of the semiconductor integrated circuit according to the present invention configured as follows is as follows.

A test performed on a wafer or a package enters a specific address, for example, address 7 high into a mode register set (MRS), to enter a semiconductor memory device into a test mode and execute a test with various test commands.

However, since the semiconductor memory device is mounted, address 7 cannot be controlled separately, and thus the semiconductor memory device cannot enter the test mode. Therefore, it was difficult to test the mounted semiconductor memory device.

The present invention provides a circuit capable of entering various test modes after the semiconductor memory device is mounted in order to solve this difficulty.

1, 2, and 3 are diagrams for allowing a user using a semiconductor memory device to enter a desired test mode among four test modes. However, note that we do not present circuits that define only the four test modes.

When the semiconductor memory device is mounted, a test desired by the user through an electrically erasable and programmable read only memory (EEPROM) that stores information on the mounted semiconductor memory device, that is, information such as a memory module and a data rate. Serial data can be entered to enable entry into the mode. In the data storage space of the EEPROM, there is a data storage space for a user to read and write. The data is input as an external input signal corresponding to the test mode in a data storage space available to the user. Therefore, data output from an EEPROM information reading process and an external clock are input to the semiconductor memory device through an input / output pad of the semiconductor memory device during computer booting. As a result, the semiconductor memory device, that is, the DRAM, enters a test mode desired by the user.

The following describes the operation of the semiconductor memory device in more detail.

The data conversion section 11 of the input signal conversion means 10 outputs the input 2-bit serial data data_s <0: 1> as 2-bit parallel data data_p <0: 1>. The clock divider 12 of the input signal converting means 10 divides the external clock clk into two and outputs the divided clock clk_df.

The test mode entry signal output means 20 initializes all of the first to fourth test mode entry signals TM1 to TM4 to low in the period where the power-up signal pwrup is high.

After that, when the power-up signal pwrup transitions low, the decoder 21 of the test mode entry signal output means 20 decodes a signal dec <corresponding to the 2-bit parallel data data_p <0: 1>. i>). In addition, the synchronizer 22 of the test mode entry signal output means 20 supplies the synchronous signal dec_clk <i> to the activated decoding signal dec <i> at the timing when the divided clock clk_df transitions high. The signal output unit 23 outputs the activated synchronization signal dec_clk <i> as a test mode entry signal TM <i>.

The operation of the test mode entry signal output means 20 will be described in more detail.

If the logic level of the 2-bit parallel data data_p <0: 1> is high, data_p <0> is high and data_p <1> is low, the decoder 21 activates the third decoding signal dec3. Let's do it. That is, all of the other decoded signals dec1, dec2, and dec4 have low values, and only the third decoded signal dec3 has a high value. The synchronization unit 22 outputs only the third decoding signal dec3 that is high as the third synchronization signal dec_clk3 that is high at the timing when the frequency division clock clk_df transitions high. The signal output unit 23 which has received the third sync signal dec_clk3 that is high has only the third test entry signal TM3 of the first to fourth test entry signals TM1 to TM4 that are all low. Output high. As a result, the semiconductor memory device can enter a test mode desired by the user.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The semiconductor integrated circuit according to the present invention can enter a test mode even in a mounting environment of a semiconductor memory device, so that the cause of failure in the mounting environment can be easily found. In addition, the semiconductor integrated circuit according to the present invention can find the cause of the failure in the mounting environment faster than before, thereby reducing the development period.

Claims (12)

Input signal conversion means for generating parallel data and a divided clock by inputting serial data and an external clock input from the outside; And A decoder for outputting an activated one of a plurality of decoded signals generated by decoding the parallel data, a synchronizer for synchronizing the activated decoded signal with the divided clock and outputting a synchronized signal, and powering up the synchronized signal And a test mode entry signal output means having a signal output unit for outputting a corresponding test mode entry signal as a signal. The method of claim 1, The input signal conversion means A data converter configured to output the parallel data by inputting the serial data and the external clock; And a clock divider configured to divide the external clock to generate the divided clock. The method of claim 2, The data conversion unit And a plurality of flip-flops connected in series to output an input signal as an output signal in response to the external clock. The method of claim 2, The clock division unit And at least one counter for dividing the external clock. delete The method of claim 1, The synchronization unit And a plurality of AND gates for inputting the decoded signal and the divided clock. The method of claim 1, The signal output unit And a plurality of flip-flops initialized in response to the power up signal and outputting the synchronization signal as the test entry signal. Semiconductor memory control means for outputting serial data in response to an external input signal; And A semiconductor memory device, The semiconductor memory device includes input signal converting means for converting the serial data into parallel data and converting a clock into a divided clock, a decoder for decoding the parallel data, and a synchronizer for outputting the output signal of the decoder in synchronization with the divided clock. And a signal output unit initialized in response to a power up signal and outputting a signal synchronized with the divided clock as a test mode entry signal. delete The method of claim 8, The input signal conversion means A data converter for converting the serial data into the parallel data, and And a clock divider configured to generate the divided clock obtained by dividing the clock. delete The method of claim 8, The semiconductor memory control means And a nonvolatile memory device external to the semiconductor memory device and including information of the semiconductor memory device.

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