KR100851131B1 - Source/drain electrodes, thin-film transistor substrates, manufacture methods thereof, and display devices - Google Patents

Abstract

A source / drain electrode according to the present invention is used for a thin film transistor substrate including a substrate, a thin film transistor semiconductor layer, a source / drain electrode, and a transparent pixel electrode. The source / drain electrode comprises a nitrogenous layer and a thin film of pure aluminum or aluminum alloy. Nitrogen in the nitrogen-containing layer is bonded to silicon in the thin film transistor semiconductor layer, and a thin film of pure aluminum or aluminum alloy is connected to the thin film transistor semiconductor layer through the nitrogen-containing layer.

Description

SOURCE / DRAIN ELECTRODES, THIN-FILM TRANSISTOR SUBSTRATES, MANUFACTURE METHODS THEREOF, AND DISPLAY DEVICES

1 shows an enlarged schematic cross-sectional view illustrating the structure of a representative liquid crystal display panel employing an amorphous silicon thin film transistor substrate.

2 shows a schematic cross-sectional view illustrating the structure of a representative conventional amorphous silicon thin film transistor substrate.

3 shows a schematic cross-sectional view illustrating the structure of a thin film transistor substrate as one embodiment of the present invention.

4A, 4B, 4C, 4D, 4E, 4F, and 4G show process diagrams illustrating some of the manufacturing processes of the thin film transistor substrate of FIG. 3.

FIG. 5 shows a cross-sectional transmission electron micrograph of the interface between the Al—Ni alloy thin film and the channel amorphous silicon thin film prepared in Experimental Example 1. FIG.

FIG. 6 shows a cross-sectional transmission electron micrograph of the interface between an Al—Ni alloy thin film and a channel amorphous silicon thin film of a sample without a nitrogen containing layer as a comparative sample.

FIG. 7 shows a Kelvin pattern used to measure contact resistivity between aluminum alloy thin films and transparent pixel electrodes.

8 shows a diagram showing how the stress of the film changes with the deposition temperature of the aluminum alloy film.

FIG. 9 shows a cross-sectional transmission electron micrograph of the interface between the Al—Ni alloy thin film and the channel amorphous silicon thin film prepared in Experimental Example 14. FIG.

FIG. 10 shows a cross-sectional transmission electron micrograph of the interface between the Al—Ni alloy thin film and the channel amorphous silicon thin film prepared in Experimental Example 15.

The present invention relates to source / drain electrodes and substrates for use in thin film transistors of liquid crystal displays, semiconductor devices and optical components. Moreover, this invention relates to the manufacturing method of a said board | substrate, and a display device. More particularly, the present invention relates to novel source / drain electrodes comprising pure aluminum or aluminum alloy thin films as components.

Liquid crystal displays are used in a variety of applications, from small mobile phones to large televisions with screens of 30 inches or larger. These are classified into simple matrix liquid crystal display devices and active matrix liquid crystal display devices by the pixel driving method. Among these, an active matrix liquid crystal display device having a thin film transistor (hereinafter referred to simply as TFT) as a switching element is widely used because it can realize a high resolution image and generate an image at high speed.

Referring to FIG. 1, a substrate having a TFT array using, for example, hydrogenated amorphous silicon as an active semiconductor layer (hereinafter referred to as an “amorphous silicon thin film transistor substrate”) (hereinafter referred to as a “thin film transistor substrate”). The structure and principle of operation of an exemplary liquid crystal panel for use in an active matrix liquid crystal display device are illustrated.

The liquid crystal display panel 100 in FIG. 1 includes a thin film transistor substrate 1, an opposing substrate 2, and a liquid crystal layer 3. The opposing substrate 2 is disposed to face the thin film transistor substrate 1. The liquid crystal layer 3 is disposed between the thin film transistor substrate 1 and the opposing substrate 2 and functions as a light modulation layer. The thin film transistor substrate 1 includes an insulated glass substrate 1a, on which a thin film transistor 4, a transparent pixel electrode 5, and an interconnection section 6 including scan lines and signal lines are disposed. do. The transparent pixel electrode 5 is typically made of indium tin oxide (ITO) containing indium oxide (In ₂ O ₃ ) and about 10 mass% tin oxide (SnO). The thin film transistor substrate 1 is driven by the control circuit 14 connected thereto via the drive circuit 13 and the TAB tape 12.

The opposing substrate 2 includes an insulating glass substrate 1b, a common electrode 7, a color filter 8 and a light shielding film 9. The common electrode 7 is disposed on the front surface of the glass substrate 1b facing the thin film transistor substrate 1. The entire counter substrate 2 operates as a counter electrode. The color filter 8 is disposed at a position facing the transparent pixel electrode 5. The light shielding film 9 is disposed on the thin film transistor substrate 1 so as to face the thin film transistor 4 and the wiring portion 6. The opposing substrate 2 further has an alignment layer 11 for orienting liquid crystal molecules (not shown) in the liquid crystal layer 3 in a predetermined direction.

The liquid crystal display panel further includes polarizing plates 10a and 10b disposed on the outside of the thin film transistor substrate 1 and the opposing substrate 2 (on the opposing surface to the liquid crystal layer 3), respectively.

In the liquid crystal display panel 100, the electric field formed between the counter electrode 2 (common electrode 7) and the transparent pixel electrode 5 controls the alignment direction of the liquid crystal molecules in the liquid crystal layer 3 by the liquid crystal layer. The light passing through (3) is modulated. As a result, the amount of light transmitted through the opposing substrate 2 is controlled to generate and display an image.

Next, the structure and operating principle of a conventional amorphous silicon thin film transistor substrate for use in a liquid crystal display panel will be illustrated in detail with reference to FIG. FIG. 2 is an enlarged view illustrating main parts of “A” of FIG. 1.

Referring to Fig. 2, a scanning line (thin film gate wiring) 25 is disposed on a glass substrate (not shown). Part of the scan line 25 acts as a gate electrode 26 for controlling (on and off operation) the thin film transistor. The gate insulator (silicon nitride film) 27 is disposed to apply the gate electrode 26. The signal line (source / drain wiring) 34 is disposed so that the gate insulator 27 interposed therebetween and the scanning line 25 intersect. Part of the signal line 34 acts as the source electrode 28 of the thin film transistor. In the vicinity of the gate insulator 27, an amorphous silicon channel film (active semiconductor film) 33, a signal line (source / drain wiring) 34, and a silicon nitride interlayer dielectric film (protective film) 30 are sequentially arranged. This type of liquid crystal display panel is generally referred to as a bottom gate type panel.

The amorphous silicon channel film 33 includes a doped layer (n layer) and an intrinsic layer (i layer, also referred to as undoped layer) doped with phosphorus (P). On the gate insulator 27, there is a pixel area in which the transparent pixel electrode 5 is disposed. The transparent pixel electrode 5 is formed of, for example, an ITO film containing In ₂ O ₃ and SnO. The drain electrode 29 of the thin film transistor is contacted and electrically connected to the transparent pixel electrode 5 via a barrier metal layer described later.

When the gate voltage is applied to the gate electrode 26 through the scan line 25, the thin film transistor 4 is turned on. In this state, the driving voltage applied to the signal line 34 is applied from the source electrode 28 to the transparent pixel electrode 5 through the drain electrode 29. When the transparent pixel electrode 5 is applied with a driving voltage having a predetermined level, a potential difference occurs between the transparent pixel electrode 5 and the counter electrode 2 as described above with reference to FIG. 1. This potential difference causes light modulation by orienting or aligning the liquid crystal molecules in the liquid crystal layer 3.

In the thin film transistor substrate 1, the source / drain wires 34 are electrically connected to the source / drain electrodes; The signal line is electrically connected to the transparent pixel electrode 5 (signal line to the pixel electrode); The scanning lines 25 electrically connected to the gate electrode 26 are made from thin films of pure alloys or aluminum alloys, such as Al-Nd (hereinafter, pure aluminum and aluminum alloys collectively referred to as "aluminum alloys"). This is because such pure aluminum or aluminum alloy has low resistivity and can be easily processed. Barrier metal layers 51, 52, 53 and 54 containing a refractory metal such as Mo, Cr, Ti or W are disposed on and / or under these wirings as shown in FIG. Representative examples of such wiring include a molybdenum (Mo) layer having a thickness of about 50 nm (bottom barrier metal layer), a pure aluminum or Al-Nd alloy thin film having a thickness of about 150 nm, and a Mo layer having a thickness of about 50 nm (upper barrier). It is a multilayer (three layer) wiring including the metal layer) arranged in order.

The reason why the three-layered multilayer wiring is used as the source / drain wiring 34 connected to the channel amorphous silicon thin film 33 will be described later.

As shown in FIG. 2, the lower barrier metal layer 53 is disposed between the channel amorphous silicon thin film 33 and the aluminum alloy thin film. This configuration is mainly formed to prevent interdiffusion between silicon and aluminum at the interface between the aluminum alloy film and the channel amorphous silicon thin film (hereinafter simply referred to as "interface").

If the aluminum alloy is in direct contact with the channel amorphous silicon thin film, and a heat treatment such as sintering or annealing is performed in the subsequent chamber for the production of the thin film transistor, aluminum in the aluminum alloy diffuses into the amorphous silicon and / or silicon in the amorphous silicon is aluminum Diffuse into the alloy. As a result, the performance of amorphous silicon as a semiconductor is greatly degraded, thus reducing the on-state current, leakage of current (off-state current) and / or switching speed of the thin film transistor when the thin film transistor is off-state. Is reduced. Therefore, the desired thin film transistor characteristics cannot be achieved, and the formed display device has inferior performance and quality. Lower barrier metal layer 53 effectively prevents interdiffusion between aluminum and silicon.

The upper barrier metal layer 54 is mainly disposed to prevent the formation of hillocks (or shaped projections) on the surface of the aluminum alloy thin film and to ensure contact with ITO to be disposed thereon. Hillock will probably be formed as a result of heat treatment generally of about 300 ° C to about 400 ° C. This heat treatment is performed in the formation of a silicon nitride film (protective film) after the formation of the aluminum alloy thin film in the manufacturing process of the thin film transistor substrate. Specifically, the substrate including the aluminum alloy thin film is typically treated by chemical vapor deposition (CVD) to form a silicon nitride film (protective film). Hillock is probably caused by the thermal expansion coefficient difference between the aluminum alloy thin film and the glass substrate in this process. The upper barrier metal layer 54 effectively prevents the formation of hillocks.

However, the formation of the upper and lower barrier metal layers requires an additional deposition system for the formation of the metal layer, in addition to the deposition system for the formation of the aluminum alloy interconnects. Specifically, a deposition system must be used that includes an additional deposition chamber for the formation of each barrier metal thin film. A representative example of such a system is a cluster tool system including a plurality of deposition chambers connected to a transfer chamber. Systems including additional units for the formation of such barrier metal layers increase manufacturing costs and lower productivity and should be avoided in large scale, low cost production of liquid crystal panels.

 As shown in FIG. 2, the aluminum alloy thin film is connected to the transparent pixel electrode 5 via the barrier metal layer 51. If the aluminum alloy thin film is directly connected to the transparent pixel electrode, the contact resistance between these parts becomes high and the quality of the displayed image is impaired. Aluminum used as a material for wiring to a transparent pixel electrode is very oxidized. Thus, the insulating layer of aluminum oxide is formed at the interface between the aluminum alloy thin film and the transparent pixel electrode. Aluminum oxide is caused by oxygen formed or added during the film forming process of the liquid crystal display panel. Although indium tin oxide (ITO) is an electrically conductive metal oxide as a material for the transparent pixel electrode, it does not form an electrical ohmic contact when the aluminum oxide layer is formed as described above.

However, the formation of such a barrier metal layer requires an additional deposition chamber for the formation of the barrier metal layer in addition to the sputtering system for the formation of the gate electrode, the source electrode and the drain electrode. These additional units raise manufacturing costs and lower productivity.

In addition, the metal used as the barrier metal layer is processed by a treatment such as wet etching with a chemical solution at a different ratio from pure aluminum and aluminum alloy. Therefore, the processing size in the cross sectional direction in the processing is not appropriately adjusted. Therefore, the formation of the barrier metal layer requires complicated processing, which raises the production cost and lowers productivity in terms of film formation and processing.

Thus, it is possible to eliminate the need for a barrier metal layer and to allow for direct contact between the source / drain electrodes and the transparent pixel electrode, and for materials capable of direct contact between semiconductor layers such as source / drain electrodes and channel amorphous silicon thin films. There has been a suggestion.

Japanese Unexamined Patent Application Publication No. Hei 11-337976 discloses a technique using indium zinc oxide (IZO) containing indium oxide and about 10% by mass of zinc oxide as a material for a transparent pixel electrode. However, according to this technique, the most widely used ITO film should be replaced with an IZO film, but such an IZO film causes an increase in material cost.

Japanese Patent Laid-Open No. 11-283934 discloses a method of modifying the surface of a drain electrode by treating the drain electrode by plasma treatment or ion implantation. However, this method requires an additional chamber for surface treatment, which leads to a decrease in productivity.

Japanese Patent Laid-Open No. 11-284195 discloses a method of constructing a gate electrode, a source electrode and a drain electrode, wherein the drain electrode is formed of a first layer of pure aluminum or an aluminum alloy and nitrogen, oxygen, silicon and carbon. It consists of a second layer of aluminum alloy or pure aluminum further comprising impurities such as. This method has the advantage that thin films for constituting the gate electrode, the source electrode and the drain electrode can be formed continuously in one deposition chamber. However, this method requires an additional chamber to form a second layer containing impurities. In addition, the resulting source / drain interconnects are often two-layered from the wall surface of the deposition chamber in chambers that incorporate impurities into the source / drain interconnects. This is due to the thermal expansion coefficient difference between the film containing impurities and the film containing impurities. In order to solve this problem, this method requires maintenance to frequently stop the deposition chamber, which seriously degrades the productivity.

Under these circumstances, the present inventors have eliminated the need for a barrier metal layer in Japanese Patent Application Laid-open No. 2004-214606, simplifying the manufacturing process without increasing the number of chambers, and directly and between the aluminum alloy film and the transparent pixel electrode. Disclosed is a method in which reliable contact is possible. In the technique disclosed in Japanese Patent Laid-Open No. 2004-214606, 0.1 to 6 atomic% of at least one selected from the group consisting of Au, Ag, Zn, Cu, nickel, Sr, Ge, Sm, and Bi as alloy elements, The object was achieved by using an aluminum alloy such that at least one of these alloying elements is a precipitated layer or a concentrated layer at the interface between the aluminum alloy film and the transparent pixel electrode.

Japanese Laid-Open Patent Publication No. 2003-273109 discloses a thin film for three-layer aluminum alloy wiring comprising an electrically conductive top aluminum nitride layer (AlN layer), an aluminum alloy thin film, and an electrically conductive bottom aluminum nitride layer in that order. The upper aluminum nitride layer was directly connected to the ITO film to realize a satisfactory low contact resistance. The lower aluminum nitride layer was directly connected to a semiconductor layer, such as an amorphous silicon layer, showing good ohmic contact. However, this method requires quite complicated control in sputtering because sputtering must be performed while appropriately adjusting the composition and properties of the reaction gas to form the aluminum nitride layer. In addition, there is still room for improvement in contact resistance and ohmic contact in this method, and there has been a need for such further improvement.

Although the above description has been given by taking a liquid crystal display device as a representative example, problems in the prior art are commonly present in amorphous silicon thin film transistor substrates used in not only liquid crystal display devices but also other devices. This problem also occurs in thin film transistor substrates using polycrystalline silicon instead of amorphous silicon as the semiconductor layer of the thin film transistor.

The present invention has been made under such circumstances, and one object of the present invention is to provide a technique that provides excellent thin film transistor characteristics without a lower barrier metal layer and enables direct and reliable connection between the source / drain wiring and the semiconductor layer of the thin film transistor. To provide.

It is another object of the present invention to ensure excellent thin film transistor characteristics, high thermal stability and low contact resistivity without the lower barrier metal layer and the upper barrier metal layer, and to ensure the direct and reliable connection of source / drain wiring to the transparent pixel electrode as well as the semiconductor layer of the thin film transistor. It is to provide a technology that enables the connection.

In order to achieve the above objects, the present invention provides a source / drain electrode for use in a thin film transistor substrate including a substrate, a thin film transistor semiconductor layer, a source / drain electrode, and a transparent pixel electrode. And a thin film composed of a nitrogen containing layer and a pure aluminum or aluminum alloy, wherein the source / drain electrode is configured such that the nitrogen of the nitrogen containing layer is combined with the silicon of the thin film transistor semiconductor layer, and the thin film of pure aluminum or aluminum alloy contains the nitrogen containing layer. It is configured to be connected to the thin film transistor semiconductor layer through.

In a preferred embodiment, the nitrogenous layer mainly contains silicon nitride.

In another preferred embodiment, the nitrogenous layer contains silicon oxynitride.

The nitrogen-containing layer preferably has a nitrogen atom surface density (N1) of 1 x 10 ¹⁴ cm ^-2 or more and 2 x 10 ¹⁶ cm ^-2 or less.

The nitrogenous layer has an oxygen atom surface density (O1), and the ratio of N1 to O1 (N1 / O1) is preferably 1.0 or more.

The nitrogen-containing layer preferably has a nitrogen atom surface density that is equal to or greater than the surface density of the silicon effective dangling bond constituting the semiconductor layer.

The nitrogenous layer preferably has a thickness in the range of 0.18 nm or more and 20 nm or less.

In another preferred embodiment, the nitrogenous layer has a plurality of nitrogen atoms (N) and a plurality of silicon atoms (Si), and the maximum ratio of N to Si (N / Si) is in the range of 0.5 or more and 1.5 or less.

The thin film transistor semiconductor layer preferably contains amorphous silicon or polycrystalline silicon.

The aluminum alloy preferably contains 6 atomic% or less Ni (nickel) as the alloying element.

In another preferred embodiment, the thin film of pure aluminum or aluminum alloy is a thin film composed of an aluminum alloy, the aluminum alloy containing at least 0.3 atomic percent and at most 6 atomic percent nickel (Ni) as an alloying element, the source / drain electrode A thin film of silver aluminum alloy is additionally configured to be directly connected to the transparent pixel electrode.

The aluminum alloy also contains, as an alloying element, at least 0.1 atomic% to 1.0 atomic% of at least one element selected from the group consisting of Ti, V, Zr, Nb, Mo, Hf, Ta and W.

In another preferred embodiment the aluminum alloy is also selected from the group consisting of Mg, Cr, Mn, Ru, Rh, Pd, Ir, Pt, La, Gd, Tb, Dy, Nd, Y, Co and Fe as alloying elements. One or more elements are contained in 0.1 atomic% or more and 2.0 atomic% or less.

The present invention also provides a thin film transistor substrate comprising the source / drain electrodes.

The invention also provides a display device comprising a thin film transistor substrate.

In addition and advantageously, the present invention relates to the provision of a method of manufacturing the thin film transistor substrate, the method comprising the steps of: (a) forming a semiconductor layer on or on a substrate to produce a thin film transistor substrate; (b) forming a nitrogen-containing layer on the semiconductor layer; And (c) forming a layer of pure aluminum or an aluminum alloy on the nitrogenous layer.

In a preferred embodiment, the semiconductor layer is formed in the film forming system in step (a), and step (b) is performed in the same film forming system.

In another preferred embodiment, the semiconductor layer is formed in a chamber in step (a), and step (b) is performed in the same chamber.

In another embodiment, the semiconductor layer is formed at a constant film formation temperature in step (a), and step (b) is performed at a temperature substantially the same as the film formation temperature.

In another preferred embodiment, the semiconductor layer in step (a) is formed using a gas, step (b) is carried out in a mixed atmosphere of the gas and nitrogen-containing gas.

In another embodiment, step (b) is carried out in a mixed atmosphere of a nitrogenous gas and a reducing gas.

Preferably, step (b) is carried out by a plasma nitridation process.

Preferably, the plasma nitriding process is carried out at a pressure of at least 55 Pa.

Preferably, the plasma nitriding process is carried out at a temperature of 300 ℃ or more.

Preferably, the plasma nitriding process is carried out in a mixture atmosphere of nitrogen-containing gas and reducing gas.

The plasma nitridation process of step (b) is preferably carried out in a mixed atmosphere of the nitrogenous gas and the gas used in step (a).

In another preferred embodiment, step (b) is carried out by a thermal nitriding process.

Preferably, the thermal nitriding process is carried out at a temperature of 400 ° C. or less.

Step (b) is carried out by an amination process.

Preferably, the amination process uses ultraviolet radiation.

Preferably, the amination process uses a solution containing nitrogen.

Step (c) is carried out using a sputtering process.

The source / drain electrodes of the present invention have the above-described configuration, and generally used aluminum or aluminum alloy can be used. In addition, the source / drain electrodes of the present invention can be connected to the semiconductor layer of the thin film transistor through a nitrogen-containing layer without a barrier metal layer, unlike conventional equivalents (source / drain electrodes). The source / drain electrodes have good thin film transistor characteristics.

By additionally using an Al-Ni alloy containing a specific amount of nickel as the aluminum alloy, the source / drain electrodes according to the present invention can be directly connected not only to the semiconductor layer of the thin film transistor but also to the transparent pixel electrode. The prepared source / drain electrodes have excellent thin film transistor characteristics, contact resistivity, and thermal stability.

By using the source / drain electrodes according to the present invention, it is possible to manufacture high performance display devices having excellent productivity at low cost.

Further objects, features and advantages of the present invention will become apparent from the following description of the preferred embodiments with reference to the accompanying drawings.

The inventors studied extensively to provide a novel source / drain electrode to be connected to a semiconductor layer of a thin film transistor. Specifically, the present inventors can exhibit excellent thin film transistor characteristics when connected to the semiconductor layer without intervening the barrier metal layer, unlike the conventional equivalent source / drain electrodes, and are generally used as materials for wiring of the source / drain electrodes. In order to provide novel source / drain electrodes that can be used without processing, pure aluminum or aluminum alloys (hereinafter, commonly referred to as "aluminum alloys") which are commonly used are studied. As a result, the inventors have found that the above objects can be achieved by arranging the source / drain electrodes adjacent to the semiconductor layer from the nitrogen-containing layer and the aluminum alloy thin film, wherein nitrogen (N) in the nitrogen-containing layer is formed of silicon in the semiconductor layer ( Si). The present invention has been made based on these findings. This configuration enables a direct connection between the aluminum alloy thin film and the semiconductor layer of the thin film transistor through the nitrogen containing layer.

By using an aluminum alloy (hereinafter referred to as an "Al-Ni alloy" to distinguish it from a conventional aluminum alloy) as an aluminum alloy additionally containing 0.3 to 6 atomic% nickel, the Al-Ni alloy thin film is made of a transparent pixel electrode. Can be connected directly to This provides a source / drain electrode having excellent electrical properties without a barrier metal layer, unlike a source / drain electrode which is a conventional equivalent.

As used herein, the term "source / drain electrode" means and includes both the source / drain electrode itself and the source / drain wiring. Specifically, each of the source / drain electrodes according to the present invention includes a source / drain electrode integrated with the source / drain wiring, and the source / drain wiring is in contact with the source / drain region.

Source / drain electrodes according to the invention are described in detail below. For convenience of description, the source / drain electrodes are classified and distinguished as "source / drain electrodes according to the first embodiment" and "source / drain electrodes according to the second embodiment". The source / drain electrode according to the first embodiment can be connected to the semiconductor layer of the thin film transistor without intervening the barrier metal layer, and the source / drain electrode according to the second embodiment is connected to the semiconductor layer of the thin film transistor without intervening the barrier metal layer. It may also be directly connected to the transparent pixel electrode. The source / drain electrode according to the second embodiment has the same configuration as the source / drain electrode according to the first embodiment except for the composition of the aluminum material.

Source / drain electrodes according to the first embodiment

Each of the source / drain electrodes according to the first embodiment includes a nitrogen-containing layer and an aluminum alloy thin film. The nitrogen-containing layer is disposed to cover the thin film transistor semiconductor layer, and nitrogen in the nitrogen-containing layer bonds with silicon of the semiconductor layer. The nitrogenous layer serves as a barrier for preventing interdiffusion between aluminum and silicon at the interface between the aluminum alloy thin film and the thin film transistor semiconductor layer. The source / drain electrode according to the first embodiment thus exhibits excellent thin film transistor characteristics, typically without the barrier metal layer of molybdenum (Mo), unlike the conventional equivalent source / drain electrode, as demonstrated in the experimental example below. to provide. This configuration eliminates the need for a separate deposition system for the formation of a barrier metal, since the nitrogenous layer can be easily formed by, for example, a plasma nitridation process after the formation of the semiconductor layer and before the formation of the aluminum alloy layer. do.

The nitrogenous layer which characterizes the present invention will be described in detail below.

Nitrogen (N) in the nitrogen-containing layer is bonded to silicon in the semiconductor layer, whereby the nitrogen-containing layer mainly contains silicon nitride, as described above. This layer additionally contains silicon oxynitride. Silicon oxynitride is formed as a result of combining silicon nitride with oxygen (O), which is inevitably introduced during the process of forming the nitrogenous layer, for example.

The nitrogenous layer preferably further satisfies the following requirements, as demonstrated in the experimental examples below.

The nitrogen-containing layer preferably has a nitrogen surface density of at least the surface density of the effective suspension bond of the material (typically silicon) of the semiconductor layer of the thin film transistor. As described above, the surface of the semiconductor layer should be covered with a nitrogenous layer to prevent interdiffusion between the metallization material and the semiconductor material. In this case, the unbound bond (suspension bond) of the surface of the semiconductor layer is preferably bonded with nitrogen. As used herein, the term "effective suspension bond" means a bond that may exist on the surface of a semiconductor layer even when steric hindrance of nitrogen atoms is taken into account. The term "surface density of effective suspending bond" is a surface density assuming that the nitrogenous layer covers the entire surface of the semiconductor layer. The surface density of effective suspension bonds depends on the type of semiconductor material. Silicon is substantially in the range of about 1 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁵ cm ⁻² , but slightly depending on the direction of the crystal plane.

Specifically, the nitrogenous layer is 1 x at the interface between a thin film of pure aluminum or an aluminum alloy and the semiconductor layer both in the case where it mainly comprises silicon nitride and when it further comprises silicon oxynitride in addition to silicon nitride as the main component. It is preferred to have a nitrogen surface density (N1) of at least 10 ¹⁴ cm ⁻² and up to 2 × 10 ¹⁶ cm ⁻² . In order to ensure desired thin film transistor characteristics, the nitrogen surface density (N1) of the nitrogen-containing layer is more preferably at least 2 x 10 ¹⁴ cm ^-2 , even more preferably at least 4 x 10 ¹⁴ cm ^-2 . However, excessively high nitrogen surface density (N1) of the nitrogenous layer may increase the amount of insulating silicon nitride in the nitrogenous layer. This increases the electrical resistance, thus degrading the thin film transistor characteristics. More preferably, the upper limit of the nitrogen surface density (N1) is 1 × 10 ¹⁶ cm ⁻² .

When the nitrogen-containing layer contains silicon oxynitride, that is, when the nitrogen-containing layer further contains silicon oxide in addition to silicon nitride, in addition to the requirement for the surface density of nitrogen (N1), the surface density of oxygen (O1) It is preferable that ratio (N1 / O1) of surface density (N1) of nitrogen is 1.0 or more. This further improves thin film transistor characteristics. Silicon nitride and silicon oxynitride are primarily insulators, but as described below, the electrical resistance in this configuration is low because the nitrogenous layer has a very small thickness of, for example, 0.18 nm or more and 20 nm or less. Can be.

The inventors have found through experiments that the thin film transistor characteristics are affected by the N1 / O1 ratio, and as demonstrated in the experimental examples mentioned later, the N1 / O1 ratio is greater than 1.0 to provide better thin film transistor characteristics. It should be desirable to be. This is probably because the resistive component in the nitrogen-containing layer decreases at a high ratio of N1 / O1 to obtain satisfactory properties as a thin film transistor. The N1 / O1 ratio is preferably as high as possible, more preferably 1.05 or more, still more preferably 1.1 or more.

The N1 / O1 ratio can be adjusted by appropriately adjusting plasma generating conditions such as plasma gas pressure and gas composition, and process temperature, for example, in the formation of a nitrogen-containing layer using a plasma nitridation process. This will be explained in detail below.

The surface density (N 1) of nitrogen and the surface density (O 1) of oxygen in the nitrogen-containing layer can be measured, for example, by a Rutherford backscattering spectrometer (RBS).

It is preferable that the thickness of a nitrogen containing layer is 0.18 nm or more and 20 nm or less. As described above, the nitrogenous layer is effective as a barrier layer that prevents interdiffusion between aluminum and silicon at the interface between the aluminum alloy layer and the thin film transistor semiconductor layer, but the excessively thick nitrogenous layer will impair the performance of the thin film transistor. Can be. The increase in the electrical resistance due to the presence of the nitrogenous layer can be adjusted within the above range so as not to adversely affect the performance of the TFT by adjusting the thickness of the nitrogenous layer within the range specified above. The thickness of the nitrogen-containing layer is more preferably 15 nm or less, and even more preferably 10 nm or less. In the nitrogenous layer, at least one monolayer of silicon-nitrogen bond is sufficient. The atomic distance of silicon-nitrogen is about 0.18 nm, and therefore, the minimum thickness of the nitrogen-containing layer is preferably 0.18 nm or more. The thickness of the nitrogen-containing layer is more preferably 0.2 nm and even more preferably 0.4 nm. The thickness of the nitrogenous layer can be measured by various physical analysis procedures, such as the above-mentioned RBS method, X-ray photoelectron spectrometer (XPS), secondary ion mass spectrometer (SIMS), and RF glow discharge emission spectrometer ( GD-OES). The thickness of the nitrogenous layer is measured by RBS and XPS in the experimental example described later.

In the nitrogen-containing layer, the maximum ratio (N / Si) of nitrogen atoms to silicon atoms is preferably 0.5 or more and 1.5 or less. This allows the nitrogenous layer to act effectively as a barrier without degrading the thin film transistor characteristics. It is more preferable that N / Si ratio is 0.6 or more, and it is still more preferable that it is 0.7 nm or more.

The N / Si ratio can be adjusted, for example, by controlling the irradiation time of the plasma within the range of about 1 minute to about 10 minutes. This will be explained in detail below.

The N / Si ratio can be measured, for example, by analyzing these elements (nitrogen and silicon) in the thickness direction of the nitrogenous layer according to RBS.

The nitrogen-containing layer is formed by, for example, nitriding the uppermost layer of the semiconductor layer. The nitriding step is not particularly limited and, as described in detail below, includes, for example, (i) plasma nitriding step, (ii) thermal nitriding step, and (iii) amination step.

(Iii) plasma nitridation process

The plasma nitridation process uses plasma. This process preferably uses a nitrogen containing gas, as demonstrated in Example 1 and Experimental Example 1 described below. The nitrogenous gas may be a non-oxidizing gas such as N ₂ , NH ₃ , or NF ₃ . Each of these gases may be used alone or in combination as a gas mixture. If an oxidizing gas such as N ₂ O is used, since silicon in the surface of the semiconductor layer is very easily oxidized, the reaction between oxygen (O) and silicon in the oxidizing gas proceeds before the reaction between nitrogen and silicon, and thus the desired silicon nitride layer. Will not form. Specifically, the thin film transistor semiconductor layer is preferably located near the plasma source containing nitrogen. The distance between the plasma source and the semiconductor layer may be determined within an appropriate range depending on the type of plasma and the conditions for plasma generation such as force, pressure, temperature and gas composition. The distance is preferably about tens of centimeters or less. The high-energy nitrogen atoms are in the immediate vicinity of the plasma and can easily form the desired nitrogenous layer on the surface of the semiconductor layer.

Nitrogen can be supplied from a nitrogenous plasma source, for example by ion implantation. In this case, the distance between the plasma source and the semiconductor layer can be arbitrarily determined because the ions accelerated by the electric field can go a long distance. The ion implantation is preferably performed by placing the semiconductor layer near the plasma source and applying high voltage negative pulses to the semiconductor layer to inject ions into the entire surface of the semiconductor layer. Alternatively, ion implantation can be performed using an ion implantation dedicated device.

Plasma generation conditions, such as the pressure and composition of the gas for plasma generation, and the process temperature, are described in the experimental examples described below, the surface density of nitrogen (N1) versus the surface density (O1) of oxygen in the nitrogen-containing layer. It is desirable to adjust the ratio N1 / O1 to 1.0 or more in the following manner to further improve the thin film transistor characteristics. This effectively prevents the oxidation of the semiconductor layer, accelerates the nitriding reaction and increases the efficiency of the nitriding.

Specifically, the reaction pressure is preferably 55 Pa or more. When the pressure is less than 55 Pa, the nitriding reaction may proceed slowly, and it may take a long time to form a nitrogen-containing layer that can effectively serve as a diffusion barrier. In addition, the oxidation reaction can proceed considerably before the nitriding reaction, resulting in deterioration of the thin film transistor characteristics. In this regard, the pressure is preferably as high as possible, more preferably at least 60 Pa, even more preferably at least 66 Pa. The upper limit of pressure typically depends on the performance of the system or unit used and may not be unique. In view of stable supply of plasma, the pressure is preferably about 400 Pa or less, and more preferably about 266 Pa or less. For example, the upper limit of the pressure for stable supply of plasma is 133 Pa in the system used in Experimental Example 11 described later.

It is preferable that reaction temperature is 300 degreeC or more. If the reaction temperature is less than 300 ℃, the nitriding reaction is slow, it may take a long time to form a nitrogen-containing layer that can effectively serve as a diffusion barrier. In addition, the oxidation reaction can proceed considerably before the nitriding reaction, resulting in deterioration of the thin film transistor characteristics. However, an excessively high reaction temperature may lead to degradation and damage of the semiconductor layer, so the reaction temperature is preferably about 360 ° C. or less.

As the gas used herein, a nitrogen-containing gas such as N ₂ , NH ₃ , or NF ₃ may be used alone, but a mixture of this nitrogen-containing gas and a reducing gas is preferable. This more effectively prevents oxidation of the semiconductor layer. Examples of the reducing gas include NH ₃ and H ₂ . Among these gases, NH ₃ serves not only as a reducing gas but also as a nitrogen containing gas, and may be used alone or in combination with, for example, H ₂ .

Alternatively, the gas for plasma nitridation is preferably a gas mixture of nitrogen-containing gas and material gas (SiH ₄ ) used for forming the semiconductor layer. When the nitrogenous layer is formed using only nitrogenous gas, the gas used for the formation of the semiconductor layer must be purged in the chamber after the formation of the semiconductor layer. Plasma nitridation in the gas mixture atmosphere eliminates the need to purge the gas used in the formation of the semiconductor layer, which shortens the processing time.

(Ii) thermal nitriding process

Thermal nitriding processes are typically used in nitriding because of the good uniform electrodeposition of the membranes obtained. Specifically, the heating is preferably performed at a temperature of 400 ° C. or lower, for example, in a nitrogen gas atmosphere, as described in Experimental Example 2 described later. Excessively high heating temperatures can increase damage to the semiconductor layer. In contrast, excessively low heating temperatures may not provide enough of the desired nitrogenous layer. It is more preferable that heating temperature is 200 degreeC or more and 380 degrees C or less, and still more preferably 250 degreeC or more and 350 degrees C or less. The heat treatment (thermal nitriding process) may be performed in combination with a plasma nitriding process, as described in Experimental Example 3 described later. This further accelerates the formation of the nitrogenous layer.

(Iv) Amination Process

The amination process accelerates the decomposition or reaction of gases by the action of light to form nitrogen-containing layers. Light of a wavelength in the ultraviolet region (about 200 nm to 400 nm) is generally used. The light source may be a mercury lamp such as a low pressure mercury lamp with a wavelength of 254 nm or a high pressure mercury lamp with a wavelength of 365 nm; Or an excimer laser system such as an ArF laser of 194 nm wavelength or a KrF laser of 248 nm wavelength. More specifically, the amination is preferably carried out using ultraviolet radiation of shorter wavelengths in the nitrogen-containing gas, as described in Experimental Example 4 described later. This realizes the use of more energy in the amination.

The amination process is typically carried out using a nitrogen containing solution containing amino groups. Nitrogen can be applied to the semiconductor layer more efficiently by applying ultraviolet radiation while contacting the nitrogen-containing liquid with the semiconductor layer. In Experimental Example 4 to be described later it can be seen the specific procedure.

As described above, the nitrogen-containing layer is preferably formed by one or more of the processes (i) to (iii). The system (apparatus), chamber, temperature, and gas composition for the formation of the nitrogenous layer are preferably defined or selected as follows to simplify the manufacturing process and shorten the treatment time.

With regard to the system, in order to simplify the manufacturing process, the formation of the nitrogenous layer is preferably performed in the same system as the deposition system for the formation of the semiconductor layer, more preferably in the same chamber of the same system as the formation of the semiconductor layer. Do. This eliminates the movement of additional work between systems or within one system.

Regarding the temperature, the formation of the nitrogenous layer is preferably carried out at a temperature substantially the same as the deposition temperature of the semiconductor layer, that is, within ± 10 ° C of the deposition temperature of the semiconductor layer. This saves additional time for adjusting the temperature.

The gas used herein may be a single nitrogen containing gas such as N ₂ , NH ₃ , or NF ₃ , but more preferably a gas mixture of this nitrogen containing gas and the material gas (SiH ₄ ) used to form the semiconductor layer. desirable. When the nitrogenous layer is formed using only nitrogenous gas, the gas used to form the semiconductor layer must be purged from the chamber after the formation of the semiconductor layer. Nitriding in the gas mixture atmosphere eliminates the need for purging the gas used to form the semiconductor layer and shortens the processing time.

Alternatively, the gas is preferably a mixture of nitrogenous gas and reducing gas. This more effectively prevents oxidation of the semiconductor layer. Examples of the reducing gas include NH ₃ and H ₂ . Among these gases, NH ₃ serves not only as a reducing gas but also as a nitrogen containing gas, and may be used alone or in combination with, for example, H ₂ .

After forming the nitrogen-containing layer on the thin film transistor semiconductor layer, an aluminum alloy film is typically formed by a sputtering process to yield the desired source / drain wiring. The source / drain electrodes according to the present invention can be formed using a single sputtering target and a single sputtering gas, and there is no need to change the composition of the sputtering gas as in the above-mentioned Japanese Patent Laid-Open Publication No. 2003-273109. Therefore, the present invention can further simplify the manufacturing method.

One of the main features of the source / drain electrodes according to the present invention is that a nitrogenous layer is disposed between the thin film transistor semiconductor layer and the aluminum alloy layer so as to cover the semiconductor layer. Thus, the types of aluminum alloy and semiconductor layers are not particularly limited, and those generally used in the source / drain electrodes may be used as long as they do not adversely affect the thin film transistor characteristics. Representative examples of the semiconductor layer include amorphous silicon and polycrystalline silicon. The aluminum alloy may be a commonly used aluminum material such as, for example, pure aluminum or aluminum alloy containing silicon, copper, or a rare earth element such as Nd or Y as the alloying element.

The aluminum material for wiring of the source / drain electrodes according to the first embodiment may be a conventional unprocessed aluminum alloy as described above, but is preferably an Al-Ni alloy containing 6 atomic% or less nickel. Do. This configuration also realizes properties equivalent to those of the thin film transistors of the conventional aluminum alloy even if the obtained thin film transistor substrate does not use a barrier metal layer. This will be explained in the experimental examples described below. If the Al-Ni alloy contains more than 6 atomic percent nickel, the Al-Ni alloy thin film will have an excessively high electrical resistance. Therefore, the response speed of the pixel is decreased, the power consumption is increased, and the quality of the obtained screen is poor, which may not be suitable for practical use. It is preferable that content of nickel is 5 atomic% or less. The lower limit of the nickel content is not particularly limited in view of thin film transistor characteristics. However, when the Al-Ni alloy thin film is directly connected to the ITO thin film, the Al-Ni alloy preferably contains at least 0.3 atomic% nickel.

The Al-Ni alloy used in the present invention is a group consisting of Ti, V, Zr, Nb, Mo, Hf, Ta, and W (this group is also referred to as "X1 group") as a third component. It may further comprise 0.1 atomic% or more to 1.0 atomic% or less of one or more elements selected from. The alloy obtained is hereinafter also referred to as "Al-Ni-X1 alloy". Alternatively or in addition, the Al—Ni alloys may be selected from the group consisting of Mg, Cr, Mn, Ru, Rh, Pd, Ir, Pt, La, Gd, Tb, Dy, Nd, Y, Co, and Fe (the group is then referred to as “X2” And at least 0.1 atomic percent to at most 2.0 atomic percent of one or more elements selected from the group consisting of " also referred to as " The alloy obtained is hereinafter referred to also as "Al-Ni-X2 alloy". Al-Ni-X1-X2 alloys containing at least one element belonging to group X1 and at least one element belonging to group X2 can be used in the present invention.

One or more elements belonging to groups X1 and X2, if incorporated into the Al-Ni alloy, have a hillock on the surface of the Al-Ni alloy thin film when the Al-Ni alloy thin film is in direct contact with the ITO film. Formation of projections) prevents the reduction of thermal safety. The X1 and X2 groups look at each other in detail. These differences, including their preferred contents, will be explained in detail in the source / drain electrodes according to the second embodiment described below.

The source / drain electrodes according to the first embodiment eliminate the need for interposing a lower barrier metal layer between the aluminum alloy thin film and the thin film transistor semiconductor layer, unlike conventional equivalents. Therefore, the aluminum alloy thin film can be in direct contact with the semiconductor layer through the nitrogenous layer. Sample TFTs using pure aluminum or Al-Ni thin films prepared in the experimental examples described below have characteristics equal to or higher than those of conventional equivalents using conventional aluminum alloy thin films interposed with a barrier metal layer such as a chromium layer. It turns out to be a reality. Therefore, the present invention eliminates the need for a barrier metal layer, thus simplifying the manufacturing process and reducing the production cost.

Source / drain electrodes according to the second embodiment

Each of the source / drain electrodes according to the second embodiment includes a nitrogen-containing layer and an Al—Ni alloy thin film. The source / drain electrode according to the second embodiment has the same configuration as the source / drain electrode according to the first embodiment except for using a specific Al-Ni alloy described below as the aluminum material. Description of the same configuration as the source / drain electrode according to the first embodiment, such as the nitrogen-containing layer, will be omitted here.

Certain Al-Ni alloys enable direct connection between the Al-Ni alloy thin film and the thin film transistor semiconductor layer, and also enable direct connection between the Al-Ni alloy and the transparent pixel electrode. This is probably because an electrically conductive oxide (AlO _x , 0 < _x ≦ 0.8) and / or nickel-rich layer is formed at the interface between the Al—Ni alloy and the transparent pixel electrode. This will be described in detail below.

First, an Al-Ni alloy used in the source / drain electrodes according to the second embodiment is described.

The Al-Ni alloy used here contains nickel of 0.3 atomic% or more and 6 atomic% or less. The lower limit (0.3 atomic%) of the nickel content is mainly set in view of reducing contact resistivity at the interface between the Al-Ni alloy thin film and the transparent pixel electrode and ensuring satisfactory thermal stability.

When the nickel content of the source / drain electrodes according to the second embodiment is less than 0.3 atomic%, the contact resistivity at the interface slightly increases and the thermal stability decreases. When the nickel content exceeds 6 atomic%, the Al-Ni alloy thin film may have an excessively high electrical resistance. Therefore, the response speed of the pixel is decreased, the power consumption is increased, and the quality of the obtained screen is poor, which is not suitable for practical use. In consideration of these advantages and disadvantages, the nickel content is preferably 0.5 atomic% or more and 5 atomic% or less.

It is preferable that Al-Ni alloy further contains at least 0.1 atomic%-1.0 atomic% of 1 or more types which belong to an X1 group as a 3rd component. If the content of one or more elements belonging to group X1 is less than 0.1 atomic%, the activity of these elements may not be effective. In contrast, if the content exceeds 1.0 atomic%, the activity may be increased but the resistivity of the Al-Ni-X1 alloy thin film may increase. In view of these points, the content of at least one element belonging to the X1 group is more preferably 0.2 atomic% or more and 0.8 atomic% or less. Each of these elements may be used alone or in combination. When used in combination, the total content of elements must be within the range specified above.

Alternatively, or in addition, the Al-Ni alloy may further include, as a third component, one or more elements belonging to the group X2 in an amount of 0.1 atomic% or more and 2.0 atomic% or less. This effectively prevents a decrease in thermal stability due to the formation of hillocks (lumps) on the surface of the Al—Ni alloy thin film, as in the Al—Ni—X 1 alloy. If the content of at least one element belonging to the X2 group is less than 0.1 atomic%, its activity may not be effective. However, if the content exceeds 2.0 atomic%, although its activity is increased, the resistivity of the Al—Ni—X 2 alloy thin film may increase. In view of these points, the content of at least one element belonging to the X2 group is more preferably 0.3 atomic% or more and 1.8 atomic% or less. Each of these elements may be used alone or in combination. When used in combination, the total content of elements must be within the range specified above.

The Al-Ni alloy used in the present invention may be an Al-Ni-X1-X2 alloy including both one or more elements belonging to the X1 group and one or more elements belonging to the X2 group.

The elements belonging to the X1 and X2 groups are selected in view of the thermal stability and the electrical resistivity of the obtained Al-Ni-X1 alloy thin film or Al-Ni-X2 alloy thin film. Groups X1 and X2 differ in mechanisms that contribute to thermal stability. This will be described in detail with reference to FIG. 8 below.

8 is a diagram schematically showing how the stress of an aluminum thin film changes with temperature. In FIG. 8, the symbols "A", "B", and "C" each represent pure aluminum data, Al-X2 alloy data including elements belonging to group X2, and Al-X1 alloys containing elements belonging to group X1. Display the data.

8 shows that the compressive stress increases at a temperature at which the Al-X2 alloy film "B" containing an element belonging to the X2 group rises. Particle growth is suppressed in the early stages of temperature rise, but starts at a relatively low temperature, and stress is noticeably relieved at a narrow range of temperatures. This is probably because the dissolved elements contained in the alloy precipitate as intermetallic compounds, which accelerates the grain growth of aluminum and reduces the electrical resistivity. In particular, the electrical resistivity is significantly reduced at relatively low heating temperatures. However, when the thin film is further heated in a state where the stress is completely relaxed, compressive stress occurs in the thin film, thereby causing, for example, the formation of a hillock. The heat resistance temperature of the alloy will probably be close to the temperature at which the stress is relaxed.

The Al-X1 alloy film "C" containing elements belonging to the X1 group increases the compressive stress with increasing temperature as in the Al-X2 alloy film "B", and the grain growth of aluminum is increased in the Al-X2 alloy film. Starts at a temperature similar to However, elements belonging to the X1 group diffuse out of the solid solution and precipitate as intermetallic compounds at a relatively low rate. Therefore, as illustrated in FIG. 8, the intermetallic compound gradually precipitates at a wide range of temperatures, and the stress gradually relaxes with precipitation. Therefore, the stress is sufficiently relaxed, most of the dissolved elements are precipitated as intermetallic compounds, and a lot of heating and a long time are required before the grain growth of aluminum proceeds and the matrix of the film has sufficiently reduced electrical conductivity. This increases the thermal stability. Specifically, the elements belonging to the X1 group are more slowly precipitated as intermetallic compounds, which may increase the thermal stability more effectively and exhibit sufficient advantages of improving the thermal stability in a smaller amount than the elements belonging to the X2 group. .

Therefore, the elements belonging to the X1 group and the elements belonging to the X2 group are different in a mechanism showing thermal stability, and therefore, the content (the upper limit of the content) is different.

As demonstrated in the experimental examples described below, the elements belonging to the X1 group can reduce the contact resistivity to a target level in a smaller amount than the elements belonging to the X2 group. This activity is also observed when the membrane is treated at relatively low heating temperatures.

In addition, the elements belonging to the X1 group prevent the formation of voids in the electrode film as compared with the elements belonging to the X2 group, although the content of the elements belonging to the X1 group should be set less than the contents of the elements belonging to the X2 group. . Specifically, when an element which rapidly precipitates as an intermetallic compound at a narrow range of temperatures is used, such as an element belonging to the X2 group, when the film is cooled to room temperature after heating, grain growth proceeds and stronger tensile stress is achieved. This occurs in the membrane. Tensile stress can form voids. In contrast, in an alloy system in which the intermetallic compound is slowly precipitated over a long period of time, such as an element belonging to the X1 group, the alloy is heated to the same temperature as in the X2 group, and the stress is not sufficiently relaxed. When the membrane is cooled to room temperature, precipitation and grain growth stop when a small amount of tensile stress remains on the membrane. Therefore, the elements belonging to the group X1 are preferably selected from the viewpoint of preventing the voids caused by the tensile stress.

Next, an oxide formed at the interface between the Al—Ni alloy thin film and the transparent pixel electrode (AlO _x , where _x satisfies the following condition: 0 < _x ≦ 0.8) will be described.

The oxide AlO _x contains less oxygen and is therefore more electrically conductive than Al ₂ O ₃ having a stoichiometric composition. This contributes to the reduction in contact resistivity without the barrier metal layer. Specifically, when the conventional aluminum wiring material is in direct contact with the transparent pixel electrode without intervening the barrier metal layer, a thick film containing oxygen in substantially the same amount as Al ₂ O ₃ and having a high resistivity is formed at the interface, which is the contact It causes an increase in resistivity. However, the arrangement according to the present invention can avoid this problem.

The thickness of the oxide AlO _x is preferably about 1 to 10 nm, more preferably about 2 to 8 nm, even more preferably about 5 nm.

The electrically conductive oxide film (AlO _x ) is preferably formed using a deposition process comprising two or more steps. For example, initially, the ITO film for constituting the transparent pixel electrode is sputtered at a substrate temperature of preferably about 100 ° C. to 200 ° C. using a non-oxidizing gas such as argon gas, so that it is about 5 to 20 nm, preferably Is formed to a thickness of about 10 nm. During this procedure, i.e., in the initial stage of formation of the ITO film constituting the transparent pixel electrode, the film formation is preferably performed in an oxygen-free atmosphere to avoid oxidation of the surface of the Al-Ni alloy thin film. When the film formation is carried out in an oxygen free atmosphere in this manner, the ITO film formed by sputtering contains less oxygen and thus reduces the electrical conductivity of the ITO film itself. However, the reduction in electrical conductivity increases the crystallinity of ITO as a result of this heating, and can therefore be offset by adequate heating of the substrate during this process.

Next, the atmosphere gas is changed from non-oxidizing gas to an oxygen-containing gas containing non-oxidizing gas and oxygen gas, and the film is, for example, about 20 nm to 200 nm, preferably about 40 nm thick while the temperature of the substrate is maintained. Is formed. Here, the oxygen content of the atmosphere gas is not particularly limited, but for example, the oxygen partial pressure is set to 10 to 50 μTorr, preferably about 20 μTorr, for an argon pressure of about 1 to 5 mTorr, preferably about 3 mTorr. It is preferable. The inventors have shown experimentally that the electrical resistivity of the formed ITO film is minimized to about 1 × 10 ⁻⁴ Ωcm ² under these conditions. This same advantage can be obtained by adding steam to the atmosphere gas instead of oxygen. Therefore, the ITO film itself has sufficiently high electrical conductivity while preventing the oxidation of the aluminum alloy film in the initial stages of the formation of the ITO film by forming the ITO film by two or more steps of sputtering while changing the oxygen content of the atmosphere gas. Can be.

Next, a nickel-rich layer formed at the interface between the Al-Ni alloy thin film and the transparent pixel electrode will be described. The nickel-rich layer is electrically conductive as in AlO _x films and contributes to the reduction in contact resistivity.

The average nickel concentration of the nickel-concentrated layer is preferably two times or more, and more preferably 2.5 times or more of the average nickel concentration of the Al-Ni alloy. The thickness of the nickel-concentrated layer is preferably 0.5 nm or more and 10 nm or less, and more preferably 1.0 nm or more and 5 nm or less.

The sample TFT manufactured using a specific Al-Ni alloy thin film is the same as or similar to a conventional TFT using a conventional aluminum alloy thin film interposed with a barrier metal layer such as a chromium layer, as demonstrated in the experimental examples described below. It has been found to realize higher thin film transistor characteristics, contact resistivity, and thermal stability. Thus, the source / drain electrodes according to the second embodiment of the present invention eliminate the need for a barrier metal layer, thus simplifying the manufacturing process and reducing the manufacturing cost. In addition, the source / drain electrodes sufficiently reduce the electrical resistivity at relatively low heating process temperatures of about 200 ° C., allowing a wider range of types and process conditions for the display device material to be selected.

First embodiment

Specific preferred embodiments of the thin film transistor substrate according to the present invention are described below with reference to the accompanying drawings. This preferred embodiment will be described by taking a liquid crystal display device including an amorphous silicon thin film transistor substrate as a representative example. The following is merely presented by way of example only, and not intended to limit the scope of the invention, it is noted that various modifications and variations are possible in the present invention without departing from the teachings and scope of the invention. The inventors have experimentally applied source / drain electrodes according to the invention to TAB connection electrodes for input and output of, for example, reflective electrodes and signals from and to and from external sources for reflective liquid crystal display devices. Proved to be possible.

An embodiment of an amorphous silicon thin film transistor substrate according to the present invention will be described in detail with reference to FIG. 3.

3 is a schematic diagram illustrating a preferred embodiment of the thin film transistor substrate according to the present invention. In FIG. 3, components corresponding to the conventional thin film transistor substrate of FIG. 2 use the same reference numerals.

Referring to FIG. 3, the source electrode 28 and the drain electrode 29 are electrically connected to the source / drain wiring 34. Source / drain connection 34 includes a nitrogen-containing layer (not shown) and an Al-2.0 atomic% Ni alloy film (not shown), wherein the nitrogen-containing layer is disposed to cover the channel amorphous silicon thin film. . The configuration of the source / drain wiring 34 will be described in detail in FIGS. 4E and 4F below.

Comparing FIGS. 2 and 3, a conventional thin film transistor substrate includes a lower barrier metal layer 53 and an upper barrier metal layer 54, typically molybdenum, above and below the source / drain electrodes (FIG. 2). It is shown that the thin film transistor substrate according to the present invention does not include the lower barrier metal layer 53 (FIG. 3). In addition, as demonstrated in the following experimental example, the present invention also eliminates the need to arrange the top barrier metal layer 54.

In this embodiment, unlike conventional equivalents, a direct connection between the aluminum alloy and the channel amorphous silicon thin film is possible through the nitrogenous layer without intervening the lower barrier metal layer. As a result, excellent thin film transistor characteristics equivalent to or higher than those of conventional thin film transistor substrates are obtained (see Experimental Examples 1 and 2 below). Further, in another embodiment of the present invention, unlike conventional equivalents, a direct connection between the aluminum alloy and the transparent pixel electrode is possible without intervening the upper barrier metal layer. As a result, excellent thin film transistor characteristics corresponding to or higher than those of conventional thin film transistor substrates are obtained (see Experimental Example below).

As a result, the present invention eliminates the need for upper and lower barrier metal layers that are essential for conventional wiring.

Next, a method of manufacturing the thin film transistor substrate shown in FIG. 3 according to the present invention will be described with reference to FIGS. 4A to 4G. The parts in FIG. 4 corresponding to the parts in FIG. 3 used the same reference numerals.

First, an aluminum alloy thin film (Al-2.0 atomic% Nd) 61 having a thickness of about 200 nm and a molybdenum thin film 52 (not shown) having a thickness of about 50 nm were deposited on the glass substrate 1a by sputtering. It was formed sequentially (FIG. 4A). Film formation by sputtering was performed at room temperature. The resist 62 pattern is formed on the multilayer thin film by photolithography (FIG. 4B), and the multilayer film including the aluminum thin film 61 and the molybdenum thin film 52 is formed using the patterned resist 62 as a mask. It was etched to form a gate electrode 26 (FIG. 4C). In this process, it is desirable to improve the coating force of the gate insulator 27 to be formed by being tapered around the multilayer thin film at an angle of about 30 ° to about 60 °.

Then, a silicon nitride film (gate insulator) 27 having a thickness of about 300 nm was typically formed by plasma CVD (FIG. 4D). Film formation by plasma CVD was performed at a temperature of about 350 ° C. On the silicon nitride film (gate insulator) 27 is an undoped hydrogenated amorphous silicon film (a-Si-H) 55 having a thickness of about 200 nm, and a phosphorus-doped typically about 80 nm thick by plasma CVD. An n ⁺ -type hydrogenated amorphous silicon film (n ⁺ a-Si-H) 56 was formed sequentially. An n ⁺ -type hydrogenated amorphous silicon film was formed by performing plasma CVD using SiH ₄ and PH ₃ as materials.

Subsequently, a nitrogen-containing layer 60 was formed in the n ⁺ -type hydrogenated amorphous silicon film (n ⁺ a-Si-H) 56 in the chamber of the plasma CVD system used to form the silicon nitride film (FIG. 4E). Specifically, the material gas used to form the amorphous silicon film is discharged from the chamber while the substrate is held in the chamber. Next, the surface of the n ⁺ -type hydrogenated amorphous silicon film 56 was plasma treated for 3 minutes, while plasma was generated while nitrogen gas alone was injected into the chamber as a carrier gas. Thus, the nitrogenous layer 60 is formed. Plasma treatment was performed at a high frequency power density of 0.24 W / cm 2, a deposition temperature of 320 ° C., and a gas pressure of 67 Pa. The surface of the workpiece was analyzed by RSB and XPS to confirm that the nitrogenous layer was formed to a thickness of about 5.8 nm.

The nitrogenous layer 60 was formed by a plasma nitridation process in this embodiment. However, the process of forming such a layer is not limited to this, and a preferable nitrogen-containing layer may also be formed by the above-mentioned (ii) thermonitridation process and (iii) amination process as demonstrated in the following experimental example ( See Experimental Examples 1 to 4 below).

Then, an Al-2.0 atomic% Ni alloy film 63 having a thickness of about 300 nm was formed on the nitrogen-containing layer 60 by sputtering typically (FIG. 4F). Film formation by sputtering was performed at room temperature. Next, a pattern of the resist is formed by photolithography, and the Al-2.0 atomic% Ni alloy film 63 is etched using the patterned resist as a mask to form the source electrode 28 and the drain electrode 29. (FIG. 4F). The n ⁺ -type hydrogenated amorphous silicon film 56 was stripped by dry etching using the source electrode 28 and the drain electrode 29 as a mask (FIG. 4G).

A silicon nitride film (protective film) (not shown) was typically formed at a thickness of about 300 nm in a plasma nitride system. Film formation was performed here at the temperature of about 200 degreeC. Thereafter, a resist pattern was formed on the silicon nitride film 30 and processed by dry etching, for example, to form the contact holes 57.

An ashing step, typically using an oxygen plasma, was then performed, and the photoresist layer (not shown) was stripped using a remover containing, for example, an amine. An ITO film (indium oxide further containing 10% by mass of tin oxide) was formed to a thickness of about 50 nm. Then, pattern formation by wet etching was performed to obtain a transparent pixel electrode 5. Thus, a thin film transistor substrate was completed.

In the thin film transistor substrate according to the present embodiment, the Al—Ni alloy thin film is directly connected to the channel amorphous silicon thin film through the nitrogen containing layer and also directly to the ITO film.

Here, the transparent pixel electrode 5 is an ITO film but may be an IZO film. Instead of amorphous silicon, film silicon (polycrystalline silicon) can be used as the active semiconductor layer.

The liquid crystal display device shown in FIG. 1 is produced using the thin film transistor substrate produced | generated above by the following method, for example.

First, the alignment layer was formed by applying, for example, a film of polyimide to the thin film transistor substrate 1, drying the film and rubbing it.

In the case of the opposing board | substrate 2, the light shielding film 9 is formed on a glass substrate by patterning chromium as a matrix, for example. Then, red, green, and blue dendritic color filters 8 are formed in the gaps in the matrix light shielding film 9. A transparent conductive film such as an ITO film is formed as the common electrode 7 on the light shielding film 9 and the color filter 8. Thus, the counter electrode is provided. Next, for example, a polyimide film is applied to the uppermost layer of the counter electrode, and the resulting film is dried and rubbed to form the alignment layer 11.

Thereafter, the thin film transistor substrate 1 and the opposing substrate 2 are disposed so that the alignment layer 11 of the opposing substrate 2 and the TFT of the thin film transistor substrate 1 face each other. A sealing material 16 such as resin is used to bond the two substrates except for the charging port for the liquid crystal. In this process, the distance (gap) between the thin film transistor substrate 1 and the opposing substrate 2 is kept substantially constant, for example, by inserting the spacers 15 therebetween.

The empty cell thus formed is placed under vacuum, and the liquid crystal material is filled to form a liquid crystal layer by gradually increasing the pressure to atmospheric pressure while the filling port is immersed in the liquid crystal material. Thereafter, the filling port is sealed. Finally, the polarizing plate 10 was attached to both sides of the cell to complete the liquid crystal display panel.

Then, the drive circuit 13 is electrically connected to the liquid crystal display panel, and is disposed on the side or the rear surface of the liquid crystal display panel to drive the liquid crystal display device. A frame 23 having an opening that serves as a screen of the liquid crystal display panel, a light distribution member 22 and another frame 23 as a planar light source are arranged so that the liquid crystal display panel is held to complete the liquid crystal display device.

Example

As in the present invention, the experiments of Experimental Examples 1 to 5 were conducted to demonstrate that excellent thin film transistor characteristics can be obtained without using a barrier metal layer by using a source / drain electrode containing a nitrogen-containing layer. Methods of measuring these experimental conditions and properties are described below.

Source / Drain Electrodes

A source / drain electrode according to the first embodiment was used in Experimental Examples 1 to 4 using an Al-2.0 atomic% Ni alloy. A source / drain electrode according to the first embodiment was used in Experiment 5 except that pure aluminum was used instead of Al-2.0 atomic% Ni alloy. Only the method of forming the nitrogen-containing layer for the source / drain electrodes is different from each other in Experimental Examples 1 to 4. Specifically, the nitrogen-containing layer was formed by the plasma nitriding process described in detail in the first embodiment in Experimental Example 1, by the thermal nitriding process in Experimental Example 2, and by the amination process in Experimental Examples 3 and 4.

Experimental Example 1

A thin film transistor was manufactured according to the procedure of the first embodiment.

Experimental Example 2

A thin film transistor was manufactured by the procedure of the first embodiment except that the nitrogen-containing layer was formed by the following method.

First, an n ⁺ -type hydrogenated amorphous silicon film (n ⁺ a-Si-H) 56 was formed according to the procedure of the first embodiment. Next, heating was performed for 30 minutes using nitrogen as a carrier gas at 350 ° C. in the plasma nitriding system used for formation of the silicon nitride film. The surface of the workpiece after heating was analyzed by the procedure of the first embodiment to confirm that the nitrogenous layer was formed to a thickness of about 6 nm.

Experimental Example 3

A thin film transistor was manufactured by the procedure of the first embodiment except that the nitrogen-containing layer was formed by the following method.

First, an n ⁺ -type hydrogenated amorphous silicon film (n ⁺ a-Si-H) 56 was formed by the procedure of the first embodiment. Next, the film was placed in an ultraviolet irradiator, and ultraviolet rays having a wavelength of 254 nm were applied for 60 minutes while injecting nitrogen gas into the ultraviolet irradiator. The surface of the workpiece after heating was analyzed by the procedure of the first embodiment to confirm that the nitrogenous layer was formed to a thickness of about 3 nm.

Experimental Example 4

A thin film transistor was manufactured by the procedure of the first embodiment except that the nitrogen-containing layer was formed by the following method.

First, an n ⁺ -type hydrogenated amorphous silicon film (n ⁺ a-Si-H) 56 was formed by the procedure of the first embodiment. The membrane was then immersed in 1% by volume aqueous ammonia solution and then ultraviolet light at a wavelength of 254 nm was applied to the surface of the workpiece for 60 minutes. The surface of the workpiece after heating was analyzed by the procedure of the first embodiment to confirm that the nitrogenous layer was formed to a thickness of about 2 nm.

Experimental Example 5

A thin film transistor was prepared by the procedure of the first embodiment except that pure aluminum was used instead of the Al-2.0 atomic% Ni alloy.

TFT specimen

The TFT prepared above having the configuration as shown in FIG. 4G of the first embodiment was annealed at 300 ° C. for 30 minutes. The film was used as a specimen to easily and conveniently measure the characteristics of the thin film transistor. The annealing conditions here were set to simulate heat treatment in the film forming step of the silicon nitride film (protective film) so as to calculate the maximum thermal history. Although the TFT specimens used in this experiment did not completely perform various deposition steps as in the actual thin film transistor substrate, the TFT specimens after annealing are considered to have characteristics that substantially reflect the characteristics of the actual thin film transistor substrate. .

Interdiffusion Assessment Between Silicon and Aluminum

On the TFT specimens, the interface between the channel amorphous silicon thin film and the Al-Ni alloy or pure aluminum was observed to detect whether interdiffusion occurred between silicon and aluminum. Specifically, the interface was observed at a magnification of 60 × 10 ⁴ under a cross-sectional transmission electron microscope (cross section TEM), and the interdiffusion at the interface between silicon and aluminum was quantitatively determined by an energy dispersive X-ray fluorescence spectrometer (EDX). Analyzed.

Measurement of Thin Film Transistor Characteristics

The switching behavior on the drain current-gate voltage of the TFT specimens was measured. Interdiffusion between silicon and aluminum can also be indirectly assessed by this property. In this procedure, the leakage current (drain current when a negative voltage is applied to the gate voltage; off-state current) when the thin film transistor is turned off and the on-state flowing when the thin film transistor is turned on The current was measured by the following method.

Drain current and gate voltage were measured using a TFT specimen having a gate length (L) of 10 μm, a gate width (W) of 100 μm, and a ratio of gate width to gate length (W / L) of 10. . In the measurement, the drain voltage was adjusted to 10V. Here, the off-state current is defined as the current when the gate voltage of -3 V is applied, and the on-state current is defined as the voltage when the gate voltage reaches 20V.

The measured thin film transistor characteristics were evaluated in the following manner with the thin film transistor characteristics of Comparative Sample 1 as reference values. As Comparative Sample 1, a thin film transistor was manufactured using a source / drain electrode including a pure aluminum thin film and a chromium barrier metal layer, and the characteristics of the TFTs were measured. In the TFT according to Comparative Sample 1, the on-state current was 1.2 x 10 ^-5 A and the off-state current was 4.0 x 10 ^-13 A. These values were taken as baseline. Specimens with off-state currents of less than 10 times the reference value (below 4.0 × 10 ^-12 A) were rated as “good” and specimens with off-state currents higher than this range were “bad” (not good). Not evaluated). At on-state currents, specimens with on-state currents of 20% or less (9.6 × 10 ^-6 A or less) of the reference value were rated as “excellent” and those with on-state currents outside of this range were “ Poor ".

result

5 is a cross-sectional transmission electron photograph of a specimen according to Experimental Example 1. 5 demonstrates that a nitrogenous layer (nitride layer) was formed near the interface between the Al—Ni alloy thin film and the channel amorphous silicon thin film at the source / drain electrode. Bright portions indicated by arrows in FIG. 5 are precipitated Al ₃ Ni particles.

The interface was analyzed by EDX to confirm that the interface was smooth without interdiffusion between silicon and aluminum.

The same results were also observed in the specimens according to Experimental Examples 2 to 5, but photographs of these specimens were omitted.

The thin film transistor characteristics of the specimens according to Comparative Sample 1 and Experimental Examples 1 to 5 are described in Table 1 below.

From Table 1, it can be seen that the TFTs according to Experimental Examples 1 to 5 have excellent thin film transistor characteristics substantially the same as those of Comparative Sample 1 (typical equivalents) regardless of the process of forming the nitrogen-containing layer.

This result can be effectively prevented by using the source / drain electrodes according to the first embodiment, interdiffusion between silicon and aluminum at the interface between the channel amorphous silicon thin film and the aluminum alloy film even without the lower barrier metal layer, It shows that thin film transistor characteristics can be realized.

Comparison sample 2

In this connection, although the AlN layer was formed as a lower layer of the pure aluminum thin film by the method of JP 2003-273109 A, the aluminum thin film was double layered. Therefore, the thin film transistor characteristics of this specimen were not measured. The bilayer of the aluminum thin film was probably caused because the AlN layer was formed only as the bottom layer of the aluminum thin film, resulting in intensive stress on the aluminum alloy.

Experimental Example 6

Except that the conditions (plasma irradiation time) of the plasma nitriding process were changed as shown in Table 2, a series of TFT specimens were prepared according to the procedure of Experimental Example 1, and the characteristics of the TFTs were evaluated by the procedure of Experimental Example 1. It was. In Table 2, data on the thickness of the nitrogen-containing layer, the N / Si ratio (number of nitrogen atoms / number of silicon atoms) and surface density of nitrogen were measured by the above method.

Comparison sample 3

TFT specimens were prepared as comparative samples according to the procedure of Experimental Example 1 except that no nitrogen-containing layer was formed. Next, the interface between the channel amorphous silicon thin film and the Al-Ni alloy thin film was observed for the TFT specimens, and the characteristics of the thin film transistor were evaluated according to the procedure of Experimental Example 1.

6 is a cross-sectional transmission electrophotograph of a specimen according to Comparative Sample 3. FIG. FIG. 6 shows that many voids (indicated by arrows in FIG. 6) are observed in Al—Ni alloy thin films and channel amorphous silicon thin films at the source / drain electrodes. This indicates that interdiffusion between aluminum and silicon occurs frequently at the interface. Analyzing the interface by EDX showed significant interdiffusion between silicon and aluminum.

The properties of the TFT specimens according to Experimental Example 6 (Sample Nos. 3 to 9) and Comparative Sample 3 (Sample No. 2) are listed in Table 2. Table 2 also describes the results of Comparative Sample 1 (Sample No. 1) in Table 1.

In Table 2, Sample Nos. 4 to 7 and 9 are samples of the present invention that satisfy the preferred conditions in the present invention, Sample No. 2 is a comparative sample without a nitrogenous layer, and Sample Nos. 3 and 8 are preferred of the present invention. Reference sample that does not satisfy the condition. Among the samples of the present invention, sample numbers 4 to 7 each comprise an Al—Ni alloy layer, and sample number 9 comprises a pure aluminum layer.

Table 2 shows that Sample Nos. 4 to 7 have thin film transistor characteristics as good as Sample No. 1 (typical equivalent). These samples are prepared by setting plasma irradiation at about 1 to 10 minutes and appropriately adjusting the thickness of the nitrogen-containing layer, the N / Si ratio (ratio of nitrogen atoms to silicon atoms) and the surface density of nitrogen.

In contrast, sample numbers 2, 3, and 8 show degraded thin film transistor characteristics. Although a detailed explanation for this reason has not been elucidated, Reference Sample 8 thickened the nitrogen-containing layer due to a long plasma irradiation period, causing damage to the channel amorphous silicon thin film, and the amount of oxygen contained in the plasma on the surface of the channel amorphous silicon thin film. It is considered that the characteristics of the thin film transistors are poor because they result in oxidation of silicon.

Experimental Example 7

A thin film transistor sample was prepared except that the nickel content of the Al-Ni alloy was changed as shown in Table 3, and the characteristics of the thin film transistor were measured according to the procedure of Experimental Example 1. The plasma nitridation process was carried out under the same conditions as in Experimental Example 1, but the plasma irradiation time was 3 minutes, and the resulting nitrogen-containing layer had a thickness of about 5.8 nm, a ratio of N / Si of 1.0, and a ratio of 6.8 x 10 ¹⁵ cm ^-2 . It had a surface density of nitrogen.

The results are shown in Table 3.

Table 3 shows that TFT samples using Al-Ni alloy thin films with varying nickel content within 0.1 to 6 atomic percent have excellent thin film transistor characteristics.

Experimental Example 8

As a third component, the procedure of Experimental Example 1, except that La or Nd was incorporated into an Al-2.0 atomic% Ni alloy or an Al-0.1 atomic% Ni alloy and the content of La or Nd was changed as shown in Table 4. The thin film transistor sample was prepared by using the above, and the characteristics of the thin film transistor were measured. The plasma nitridation process was carried out under the same conditions as in Experimental Example 1, but the plasma irradiation time was 3 minutes, the thickness of the resulting nitrogen-containing layer was about 5.8 nm, the ratio of N / Si was 1.0, and the surface density of nitrogen was 6.8. x 10 ¹⁵ cm ^-2 .

The results are described in Table 4.

Table 4 shows TFT samples using Al-Ni-La alloys containing 0.1 to 2.0 atomic% La and TFT samples using Al-Ni-Nd alloys containing 0.1 to 2.0 atomic% Nd. It shows excellent thin film transistor characteristics.

Experimental Example 9

A thin film transistor sample was prepared by the procedure of Experimental Example 1, except that 0.3 atomic% of the optional elements (elements belonging to the X1 group) described in Table 5 were further mixed with the Al-2.0 atomic% Ni alloy as the third component. The thin film transistor characteristics thereof were measured. The plasma nitridation process was carried out under the same conditions as in Experimental Example 1, but the plasma irradiation time was 3 minutes, the thickness of the resulting nitrogen-containing layer was about 5.8 nm, the ratio of N / Si was 1.0, and the surface density of nitrogen was 6.8. x 10 ¹⁵ cm ^-2 .

The results are described in Table 5.

Table 5 shows that TFT samples using Al-Ni-X1 alloys containing elements belonging to the X1 group have excellent thin film transistor characteristics.

Experimental Example 10

A thin film transistor sample was prepared by the procedure of Experimental Example 1, except that 1.0 atomic% of the optional elements (elements belonging to the X2 group) described in Table 6 were further incorporated into the Al-2.0 atomic% Ni alloy as the third component. The thin film transistor characteristics thereof were measured. The plasma nitridation process was carried out under the same conditions as in Experimental Example 1, but the plasma irradiation time was 3 minutes, the thickness of the resulting nitrogen-containing layer was about 5.8 nm, the ratio of N / Si was 1.0, and the surface density of nitrogen was 6.8. x 10 ¹⁵ cm ^-2 .

The results are described in Table 6.

Table 6 demonstrates that TFT samples produced using Al-Ni-X2 alloys containing elements belonging to the X2 group have excellent thin film transistor characteristics.

In order to measure how thin film transistor characteristics change with the ratio of the surface density (N1) of nitrogen to the surface density (O1) of oxygen (N1 / O1) in the nitrogen-containing layer, the conditions for forming the nitrogen-containing layer (gas pressure, deposition temperature and Experimental Examples 11 to 13 were carried out while changing the gas composition) as follows.

Experimental Example 11

It was measured how the ratio of N1 / O1 changed as the pressure varied from 33 to 399 Pa.

Specifically, TFT samples were prepared by the revised method corresponding to the method described in Embodiment 1 above. The method for manufacturing the source / drain electrodes here will be described below with reference to FIGS. 4A-4G as in Embodiment 1.

First, an aluminum alloy thin film (Al-2.0 atomic% Nd) 61 having a thickness of about 200 nm and a molybdenum thin film 52 (not shown) having a thickness of about 50 nm were deposited on the glass substrate 1a by sputtering. It was formed sequentially (FIG. 4A). Film formation by sputtering was performed at room temperature. A resist 62 pattern is formed on the multilayer thin film by photolithography (FIG. 4B), and the multilayer film including the aluminum thin film 61 and the molybdenum thin film 52 is formed using the patterned resist 62 as a mask. It etched to form the gate electrode 26 (FIG. 4C). In this procedure, it is desirable that the periphery of the multilayer thin film is etched in a tapered form at an angle of about 30 ° to about 60 ° to improve the application force of the gate insulator 27 to be formed.

Then, a silicon nitride film (gate insulator) 27 having a thickness of about 300 nm was typically formed by plasma CVD (FIG. 4D). Here, film formation by plasma CVD was performed at a temperature of about 320 ° C. An undoped hydrogenated amorphous silicon film (a-Si-H) 55 having a thickness of about 200 nm on a silicon nitride film (gate insulator) 27, and phosphorus- typically having a thickness of about 80 nm by plasma CVD. A doped n ⁺ -type hydrogenated amorphous silicon film (n ⁺ a-Si-H) 56 was formed sequentially. An n ⁺ -type hydrogenated amorphous silicon film was formed by performing plasma CVD using SiH ₄ and PH ₃ as materials. The film formation temperature was set here to 320 ° C.

Subsequently, a nitrogen-containing layer 60 was formed in the n ⁺ -type hydrogenated amorphous silicon film (n ⁺ a-Si-H) 56 in the chamber of the plasma CVD system used to form the silicon nitride film (FIG. 4E). Specifically, the material gas used to form the amorphous silicon film is discharged from the chamber while the substrate is held in the chamber. Next, the surface of the low resistance amorphous silicon film (n ⁺ -type hydrogenated amorphous silicon film 56) was subjected to plasma treatment for 1 minute, while plasma was generated while nitrogen gas alone was injected into the chamber as a carrier gas. Thus, the nitrogenous layer 60 is formed. Plasma treatment was performed at a film formation temperature of 320 ° C., which was the same as a high frequency power density of 0.72 W / cm 2 and a deposition temperature of the amorphous silicon film.

Plasma treatments were performed at variable pressures ranging from 33 to 399 Pa. However, the plasma was stably generated at a pressure of about 133 Pa or less, and the plasma treated sample at a pressure above 133 Pa was not processed in the subsequent step.

Then, an Al-2.0 atomic% Ni alloy film 63 having a thickness of about 300 nm was formed on the nitrogen-containing layer 60 by sputtering typically (FIG. 4F). Film formation by sputtering was performed at room temperature. Next, a pattern of the resist is formed by photolithography, and the Al-2.0 atomic% Ni alloy film 63 is etched using the patterned resist as a mask to form the source electrode 28 and the drain electrode 29. (FIG. 4F). The n ⁺ -type hydrogenated amorphous silicon film 56 was stripped by dry etching using the source electrode 28 and the drain electrode 29 as a mask (FIG. 4G).

The TFT prepared above was annealed at 300 ° C. for 30 minutes. Here, the annealing conditions were set so as to simulate the heat treatment in the film forming step of the silicon nitride film (protective film) so as to calculate the maximum thermal history. Although the TFT specimens according to the present experimental example did not completely perform various film forming steps as in the actual thin film transistor substrate, the TFT specimens after annealing are considered to have characteristics that substantially reflect the characteristics of the actual thin film transistor substrate.

Measurement of Thin Film Transistor Characteristics

The switching behavior on the drain current-gate voltage of the TFT specimens was measured. In particular, the switching behavior was evaluated by the procedure of Experimental Example 1 by measuring the off-state current and the on-state current.

The thin film transistor characteristics of the TFT sample according to Experimental Example 11 are described in Table 7. A thin film transistor was prepared as a comparative sample by the procedure of Experimental Example 11 except for using a source / drain electrode which was a pure aluminum thin film and a chromium barrier metal layer but was not plasma treated, and the characteristics of the TFT were measured. These results are listed in Table 7 (Sample No. 1).

Table 7 demonstrates the following. Sample Nos. 6 to 11 subjected to a plasma nitridation treatment at a pressure of 55 to 133 Pa so that the N1 / O1 ratio is 1.0 or more have characteristics of excellent thin film transistors substantially the same as Sample No. 1 as a typical sample.

In contrast, plasma nitrided samples No. 3 to 5 and plasma nitridation untreated sample no. 2 at a pressure of 50 Pa or less such that the N1 / O1 ratio is less than 1.0 have poor thin film transistor characteristics.

Among the samples, Sample Nos. 4 and 5, which were subjected to plasma nitridation at a pressure of 40 to 50 Pa, had reduced on-state current. This is probably because the N1 / O1 ratio of the nitrogenous layer is less than 1.0, which is more insulated.

Sample number 3 subjected to plasma nitridation at a pressure of 33 Pa shows both a reduced on-state current and an increased off-state current. This is probably due to insufficient plasma nitridation and interdiffusion between silicon and aluminum failed to provide a layer that effectively acts as a diffusion barrier.

Experimental Example 12

It is measured how the N1 / O1 ratio changes as the plasma treatment temperature changes in the range of 280 ° C to 340 ° C.

Specifically, a TFT sample was prepared according to the procedure of Experimental Example 11 except that plasma nitriding was performed at a pressure of 67 Pa and a variable temperature as described in Table 8, and the thin film transistor characteristics thereof were evaluated.

The thin film transistor characteristics of the TFT sample according to Experimental Example 12 are described in Table 8. A thin film transistor was prepared as a comparative sample by the procedure of Experimental Example 12, except for using a source / drain electrode including a pure aluminum thin film and a chromium barrier metal layer but not subjected to plasma nitridation process, and the characteristics of the TFT were measured. . These results are shown in Table 8 (sample number 1).

Table 8 demonstrates the following. Plasma nitriding samples Nos. 4 to 8 at a temperature of 300 ° C. to 340 ° C. such that the N1 / O1 ratio is 1.0 or more has characteristics of excellent thin film transistors substantially the same as Sample No. 1 as a typical sample.

In contrast, sample numbers 2 and 3 plasma-nitrated at temperatures below 300 ° C. such that the N1 / O1 ratio is less than 1.0 have reduced on-state current and poor film transistor characteristics. This is probably because the nitrogenous layer having an N1 / O1 ratio of less than 1.0 is more insulating.

Experimental Example 13

It is measured how the N1 / O1 ratio varies with the gas composition in plasma nitriding.

Specifically, plasma nitriding process treatment at a pressure of 67 Pa and a temperature of 320 ° C. using only pure gas (sample number 2 in Table 9) and a gas mixture of N ₂ and 25% NH ₃ (sample number 3 in Table 9). Except for that, TFT samples were prepared according to the procedure of Experimental Example 11 and their thin film transistor characteristics were evaluated.

The thin film transistor characteristics of the TFT sample according to Experimental Example 13 are described in Table 9. A thin film transistor was prepared as a comparative sample by the procedure of Experimental Example 13, except for using a source / drain electrode including a pure aluminum thin film and a chromium barrier metal layer but not subjected to plasma nitridation process, and the characteristics of the TFT were measured. . These results are listed in Table 9 (sample number 1).

As demonstrated in Table 9, the thin film transistor sample plasma-nitrided using two different gases shows excellent thin film transistor characteristics. Among these, sample number 3, which is plasma-nitrided using a gas mixture containing reducing gas (NH ₃ ) such that the N1 / O1 ratio is 1.0 or more, is on-state higher than sample number 2 prepared without using reducing gas. It has a current and has excellent thin film transistor characteristics substantially the same as sample number 1 as a comparative sample. This is probably because reducing gas (NH ₃ ) acts to further prevent oxidation of the semiconductor layer.

Experimental Example 14

A TFT sample was prepared by preparing a nitrogen-containing layer in a chamber of the same system as that for forming the semiconductor layer at the same temperature as the deposition temperature of the semiconductor layer, and the thin film transistor characteristics of the TFT sample were measured.

Specifically, TFT samples were prepared by the revised method corresponding to the method described in Experimental Example 11. Here, the method of manufacturing the source / drain electrodes will be described in detail below with reference to FIGS. 4A to 4G.

First, an aluminum alloy thin film (Al-2.0 atomic% Nd) 61 having a thickness of about 200 nm and a molybdenum thin film 52 (not shown) having a thickness of about 50 nm were formed on the glass substrate 1a by sputtering. It was formed sequentially (FIG. 4A). Film formation by sputtering was performed at room temperature. The resist 62 pattern is formed on the multilayer thin film by photolithography (FIG. 4B), and the multilayer film including the aluminum thin film 61 and the molybdenum thin film 52 is formed using the patterned resist 62 as a mask. It was etched to form a gate electrode 26 (FIG. 4C). In this procedure, it is desirable to improve the applicability of the gate insulator 27 to be formed by tapering around the multilayer thin film at an angle of about 30 ° to about 60 °.

Then, a silicon nitride film (gate insulator) 27 having a thickness of about 300 nm was typically formed by plasma CVD (FIG. 4D). The film formation by plasma CVD was performed here at a temperature of about 320 ° C. On the silicon nitride film (gate insulator) 27 an undoped hydrogenated amorphous silicon film (a-Si-H) 55 having a thickness of about 200 nm and phosphorus-doped typically about 80 nm in thickness by plasma CVD An n ⁺ -type hydrogenated amorphous silicon film (n ⁺ a-Si-H) 56 was formed sequentially. An n ⁺ -type hydrogenated amorphous silicon film was formed by performing plasma CVD using SiH ₄ and PH ₃ as materials. The film formation temperature was set here to 320 ° C.

The material gas used to form the amorphous silicon film was then discharged from the chamber while the substrate was held in the chamber of the plasma CVD system used to form the silicon nitride film. Next, the surface of the low resistive amorphous silicon film (n ⁺ -type hydrogenated amorphous silicon film) 56 was plasma treated for 1 minute, while plasma was generated while nitrogen gas alone was injected into the chamber as a carrier gas. Thus, the nitrogenous layer 60 is formed (FIG. 4E). Plasma treatment was performed at a high frequency power density of 0.72 W / cm 2, a film formation temperature of 320 ° C. which was the same as the film forming temperature of the amorphous silicon film, and a gas pressure of 67 Pa.

The surface of the workpiece was analyzed by RSB and XPS to confirm that the nitrogenous layer was formed to a depth of about 4.0 nm from the surface. In other words, a nitrogen-containing layer having a thickness of about 4.0 nm was formed on the surface of the amorphous silicon film of low resistance by the method according to Experimental Example 14.

Then, an Al-2.0 atomic% Ni alloy film 63 having a thickness of about 300 nm was formed on the nitrogen-containing layer 60 by sputtering typically (FIG. 4F). Film formation by sputtering was performed at room temperature. Next, a pattern of the resist is formed by photolithography, and the Al-2.0 atomic% Ni alloy film 63 is etched using the patterned resist as a mask to form the source electrode 28 and the drain electrode 29. (FIG. 4F). The n ⁺ -type hydrogenated amorphous silicon film 56 was stripped by dry etching using the source electrode 28 and the drain electrode 29 as a mask (FIG. 4G).

The TFT prepared above was annealed at 300 ° C. for 30 minutes. Here, the annealing conditions were set so as to simulate the heat treatment in the film forming step of the silicon nitride film (protective film) so as to calculate the maximum thermal history. Although the TFT sample according to the present experimental example did not completely perform various film forming steps as in the actual thin film transistor substrate, the TFT sample after annealing is considered to have a characteristic that substantially reflects the characteristics of the actual thin film transistor substrate.

Interdiffusion Assessment Between Silicon and Aluminum

On the TFT samples, the interface between the channel amorphous silicon thin film and the Al-Ni alloy was observed to observe whether interdiffusion occurred between silicon and aluminum. Specifically, the interface was observed at a magnification of 60 × 10 ⁴ , and the interdiffusion between silicon and aluminum at the interface was quantitatively analyzed by an energy dispersive X-ray fluorescence spectrometer (EDX) by the procedure of Experimental Example 1.

Measurement of Thin Film Transistor Characteristics

The switching behavior on the drain current-gate voltage of the TFT sample was measured. Specifically, the switching behavior was evaluated by the procedure of Experimental Example 11 by measuring the off-state current and the on-state current.

result

9 is a cross-sectional transmission electrophotograph of the specimen according to Experimental Example 14. 9 demonstrates that a nitrogenous layer (nitride layer) was formed near the interface between the Al—Ni alloy thin film and the channel amorphous silicon thin film at the source / drain electrode. The dense black portions indicated by arrows in FIG. 9 are precipitated Al ₃ Ni particles.

The interface was analyzed by EDX to confirm that the interface was smooth without interdiffusion between silicon and aluminum.

The off-state current of this sample was 4.0 x 10 ^-13 A, the on-state current was 1.2 x 10 ^-5 A, and showed excellent thin film transistor characteristics substantially the same as in Comparative Sample 1.

Experimental Example 15

In this experimental example, plasma nitridation was carried out in a chamber of the same system for the formation of the semiconductor layer using the gas mixture containing the gas and nitrogen used for the formation of the semiconductor layer. After this procedure, the thin film transistor characteristics were measured.

Specifically, an amorphous silicon film and a low resistive amorphous silicon film having a thickness of about 80 nm were formed by the procedure of Experimental Example 14.

Next, the plasma generation was stopped and the surface of the low-resistance amorphous silicon layer was plasma treated for 10 seconds, while the plasma was continuously injected with material gas (SiH ₄ ) to form the amorphous silicon film and additionally as a carrier gas. Nitrogen gas was generated while being injected into the chamber. Next, plasma nitriding was performed at a high frequency power density of 0.07 W / cm 2, a substrate temperature of 320 ° C., and a gas pressure of 67 Pa. Here, the substrate temperature is the same as the deposition temperature of the amorphous silicon. The surface of the sample was analyzed by RSB and XPS to confirm that the nitrogenous layer was formed to a depth of about 6 nm from the surface. That is, a nitrogen-containing layer having a thickness of about 6 nm was formed on the surface of the low resistance amorphous silicon film by the method according to Experimental Example 15.

Next, a thin film transistor was prepared and annealed by the procedure of Experimental Example 14.

evaluation

In the prepared samples, it was observed and measured whether the interdiffusion between silicon and aluminum occurred at the interface between the channel amorphous silicon thin film and the Al-Ni alloy thin film. Specifically, the interface was observed at a magnification of 60 × 10 ⁴ , and the interdiffusion between silicon and aluminum at the interface was quantitatively analyzed by an energy dispersive X-ray fluorescence spectrometer (EDX) by the procedure of Experimental Example 14.

The switching behavior on the drain current-gate voltage of the TFT sample was measured. Specifically, the switching behavior was evaluated by the procedure of Experimental Example 14 by measuring the off-state current and the on-state current.

result

10 is a cross-sectional transmission electron photograph of a sample according to Experimental Example 15. 10 demonstrates that a nitrogenous layer (nitride layer) was formed near the interface between the Al—Ni alloy thin film and the channel amorphous silicon thin film at the source / drain electrode. The black dense part indicated by the arrow in FIG. 10 is precipitated Al ₃ Ni particles.

The interface was analyzed by EDX to confirm that the interface was smooth without interdiffusion between silicon and aluminum.

The off-state current of this sample was 4.0 x 10 ^-13 A, the on-state current was 1.0 x 10 ^-5 A, and showed excellent thin film transistor characteristics substantially the same as in Comparative Sample 1.

Experimental Example 16

Excellent direct-contact resistance (contact resistance) even when the Al-Ni alloy thin film is in direct contact with the transparent pixel electrode without intervening the barrier metal layer by using a source / drain electrode including the Al-Ni alloy and the nitrogen-containing layer as in the present invention. ) And this experiment was conducted to prove that thermal stability can be calculated.

Specifically, a sample including an ITO film formed on an aluminum alloy thin film in any of the source / drain electrodes and the source / drain electrodes shown in Table 10 was prepared by sputtering at 200 ° C. for 20 minutes in an atmosphere of argon gas at a pressure of 3 mTorr. For example, a source / drain electrode was prepared by subjecting the nitrogen-containing layer to a plasma nitriding process under variable conditions as shown in Table 10. The ITO film contains indium oxide and 10 mass% tin oxide.

In the samples prepared above, direct contact resistance (contact resistivity) and generation of hillocks (thermal stability) were measured by the following method.

Measurement of contact resistivity

A Kelvin pattern having a contact hole size of 10 μm ^{2 shown} in FIG. 7 was generated, and four-terminal measurements were performed. Specifically, two terminals were used to pass a current between the ITO (or IZO) and the aluminum alloy, and the voltage drop between the ITO (or IZO) and the aluminum alloy was measured using the other two terminals. More specifically, current I is passed through I ₁ -I ₂ , the voltage V between V ₁ and V ₂ is measured (FIG. 7), and the direct contact resistivity R of contact C is expressed by the formula R = (V ₂ It was measured by the calculation by -V ₁ ) / I ₂ . Contact resistivity was evaluated as follows. Samples having a contact resistivity of 2 x 10 ^-4 Pa · cm 2 or less were evaluated as having a "excellent" contact rate, using the contact resistivity between the chromium thin film and the ITO film as a reference value (2 x 10 ^-4 Pa.cm 2 or less). Samples with a resistivity greater than 2 × 10 ⁻⁴ Pa · cm 2 were evaluated as having “poor contact” resistivity.

Development of hillocks (thermal stability)

After forming a 10 μm line-and-space pattern on the sample and performing vacuum heat treatment at 250 ° C. for 30 minutes, the surface of the line-and-space pattern as interdiffusion was observed by SEM, and 0.1 μm or less The number of hillocks with a diameter was counted. 1 mm ² per 1 x 10 evaluation samples having a density of hillock of less than ⁹ to be excellent, and the sample having a density of hillock of 1 x 10 ⁹ per 1 mm greater than ² was evaluated as "Bad".

The results are shown in Table 10. The properties of the thin film transistors of the sample as in Table 2 are shown in Table 10. "Overall rating" refers to the overall rating of contact resistivity and thin film transistor characteristics. In the "total grade", samples that were excellent in both contact resistivity and thin film transistor characteristics were evaluated as "good", and inferior at least one of the contact resistivity and thin film transistor characteristics was evaluated as "bad".

In Table 10, Sample Nos. 4 to 7 are samples satisfying the preferred conditions in the present invention, Sample No. 2 is a comparative sample without the nitrogenous layer, and Sample Nos. 3 and 8 are reference samples not satisfying the preferred conditions of the present invention. And sample number 1 is a reference sample comprising a pure aluminum layer as a source / drain electrode.

Table 10 shows that Sample Nos. 4 to 7 have good contact resistivity and thermal stability, as is Sample No. 1 (typical equivalent). These are prepared by setting the plasma irradiation time to about 1 to 10 minutes and appropriately adjusting the thickness of the nitrogen-containing layer, the N / Si ratio (the ratio of the number of nitrogen atoms to the number of silicon atoms) and the surface density of nitrogen. do.

In contrast, the reference samples (sample numbers 3 and 8) were somewhat inferior in character when compared to sample number 1 (comparative samples). In this reference sample, Sample No. 1, which included certain nitrogenous layers and conventional pure aluminum layers, had excellent thin film transistor characteristics, but was inferior in contact resistivity and thermal stability. Thus, no direct contact between this sample and the ITO film was formed.

Experimental Example 17

Samples were prepared according to the procedure of Experimental Example 16 except that the nickel or lanthanum content in the Al-Ni alloy or Al-Ni-La alloy was changed as shown in Table 11, and its contact resistivity and thermal stability were measured. The plasma nitriding process was carried out under the same conditions as in Experiment 16, but the plasma irradiation time was 3 minutes, the thickness of the formed nitrogenous layer was about 5.8 nm, the ratio of N / Si was 1.0, and the surface density of nitrogen was 6.8 x. 10 ¹⁵ cm ^-2 .

The results are shown in Table 11.

Table 11 demonstrates that the contact resistivity of a TFT sample using an Al—Ni alloy thin film having a change in nickel content within a range of 0.1 atomic% to 6 atomic% is excellent. Moreover, Al-Ni alloy thin films and Al-Ni-La alloy thin films having Ni content changed within the range of 0.3 atomic% to 6 atomic% were excellent in terms of thermal stability.

Experimental Example 18

A thin film transistor sample was prepared according to the procedure of Experimental Example 16, except that La or Nd was further incorporated into the Al-2.0 atomic% Ni alloy as the third component and the La or Nd content was changed as shown in Table 12. Its contact resistivity and thermal stability were measured. Plasma nitriding was carried out under the same conditions as in Experimental Example 1, but the plasma irradiation time was 3 minutes, the thickness of the formed nitrogenous layer was about 5.8 nm, the N / Si ratio was 1.0, and the surface density of nitrogen was 6.8 x. 10 ¹⁵ cm ^-2 .

The results are shown in Table 12.

Table 12 shows TFT samples using Al-Ni-La alloys containing 0.1 to 2.0 atomic percent La and TFT samples using Al-Ni-Nd alloys containing 0.1 to 2.0 atomic percent Nd. It has excellent thin film transistor characteristics and shows excellent contact resistivity and thermal stability.

Experimental Example 19

A thin film transistor sample was prepared by the procedure of Experimental Example 16, except that 0.3 atomic% of the optional elements (elements belonging to the X1 group) described in Table 13 were further incorporated into the Al-2.0 atomic% Ni alloy as the third component. The contact resistivity and thermal stability thereof were measured. The plasma nitridation process was carried out under the same conditions as in Experimental Example 1, but the plasma irradiation time was 3 minutes, the thickness of the resulting nitrogen-containing layer was about 5.8 nm, the ratio of N / Si was 1.0, and the surface density of nitrogen was 6.8. x 10 ¹⁵ cm ^-2 .

The results are described in Table 13.

Table 13 shows that TFT samples using Al-Ni-X1 alloys containing elements belonging to the X1 group have excellent thin film transistor characteristics, excellent contact resistivity and thermal stability.

Experimental Example 20

A thin film transistor sample was prepared by the procedure of Experimental Example 16, except that 1.0 atomic% of the optional elements (elements belonging to the X2 group) described in Table 14 were further incorporated into the Al-2.0 atomic% Ni alloy as the third component. The contact resistivity and thermal stability thereof were measured. The plasma nitridation process was carried out under the same conditions as in Experimental Example 1, but the plasma irradiation time was 3 minutes, the thickness of the resulting nitrogen-containing layer was about 5.8 nm, the ratio of N / Si was 1.0, and the surface density of nitrogen was 6.8. x 10 ¹⁵ cm ^-2 .

The results are described in Table 14.

Table 14 shows that TFT samples made using Al-Ni-X2 alloys containing elements belonging to the X2 group have excellent thin film transistor characteristics, contact resistivity and thermal stability.

The invention described above has been described in terms of preferred embodiments. However, those skilled in the art will recognize that there may be many variations of this embodiment. Such modifications also fall within the scope of the invention and claimed claims.

The source / drain electrodes according to the present invention provide the effect of excellent thermal stability, contact resistivity and thin film transistor characteristics without intervening barrier metal layers.

Claims (32)

delete A source / drain electrode used for a thin film transistor substrate comprising a substrate, a thin film transistor semiconductor layer, a source / drain electrode, and a transparent pixel electrode, The source / drain electrode comprises a nitrogen containing layer and a thin film of pure aluminum or aluminum alloy, wherein the nitrogen in the nitrogen containing layer is bonded to silicon in the thin film transistor semiconductor layer, and the thin film of pure aluminum or aluminum alloy is thin film through the nitrogen containing layer. Configured to be connected to a transistor semiconductor layer, The nitrogen-containing layer comprises silicon nitride Source / drain electrodes. A source / drain electrode for a thin film transistor substrate comprising a substrate, a thin film transistor semiconductor layer, a source / drain electrode, and a transparent pixel electrode, The source / drain electrode comprises a nitrogen containing layer and a thin film of pure aluminum or aluminum alloy, wherein the nitrogen in the nitrogen containing layer is bonded to silicon in the thin film transistor semiconductor layer, and the thin film of pure aluminum or aluminum alloy is thin film through the nitrogen containing layer. Configured to be connected to a transistor semiconductor layer, The nitrogen-containing layer comprises silicon oxynitride Source / drain electrodes. A source / drain electrode for a thin film transistor substrate comprising a substrate, a thin film transistor semiconductor layer, a source / drain electrode, and a transparent pixel electrode, The source / drain electrode comprises a nitrogen containing layer and a thin film of pure aluminum or aluminum alloy, wherein the nitrogen in the nitrogen containing layer is bonded to silicon in the thin film transistor semiconductor layer, and the thin film of pure aluminum or aluminum alloy is thin film through the nitrogen containing layer. Configured to be connected to a transistor semiconductor layer, A source / drain electrode having the nitrogen-containing layer having a surface density (N 1) of nitrogen atoms of 1 × 10 ¹⁴ cm ⁻² or more and 2 × 10 ¹⁶ cm ⁻² or less. The method of claim 4, wherein And the nitrogen-containing layer has a surface density (N 1) of a nitrogen atom and a surface density (O 1) of an oxygen atom, and a ratio of N 1 to O 1 (N 1 / O 1) is 1.0 or more. The method of claim 4, wherein And a source / drain electrode having a surface density of nitrogen atoms equal to or greater than the surface density of a silicon effective dangling bond constituting the semiconductor layer. The method according to any one of claims 2 to 4, The source / drain electrode of the nitrogen-containing layer has a thickness in the range of 0.18nm or more to 20nm or less. The method of claim 4, wherein The nitrogen-containing layer has a plurality of nitrogen atoms (N) and a plurality of silicon atoms (Si), the source / drain electrode having a maximum ratio of N to Si (N / Si) in the range of 0.5 to 1.5. The method according to any one of claims 2 to 4, A source / drain electrode wherein the thin film transistor semiconductor layer comprises amorphous silicon or polycrystalline silicon. A source / drain electrode for a thin film transistor substrate comprising a substrate, a thin film transistor semiconductor layer, a source / drain electrode, and a transparent pixel electrode, The source / drain electrode comprises a nitrogen containing layer and a thin film of pure aluminum or aluminum alloy, wherein the nitrogen in the nitrogen containing layer is bonded to silicon in the thin film transistor semiconductor layer, and the thin film of pure aluminum or aluminum alloy is thin film through the nitrogen containing layer. Configured to be connected to a transistor semiconductor layer, The aluminum alloy contains 6 atomic% or less nickel (Ni) as an alloying element. Source / drain electrodes. The method of claim 10, A source / drain electrode, wherein the aluminum alloy contains 0.3 to 6 atomic% nickel (Ni) as an alloy element, and the thin film of the aluminum alloy is additionally directly connected to the transparent pixel electrode. The method of claim 10, Source / drain further comprising at least 0.1 atomic% to 1.0 atomic% of the at least one element selected from the group consisting of Ti, V, Zr, Nb, Mo, Hf, Ta, and W as alloy elements. electrode. The method of claim 10, 0.1 is one or more elements selected from the group consisting of Mg, Cr, Mn, Ru, Rh, Pd, Ir, Pt, La, Gd, Tb, Dy, Nd, Y, Co and Fe as alloy elements. A source / drain electrode further comprising at least 2.0 atomic percent and at most 2.0 atomic percent. A thin film transistor substrate comprising a source / drain electrode according to any one of claims 2 to 4 and 10. A display device comprising the thin film transistor substrate according to claim 14. (a) forming a semiconductor layer on or over the substrate to fabricate a thin film transistor substrate; (b) forming a nitrogen-containing layer on the semiconductor layer; And (c) forming a layer of pure aluminum or an aluminum alloy on the nitrogenous layer, A method of manufacturing a thin film transistor substrate according to claim 14. The method of claim 16, and (b) the semiconductor layer is formed in the film forming system, and step (b) is performed in the same film forming system. The method of claim 16, and (b) the semiconductor layer is formed in a chamber, and (b) is performed in the same chamber. The method of claim 16, in (a), the semiconductor layer is formed at a constant film formation temperature, and (b) is performed at the same temperature as the film formation temperature. The method of claim 16, and (b) the semiconductor layer is formed by the use of a gas, and (b) is performed in a mixed atmosphere of the gas and the nitrogen-containing gas. The method of claim 16, (b) The step of manufacturing a thin film transistor substrate is carried out in a mixed atmosphere of nitrogen-containing gas and reducing gas. The method of claim 16, The method of manufacturing a thin film transistor substrate, wherein step (b) is performed by a plasma nitridation process. The method of claim 22, The plasma nitriding process in step (b) is performed at a pressure of 55 Pa or more and 400 Pa or less. The method of claim 22, The plasma nitriding process in step (b) is carried out at a temperature of 300 ° C or more and 360 ° C or less. The method of claim 22, The plasma nitriding process in step (b) is performed in a mixed atmosphere of a nitrogen-containing gas and a reducing gas. The method of claim 22, and (a) the semiconductor layer is formed by the use of a gas, and the plasma nitridation step (b) is performed in a mixed atmosphere of the gas and the nitrogen-containing gas. The method of claim 16, (b) The manufacturing method of the thin film transistor substrate in which a step is performed by a thermal nitriding process. The method of claim 27, The thermal nitriding process is a method for manufacturing a thin film transistor substrate is carried out at a temperature of 200 ℃ or more to 400 ℃ or less. The method of claim 16, (b) The method of manufacturing a thin film transistor substrate wherein the step is carried out by an amination process. The method of claim 29, A method for producing a thin film transistor substrate, wherein the amination process uses ultraviolet radiation. The method of claim 29, A method for producing a thin film transistor substrate, wherein the amination process uses a solution containing nitrogen atoms. The method of claim 16, and (c) the step comprises sputtering.

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