KR100850773B1 - Image examination module for display device - Google Patents

Abstract

An image evaluation module of a display device is provided to evaluate images of an HD-class display device, an SD-class display device, and a full HD-class display device without using each corresponding image evaluation module with a hardware structure. LVDS output terminals(214a,214b) transmit an image signal to an LVDS device that outputs an image signal to a display device at a high speed. When a dual-function is selected, an FPGA(211) bypasses a dual image signal inputted from the exterior to transmit it in a dual format as it is to the LVDS output terminals. When a quad function is selected, the FPGA converts the dual-image signal inputted from the exterior into a quad image signal format, which is obtained by extending the dual-image signal double, and transmits the same to the LVDS output terminals. When a quad function is selected, memory units(213a,213b) buffer R/G/B data of the dual-image signal inputted from the exterior and provide the same to the FPGA.

Description

Image evaluation module for display device

1 is a diagram illustrating an image evaluation state of a display device.

2 is a block diagram illustrating an internal configuration of an image evaluation module of a display apparatus according to an exemplary embodiment.

3 is a graph illustrating a horizontal synchronous signal and a vertical synchronous signal according to an embodiment of the present invention.

4 is a horizontal synchronous signal (H-sync) output to the LVDS output stage when the FPGA is driven in a dual function according to an embodiment of the present invention, and is output from the FPGA to the LVDS output stage when the FPGA is driven in a quad function This is a graph showing the actual measurement waveform of the horizontal sync signal (H-sync).

* Description of the symbols for the main parts of the drawings *

200: image evaluation module 210: divider

211: FPGA 212: timing generator

213: memory 214: LVDS output terminal

The present invention relates to an image evaluation module of a display apparatus which receives a single / dual data signal of a display apparatus and distributes the single / dual data signal to a single / dual / quad.

Digital display devices, such as liquid crystal displays (LCDs), are used in various electronics and computer products, such as portable televisions, mobile telephones, camcorders, notebook computers, desktop computers, and projection televisions. Used.

1 is a diagram illustrating an image evaluation state of a display device.

A large number of control signals and image data are required to drive the general display apparatus 120 for monitors and notebook computers. Therefore, the control signals and image data as described above must be input to inspect the display apparatus.

In general, the signals for driving the display apparatus 120 include a horizontal synchronous signal (H-sync), a vertical synchronous signal (V-sync), a data enable signal (DE), a clock signal (CLK), and image data (Data). These signals are driven by a timing controller of a circuit part built in the display device 120.

Here, the vertical synchronization signal indicates a synchronization time required to display a screen of one frame, and the horizontal synchronization signal indicates a synchronization time required to display one line of the screen. Accordingly, the horizontal synchronization signal includes as many pulses as the number of pixels included in one line, and the data enable signal indicates a time point at which data is supplied to the pixels.

Referring to FIG. 1, in order to drive the display apparatus 120 using an image evaluation module, that is, a test pattern generator, the horizontal synchronization signal H-sync and the vertical synchronization signal V-. sync, data enable signal DE, clock signal CLK, and R / G / B data, which are image data, are controlled in hardware and transmitted to a timing controller inside the display device, thereby displaying The image quality of the image was evaluated to optimize signal values for driving the display apparatus 120.

However, there is a problem in that the image evaluation module 110 (test pattern generator) of the conventional display device has to be embodied and applied differently according to a method of spreading data. For example, the image evaluation module of the SD display device, which is used to evaluate an SD display device that scatters 720 × 480 screen data 60 times per second, has a structure in which the screen data should be scattered at once. Must have On the other hand, the image of the HD display device used when evaluating the 1080i type HD (high definition) display device which alternately spreads the 1920 × 1080 screen 30 times per second into even and odd lines, respectively. The evaluation module should have a structure in which screen data is to be sprayed alternately on even and odd lines. Similarly, the image evaluation module of a full HD display device should also spray screen data to match the driving of the display device.

Therefore, in order to evaluate images of an HD display device, an SD display device, and a Full HD display device, there is a problem in that an image evaluation module having a separate hardware structure corresponding to the driving method of the display devices must be provided.

The present invention has been made to solve the above problems, and an object of the present invention is to propose an image evaluation module that can be applied to various types of display devices for image evaluation.

Image evaluation of the present invention the module, (A) a high-speed output video signal (horizontal synchronization signal, vertical synchronization signal, R / G / B data, a clock signal, a data enable signal) to the LVDS apparatus for a video signal to the display device At least one LVDS output stage for transmitting; (B) ① If there is a dual function selection, the dual video signal input from the outside bypasses the dual form as it is and transmits to the LVDS output stage. ② If the quad function is selected, double the dual video signal input from the outside. An FPGA for converting into an expanded quad image signal form and transmitting the same to the LVDS output terminal; (C) A memory for buffering and providing R / G / B data in a dual video signal input from an external device according to the FPGA instruction when there is a quad function selection.

The LVDS output stage may include a first LVDS output terminal for spreading an image signal on an odd line (odd) and a second LVDS output terminal for spraying an image signal on an even line (even). In addition, the dual function or quad function operation of the FPGA is performed according to the D / Q selection signal for selecting the dual function or quad function, and when the D / Q selection signal is high, the dual function is set to low. ) Is driven by the quad function.

In addition, when the dual function is selected, the horizontal synchronization signal (H-sync) and the data enable signal (DE) input from the outside are bypassed and transmitted to the LVDS output stage. The FPGA includes a timing generation unit for dividing the horizontal synchronization signal H-sync and the data enable signal DE inputted from the second and transmitting them to the LVDS output terminal. The timing generating unit may maintain a reset state when the timing generator operates in the dual function.

The FPGA may copy the R / G / B data in the dual image signal without timing conversion and R / G / B data buffering of the dual image signal input to the FPGA when the dual function is selected. The same R / G / B data is transmitted to the LVDS output stage, and when the quad function is selected, the R / G / B data is doubled by buffering the R / G / B data in the dual video signal input to the FPGA in memory. Data is transmitted to the LVDS output terminal.

In addition, the memory is divided into at least two recording sectors, and when there is a quad function selection, R / G / B data in dual video signals input to the FPGA are alternately assigned to each recording sector by the instruction of the FPGA. Repeat write-read.

Hereinafter, the detailed description of the preferred embodiments of the present invention will be described with reference to the accompanying drawings. In the following description of the reference numerals to the components of the drawings it should be noted that the same reference numerals as possible even if displayed on different drawings.

2 is a block diagram illustrating an internal configuration of an image evaluation module of a display apparatus according to an exemplary embodiment.

The image evaluation module 200 of the present invention, which is used for image evaluation of a display device, includes a horizontal synchronous signal (H-sync), a vertical synchronous signal (V-sync), and data necessary for expressing colors for inspecting an image of the display device. Bypassing a dual video signal including an enable signal (DE), a clock signal (CLK), and dual 10-bit R / G / B data as image data to a single to single, dual to dual, and dual to quad signals ( A circuit module which bypasses or divides and outputs a dual image signal or a quad image signal to a display device. The dual type video signal is a signal having twice the amount of image information as a normal video signal during display, and the quad type video signal is a signal having four times the amount of image information as a normal video signal.

Hereinafter, an image evaluation module for receiving a dual image signal and outputting the dual image signal or converting the dual image signal into a quad image signal having a double amount of information of the dual image signal Although it will be described, this is only an embodiment of the present invention, even when receiving a single video signal and outputting it as a single video signal or converting and outputting a dual video signal type having a double information amount of the single video signal. May be applied.

The divider 210 in the image evaluation module 200 receives and distributes a dual image signal having a 60 Hz cycle, and outputs the signal at 120 Hz during output. Therefore, it can be used as a test signal of a full HD display device, and by repeatedly writing and reading a plurality of memory storage devices, the test can be applied to various display devices continuously. For example, if the image evaluation module of the present invention is applied, it can be used as an inspection device of a full HD display device if it is connected to the output of an existing SD image evaluation module, and the signal output at 120 Hz can be used to accurately display the display device. It is possible to check for abnormalities.

The image evaluation module of the present invention includes at least one memory (213; 213a, 213b), an LVDS output stage (214; 214a, 214b), and an FPGA (211).

The memory 213 is at least one physical recording device. In FIG. 1, two memories 213a and 214b (a first memory and a second memory) are shown as an embodiment. Each memory interior is divided into two write sectors (a first write sector and a second write sector). As described above, each memory has a plurality of write sectors, and writes the R / G / B data input to the FPGA 211 through the I / O bus alternately to each write sector of each memory 213, Repeat reading. That is, the FPGA 211 alternately writes the R / G / B data input through the I / O bus to the first write sector and the second write sector of each memory. The data written to memory is then read by the FPGA and transferred to the LVDS output.

Accordingly, when there is a dual function selection, each of the LVDS output stages 214 copies the R / G / B data in the dual image signal without timing conversion and R / G / B data buffering of the dual image signal input to the FPGA 211. The same R / G / B data to 214a and 214b, and conversely buffers the R / G / B data in the dual video signal input to the FPGA when the quad function is selected in the memory 213; 213a and 213b. Therefore, the R / G / B data, which is doubled, may be transmitted to the LVDS output terminals 214; 214a and 214b.

The LVDS output stages 214 (214a, 214b) are output stages for transmitting a signal to an LVDS device (not shown) which transmits a signal to a display device at high speed. The low voltage differential signaling (LVDS device) is used for high speed transmission of signals between the image scaler and the display panel, and can be used in the form of two LVDS channels. Therefore, in the present invention, the LVDS output stage is composed of two channels. The first channel outputs an odd line video signal of the image through the LVDS first output stage 214a, and the second channel outputs the LVDS second output stage 214b. The even line image signal is output through

The field-programmable gate array (FPGA) is an integrated circuit (IC) that operates as an arbitrary logic circuit and operates as intended by a programming designer, and bypasses or distributes a dual image signal input from an external source. The signal is divided and transmitted to the LVDS output terminal 214 as a dual or quad signal.

That is, the FPGA 211 operates in a dual function or quad function. When the dual function is selected, the FPGA 211 bypasses the dual image signal inputted from the outside as a dual form and transmits the dual image signal to the LVDS output terminal 214, and the quad function If there is a selection, the dual video signal input from the outside is converted into a quad video signal type which is doubled and output.

The dual image signal input to the FPGA 211 from the outside is input from an external device or input from a separate internal pattern FPGA. The dual image signal input to the FPGA is R / G / B Data Dual 10bit, horizontal synchronous signal (H-sync), vertical synchronous signal (V-sync), and data enable signal (I / O bus). DE, a clock signal CLK, and a D / Q selection signal are input to the divider FPGA 211.

The vertical synchronous signal V-sync indicates a synchronous time required to display one frame of the screen, and the horizontal synchronous signal H-sync indicates a synchronous time required to display one line of the screen, and the data enable The signal represents the point in time at which data is supplied to the pixel.

Accordingly, the horizontal synchronization signal (H-sync) includes as many pulses as the number of pixels included in one line. When the FPGA 211 is driven in a dual function, the timing generator 212 of the FPGA is input horizontally. It outputs to the LVDS output stage 214 as it is without converting the synchronous signal. When the FPGA 211 is driven by the quad function, the timing generator generates half of the horizontal synchronous signal inputted to the FPGA by half (1/2). The output signal is converted to an output frame rate and output to the LVDS output terminal 214.

That is, when the FPGA is driven with the quad function, in the timing variable, the horizontal synchronization signal (H-sync) is applied with "output timing variable value = input timing variable / 2" and the vertical synchronization signal (V-sync). Is applied as "output timing variable value = input timing variable value".

Similarly, the data enable signal DE inputted according to the output frame ratio of twice the horizontal synchronization signal is also converted and output from the timing generator 212 to have the frame ratio of twice. As a result, when the FPGA implements the quad function, the horizontal synchronization signal (H-sync) and the data enable signal (DE) input to the FPGA are timing converted to 1/2 and output.

The timing information having the timing variable is extracted from the horizontal synchronization signal and the vertical synchronization signal coming into the FPGA from the external dual channel and used to determine the output timing as shown in FIG. 3. For reference, the actual measurement waveform of the horizontal synchronous signal (H-sync) output from the FPGA to the LVDS output terminal when the FPGA is driven with the dual function is shown in FIG. 4 (a), and the FPGA is driven with the quad function. 4 (b) shows the actual measurement waveform of the horizontal synchronous signal (H-sync) output from the FPGA to the LVDS output terminal. As shown in FIG. 4 (a) and FIG. 4 (b), it can be seen that when the quad function is driven, the output frame ratio is twice that of the dual function.

Meanwhile, the D / Q selection signal in the present invention is driven by a dual function that outputs the signal form output to the LVDS output terminal 214 as a dual video signal form, or in the form of a quad video signal. This is a selection signal that decides whether to drive with the quad function to convert and output. For example, when the D / Q selection signal is high, the dual video signal input is bypassed as it is and output to the LVDS output terminal 214 in the form of a dual video signal, and the D / Q selection signal is low. In case of Low, the input dual video signal is converted into a quad video signal and output to the LVDS output terminal 214.

Hereinafter, the dual function driving of the FPGA bypassing the dual video signal form when the D / Q selection signal is high and converting to the quad video signal form when the D / Q selection signal is Low The operation of the quad function will be described. However, this is only an example of the description and, on the contrary, when the D / Q selection signal is high, the output is converted to quad and the dual mode is bypassed when the D / Q selection signal is Low. It will be obvious that it can be implemented.

First, a dual function driving mode in which the dual video signal is bypassed when the D / Q selection signal is high will be described.

When High is input as the D / Q selection signal, all dual image information and control signals input to the FPGA 211 are latched internally and then bypassed to the LVDS output terminal 214. . However, at this time, the dual type signal input to the FPGA is copied and transmitted to the LVDS first output terminal 214a and the LVDS second output terminal 214b as the same dual image signal, respectively (that is, Quad = dual + dual form).

In addition, when a dual function is selected by being input as a high (D / Q) selection signal, all internal logic requiring a quad function does not perform any operation as a reset state. For example, the timing generator 212 in the FPGA outputs the horizontal sync signal H-sync that is not driven without being driven, and the FPGA 211 does not convert the dual R / G / B data quad into the input form. Therefore, R / G / B data is not written and read in memory alternately.

Meanwhile, a description will be given of driving a quad function of an FPGA converting a quad image signal when the D / Q selection signal is low.

When Low is input as the D / Q selection signal, timing information for providing twice the output frame rate is extracted from the input dual video stream information in the FPGA and the video information is output based on the timing information. do. The horizontal synchronizing signal input to the FPGA is divided by half in the timing generator 212 and converted into a double output frame rate and output. As a result, in the timing variable, the horizontal synchronization signal H-sync is applied with "output timing variable value = input timing variable / 2", and the vertical synchronization signal V-sync with "output timing variable value = input". Timing variable value ".

Similarly, the data enable signal DE inputted according to the output frame ratio of twice the horizontal synchronization signal is also converted and outputted to have a frame rate of twice. As a result, when the FPGA implements the quad function, the timing generator 212 outputs the horizontal synchronization signal H-sync and the data enable signal DE that are input to the FPG 211 A by 1/2. do.

In addition, a memory that buffers the input R / G / B data is used to obtain 2 pixel information at a unit clock time and make it twice the 4 pixel information to be output to the LVDS output terminal 214. Each of the recording sectors (first recording sector and second recording sector) in the two memories are alternately buffered and read when the frame size is filled (may vary by model), and then outputted to the LVDS output terminal.

In the above description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention is not to be determined by the embodiments described above, but will be apparent in the claims as well as equivalent scope.

As described above, the present invention has an effect of providing and inspecting an image signal corresponding thereto even when the driving method of the display apparatus is different. For example, when connected to the output of the conventional SD-class inspection equipment can be used as an image evaluation inspection device of the HD-class display device, it is possible to accurately check the display device for abnormality with the signal output at 120Hz.

Claims (8)

(A) at least one LVDS output stage for transmitting a video signal (horizontal synchronization signal, vertical synchronization signal, R / G / B data, clock signal, data enable signal) to an LVDS device that outputs a high speed video signal to a display device; ; (B) ① If there is a dual function selection, the dual video signal input from the outside bypasses the dual form as it is and transmits to the LVDS output stage. ② If the quad function is selected, double the dual video signal input from the outside. An FPGA for converting into an expanded quad image signal form and transmitting the same to the LVDS output terminal; And (C) a memory for buffering the R / G / B data in the dual video signal input from the outside and providing the FPGA to the FPGA according to the instruction of the FPGA when there is a quad function selection. The image evaluation module according to claim 1, wherein the LVDS output stage comprises an LVDS first output stage for spreading an image signal on an odd line and an LVDS second output stage for spraying an image signal on an even line. The image evaluation module of claim 1, wherein the dual function or quad function operation of the FPGA is performed according to a D / Q selection signal for selecting the dual function or quad function. The image evaluation module of claim 3, wherein the FPGA is driven to the dual function when the D / Q selection signal is high and the quad function when the D / Q selection signal is high. The method of claim 1, wherein when the dual function is selected, the horizontal synchronization signal (H-sync) and the data enable signal (DE) input from the outside are bypassed and transmitted to the LVDS output stage. And a timing generator configured to divide the horizontal synchronization signal (H-sync) and the data enable signal (DE) inputted from the outside into 1/2 and transmit them to the LVDS output terminal. The R / G in the dual video signal according to claim 1 or 5, wherein the FPGA converts the dual video signal input to the FPGA when the dual function is selected without timing conversion and R / G / B data buffering. Copies / B data and transmits the same R / G / B data to each LVDS output stage, and buffers the R / G / B data in the dual image signal input to the FPGA when the quad function is selected. And an image evaluation module for transmitting R / G / B data, which has been expanded twice, to the LVDS output terminal. The method of claim 1, wherein the memory, Is divided into at least two recording sectors, And a quadrature selection, repeating write-reading to each recording sector alternately with R / G / B data in a dual video signal input to the FPGA by the instruction of the FPGA. The image evaluation module according to claim 5, wherein the timing generator maintains a reset state when the timing generator operates in the dual function.

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