KR100848578B1 - Clk generator of single photon counter - Google Patents

Abstract

A clock generator circuit of a single photon counter is provided to accurately count the number of photons incident on an image sensor by suppressing a short pulse clock from a counter clock. A delay unit(710) delays one of a Comp_OUT signal and a CLK_SEL signal, logically manipulates the Comp_OUT and CLK_SEL signals, and outputs a first manipulation signal. The Comp_OUT signal is an output signal from a comparator. The CLK_SEL signal is a clock select signal for counting digital pulses in the Comp_OUT signal. A logic manipulator(720) performs a logical manipulation on the Comp_OUT and CLK_SEL signals to generate a signal manipulation signal. A latch circuit unit(730) keeps a CLK_SET_OUT signal corresponding to the first and second manipulation signals and outputs the latched signal. A counter unit(740) counts the number of photons by using the Comp_OUT signal, the CLK_SEL_OUT signal, and a reset signal.

Description

Clock generator circuit for single photon counter {Clk Generator of Single Photon Counter}

1 is a schematic diagram of a typical single photon counting digital image sensor.

2 is a block diagram of a conventional single photon counting digital image sensor.

3 is a diagram illustrating a simulation result of a single photon counting image sensor.

4 is a conventional clock generation circuit for a single photon counter.

5 is a timing diagram of a conventional single photon counting counter.

6 is a diagram showing a simulation result of a conventional clock generation circuit for a single photon counter.

7 is a clock generation circuit diagram for a single photon counter according to the present invention.

8 is a diagram illustrating a simulation result of a clock generation circuit for a single photon counter according to the present invention.

9 is a diagram comparing the clock of the present invention and the conventional single photon counter clock generation circuit.

<Explanation of symbols for the main parts of the drawings>

710: delay unit 711: first inverter

712: first NAND gate 713: second inverter

714: third inverter 715: first delay means

716: second delay means 720: logic operation unit

721: second NAND gate 730: latch circuit

731: third NAND gate 732: fourth NAND gate

740: counter

The present invention relates to a clock generation circuit, and more particularly to a clock generation circuit for a single photon counter used in a single photon counting digital X-ray image sensor.

X-ray (X-ray) image sensor is a device that detects the subject information through the X-ray and converts it into an electrical video signal, it is widely used in television, camera, facsimile.

In the conventional digital X-ray image sensor, a charge accumulation method of accumulating and imaging an electron-hole pair (EHP) generated by X-rays for a given time has been used.

The charge accumulation method can be divided into direct type and indirect type, which is a method of generating an electrical signal of an electron-hole pair by directly reacting an X-ray with a detector without an intermediate medium. The indirect method converts incident X-rays into visible light through a scintillator and then converts them into electrical signals using a sensor that can receive visible light.

Indirect method loses signal when converting X-rays into visible light, and image loss occurs when detecting visible light again, whereas direct method does not lose signal like indirect method. Image quality is excellent.

However, the charge accumulation method has a disadvantage in that there is a risk of radiation exposure of the user because of the relatively high radiation dose, whether direct or indirect.

In order to overcome this drawback, the photon counting method is introduced. This method is a method of counting and imaging the number of incident photons.

The photon counting method can obtain high quality images with relatively low radiation dose (exposure dose) compared to the conventional charge accumulation type image sensor, thereby reducing the user's fear of radiation coating, which is why mammography, CT, It can be commercialized not only for medical devices such as dental DR and PET, but also for applications such as industrial nondestructive testing and molecular imaging.

An image sensor using the photon counting method is a single photon counting digital X-ray image sensor that counts and images photons incident for a given time.

1 schematically illustrates a general single photon counting digital image sensor.

Referring to FIG. 1, the single photon counting digital X-ray image sensor may be in a hybrid form in which the X-ray detector 110 and the CMOS readout chip 120 are combined, and the X-ray detector directly without flip chip bonding. It can also be connected to a readout chip for photon counting.

2 is a block diagram of a conventional single photon counting digital image sensor.

Referring to FIG. 2, the conventional single photon counting X-ray image sensor includes an X-ray detector 210 and a pixel 230 for a CMOS read chip, and has a bump bonding pad 220 connecting the same. The X-ray detector 210 and the CMOS read chip pixel 230 may be configured in an array form.

One node of the X-ray detector 210 is connected to VHH, which is a bias voltage, and the other node is connected to the bump bonding pad 220.

When photons enter the X-ray detector 210, electron-hole pairs corresponding to the energy are generated. Holes in the electron-hole pairs enter the input of the preamplifier 240 through the bonding pads. The preamplifier 240 serves as a charge integrator when the resistor R is absent, and converts the incoming charge into a voltage.

3 is a diagram illustrating a simulation result of a single photon counting image sensor.

In the case where the resistor R is present, when charge is received in the bias voltage VB state which is a common voltage by negative feedback, the output node voltage Vpreamp of the preamplifier 240 falls in the form of a pulse, and the resistor R Is discharged to the bias voltage.

In this way, when a voltage pulse enters the output node voltage Vpreamp of the preamplifier 240, the comparator 250 compares the threshold voltage V _THR , which is a reference voltage supplied from the outside of the CMOS read chip pixel 230, so that Vpreamp is greater than V _THR . If it is low, it determines that a single photon is input and sends a pulse corresponding to Low to the Comp_out node, which is an output node of the comparator 250.

This digital pulse of Comp_out enters the counter input of FIG. 2 to count how many monoliths have entered.

4 is a diagram illustrating a conventional single photon counter clock generation circuit, and FIG. 5 is a diagram illustrating a conventional single photon counting timing diagram. FIG. 6 is a simulation result of the conventional single photon counter clock generation circuit of FIG. 4. It is a figure which shows.

The conventional clock generation circuit for a single photon counter shown in FIG. 4 is a linear feedback shift register (hereinafter referred to as 'LFSR') as a counter circuit, with N rising edges D Flip-Flop and Exclusive-NOR Gate. Consists of. In case of N bit Counter, it can count up to 2 ^N -1. LFSR counters can be counted at high speed and have a small layout area, making them suitable as photon counters. The operation of the LFSR counter is divided into a reset mode, a counting mode, and a readout mode as shown in FIG. 5. In counting mode, the LFSR counter counts the digital pulses at Comp_OUT whenever the X-ray photons enter the photodiode. In readout mode, the LFSR counter operates as a shift register, and is outputted as SOUT (serial out) by cloking the external clock CLK_EXT.

The conventional LFSR counter shown in FIG. 4 is a short pulse like CLK_OLD shown in FIG. 6 when the CLK_SEL signal, which is a clock selection signal for counting digital pulses in the Comp_OUT signal, changes from high to low when entering the readout mode from the counting mode. There is a problem that the clock does not meet the maximum operating frequency of the counter and does not count or the internal node of the counter floats to prevent proper counting.

The present invention has been proposed to solve the above problems, and includes a single photon counter clock generation circuit inside the counter to prevent the generation of a short pulse clock when the CLK_SEL changes from high to low to increase the maximum operating frequency of the counter. The purpose is to ensure.

According to an aspect of the present invention, a clock signal generation circuit for a single photon counter according to the present invention may delay one of a comp_out signal, a comparator output signal, and a CLK_SEL signal, a clock selection signal for counting a digital pulse of the comp_out signal. A delay unit for performing a logic operation on the Comp_OUT signal and the CLK_SEL signal to output a first operation signal, a logic operation unit for performing a logic operation of the CLK_SEL signal and the Comp_OUT signal to generate a second operation signal, and the first operation signal And a latch circuit unit for latching and outputting the CLK_SEL_OUT signal corresponding to the second operation signal, and a counter unit 740 for counting the number of photons using the Comp_OUT signal, the CLK_SEL_OUT signal, and the reset signal RSTb. It is done.

In the clock generation circuit for a single photon counter according to the present invention, the delay unit includes a first inverter for inverting the CLK_SEL signal and a first NAND gate for NAND combining the CLK_SEL signal and the Comp_OUT signal passed through the first inverter. It is preferable that it consists of.

In the clock generation circuit for a single photon counter according to the present invention, the delay unit includes a second inverter for inverting the output signal of the first NAND gate, a third inverter for inverting the output signal of the second inverter, and the second Preferably it further comprises a first delay means for delaying the output signal of the second inverter and the second delay means located between the inverter and the third inverter.

In the clock generation circuit for a single photon counter according to the present invention, the first delay means and the second delay means are preferably formed of a capacitor or an MOS transistor.

In the clock generation circuit for a single photon counter according to the present invention, it is preferable that the logic calculating section comprises a second NAND gate NAND combining the Comp_OUT signal and the CLK_SEL signal.

In the clock generation circuit for a single photon counter according to the present invention, the latch circuit unit includes a third NAND gate for NAND combining the output signal of the delay unit and the CLK_SEL_OUT signal, and an output signal of the logic operation unit and the third NAND gate. It is preferable that it consists of a 4th NAND gate which NAND-combines an output signal.

Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.

7 is a clock generation circuit diagram for a single photon counter according to the present invention.

Referring to FIG. 7, the clock generation circuit for a single photon counter according to the present invention includes a delay unit 710, a logic operation unit 720, a latch circuit unit 730, and a counter unit 740.

The delay unit 710 delays one of the Comp_OUT signal, which is a comparator output signal, and the CLK_SEL signal, which is a clock selection signal for counting the digital pulses of the Comp_OUT signal, and then logically operates the Comp_OUT and CLK_SEL signals. 1 Output the operation signal.

The delay unit 710 may include a first NAND gate NAND combining the CLK_SEL signal and the Comp_OUT signal passed through the first inverter 711 and the first inverter 711 to invert the CLK_SEL signal. 712).

When the CLK_SEL signal passes through the first inverter 711, a certain amount of delay is generated. Therefore, when the CLK_SEL is changed from high to low, CLK_SEL_OUT is changed from high to low after 5 ns to ensure the maximum operating frequency of the counter. Will change.

In order to further ensure the delay effect, the delay unit 710 may invert the output signal of the second inverter 713 and the second inverter 713 to invert the output signal of the first NAND gate 712. First delay means 715 and the first delay means 715 disposed between the third inverter 714, the second inverter 713, and the third inverter 714 to delay an output signal of the second inverter 713; It is preferable to further include a second delay means 716 for delaying the output signal of the third inverter 714.

That is, the output signal of the first NAND gate 712 passes through the second inverter 713, the first delay means 715, the third inverter 714, and the second delay means 716. CLK_SEL_OUT changes from high to low after 5ns, which is the time to ensure that the counter's maximum operating frequency is changed from high to low.

Therefore, when CLK_SEL is changed from high to low when entering the counting mode from the counting mode, the maximum operating frequency of the counter is guaranteed, so that the counter cannot be counted because the maximum operating frequency of the counter is not satisfied.

The logic operation unit 720 includes a second NAND gate 721 to generate a second operation signal by performing a logical operation by NAND combining the CLK_SEL signal and the Comp_OUT signal. The generated second operation signal is input to the latch circuit unit 730.

The latch circuit unit 730 includes a third NAND gate 731 and a fourth NAND gate 732, and latches and outputs a CLK_SEL_OUT signal corresponding to the first operation signal and the second operation signal as inputs. do.

That is, the third NAND gate 731 receives the first operation signal, which is the output signal delayed by the delay unit 710, and the CLK_SEL_OUT signal, which is the output signal of the fourth NAND gate 732, and the fourth NAND gate 732 is input. The second operation signal, which is the output signal of the logic operation unit 710, and the output signal of the third NAND gate 731 are inputted and latched to output the CLK_SEL_OUT signal to the counter unit 740.

The counter unit 740 counts the number of photons using the Comp_OUT signal, the CLK_SEL_OUT signal, and the reset signal RSTb.

Since the counter unit 740 is well known as described above with reference to FIG. 4, a detailed description thereof will be omitted.

8 is a diagram illustrating a simulation result of a clock generation circuit for a single photon counter according to the present invention, and FIG. 9 is a diagram comparing the clock of the present invention and a conventional single photon counter clock generation circuit.

8 and 9, the clock CLK_NEW of the clock generation circuit for the single photon counter according to the present invention can guarantee the maximum operating frequency of the counter compared to the clock CLK_OLD of the conventional single photon counter clock generation circuit. As you can see the delay is changed from high to low.

As described above, the present invention has been described with reference to the embodiments illustrated in the drawings, which are merely exemplary, and it should be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. will be. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

In the clock generation circuit for a single photon counter according to the present invention, a clock generation circuit is mounted on a counter inside a pixel for a CMOS read chip to eliminate a short pulse clock of a counter clock that may occur when entering a readout mode from a counting mode. By ensuring the maximum operating frequency of the advantage that can be accurately counted photons incident on the image sensor.

Claims (6)

In the clock generation circuit for a single photon counter, Delay of one of the comp_out signal, which is a comparator output signal, and the CLK_SEL signal, which is a clock selection signal for counting the digital pulses in the comp_out signal, and then delaying the logic operation of the comp_out signal and the clk_sel signal to output a first operation signal. Unit 710; A logic operation unit 720 for generating a second operation signal by performing a logic operation on the CLK_SEL signal and the Comp_OUT signal; A latch circuit part 730 for latching and outputting the CLK_SEL_OUT signal corresponding to the first operation signal and the second operation signal; And And a counter unit (740) for counting the number of photons using the Comp_OUT signal, the CLK_SEL_OUT signal, and a reset signal (RSTb). The method of claim 1, wherein the delay unit 710 is A first inverter 711 for inverting the CLK_SEL signal; And And a first NAND gate (712) for NAND combining the CLK_SEL signal and the Comp_OUT signal passed through the first inverter (711). The method of claim 2, wherein the delay unit 710 is A second inverter 713 for inverting the output signal of the first NAND gate 712; A third inverter 714 for inverting the output signal of the second inverter 713; First delay means (715) positioned between the second inverter (713) and the third inverter (714) to delay an output signal of the second inverter (713); And And a second delay means (716) for delaying the output signal of the third inverter (714). The method of claim 3, wherein the first delay means 715 and the second delay means 716, A clock generation circuit for a single photon counter, characterized in that formed of a capacitor or a MOS transistor. The logic operation unit 720 of claim 1, wherein And a second NAND gate (721) for NAND combining the Comp_OUT signal and the CLK_SEL signal. The method of claim 1, wherein the latch circuit portion 730 is A third NAND gate 731 for NAND combining the output signal of the delay unit 710 and the CLK_SEL_OUT signal; And And a fourth NAND gate (732) for NAND combining the output signal of the logic operation unit (720) and the output signal of the third NAND gate (731).

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