KR100847913B1 - Testing Apparatus, and Testing Method - Google Patents

Abstract

Accurately time the memory under test to return from the busy state to the ready state.

A test apparatus for testing a memory under test, comprising: a pattern generator that sequentially writes a plurality of test patterns into a memory under test, and writing a test pattern into the memory under test starts, A test apparatus including a period measuring unit for measuring a period until a state in which writing of a test pattern becomes possible is measured by counting the number of pulses of a reference clock at a predetermined frequency.

Clock, MUT Signal, Logic, Capture Memory, Set Reset Latch

Description

Testing Apparatus, and Testing Method

FIG. 1: is a figure which shows the outline | summary of the structure of the test apparatus 100 by embodiment of this invention.

2 is a diagram illustrating an example of a detailed configuration of the test apparatus 100.

3 is a diagram illustrating an example of the configuration of the evaluation unit 44.

4 is a diagram illustrating an example of a timing chart illustrating the operation of the test apparatus 100.

[Description of the code]

10... 12,. Test cycle generator, 14... Pattern generator 16. Logical comparison unit, 18... Input / output circuit, 20... Driver, 22.. Comparator, 24... Period measuring unit, 26... Capture memory, 28... Trigger generation section; Bus, 30... Divided clock selector; Counter clock selector; Register, 36... Dispenser, 38... Set reset latch, 40.. Pulse selector, 42... 44,. Evaluation unit, 46. .. First result selection section, 48. Second result selection section, 50... Comparison circuit, 52... Register, 54... Error detection unit, 56. Measurement result transmitting unit, 100... Test device, 200... Test Memory

The present invention relates to a test apparatus for testing a memory under test and a test method. In particular, the present invention provides a test apparatus for evaluating a memory under test based on a time when a predetermined signal is input to the memory under test, based on a time when the memory under test returns from a busy state to a ready state. It is about.

Conventionally, an item for testing a memory under test, such as a flash memory, writes predetermined data into the memory under test, and evaluates the memory under test based on whether or not the data read from the memory under test matches the expected value data. The item to be known is known. Further, the memory under test is based on the time from the input of the predetermined signal to the memory under test, such as a flash memory, until the memory under test returns from the busy state to the ready state. There is a need to evaluate.

Since the related patent document is not recognized at present, the description is abbreviate | omitted.

In contrast, the conventional test apparatus includes a pattern generator which writes predetermined data into the memory under test, and a logic comparison circuit that determines whether the data read from the memory under test matches the expected value data. have. However, it does not include a means for accurately measuring the time from the busy state to the ready state.

For example, the conventional test apparatus may include a counter for measuring the period of a clock signal output by the memory under test, but the memory under test is ready from the busy state by using the counter. It does not include a function to measure the time until returning to the) state.

For this reason, an object of this invention is to provide the test apparatus and test method which can solve the above-mentioned subject. This object is achieved by a combination of the features described in the independent claims in the claims. The dependent claims also define more advantageous specific examples of the invention.

MEANS TO SOLVE THE PROBLEM In order to solve the said subject, in the 1st aspect of this invention, it is a test apparatus which tests a memory under test, The pattern generation part which sequentially writes several test patterns to the memory under test, and a memory under test A period measuring unit for measuring a period from the start of writing the test pattern to the state under which the memory under test becomes the state in which the next test pattern can be written by counting the number of pulses of the reference clock at a predetermined frequency. It provides a test device comprising.

The memory under test represents a first logical value when the test pattern is written and the next test pattern cannot be written, and a MUT indicating the second logical value when the next test pattern is ready to be written. Outputs a signal, and the pattern generator outputs a measurement cycle signal indicative of the start timing of writing the test pattern, and the cycle measurement unit receives the measurement cycle signal, and then the logic value of the MUT signal is changed from the first logical value to the second. The number of pulses of the reference clock may be counted for a period until the logic value is changed.

After receiving the measurement cycle signal, the test apparatus generates a pulse signal having a pulse width according to a period from when the logic value of the MUT signal is changed from the first logic value to the second logic value, and based on the pulse signal A set reset latch for controlling the pulse count period in the period measuring unit may further be included. The test apparatus may further include a capture memory for storing the measurement result in the period measuring unit.

The test apparatus selects either the evaluation unit for evaluating the memory under test, the measurement result at the period measuring unit, or the evaluation result at the evaluation unit based on the measurement result at the period measuring unit, The apparatus may further include a first result selector that outputs to the capture memory.

The test apparatus selects a logical comparison unit that determines whether or not each address of the memory under test is judged based on the read data read out from the memory under test, the determination result in the logic comparison unit, or the first result selection. The second result selector may further select one of the signals to be additionally output and store it in the capture memory.

The evaluation unit may include a plurality of registers each storing different reference values, and a comparison circuit for comparing the respective reference values with the measurement results and outputting evaluation values according to the comparison results.

The test apparatus, when starting to write the test pattern into the memory under test, when the logic value of the MUT signal does not change from the first logic value to the second logic value until a predetermined period of time has elapsed, the time-out signal The apparatus may further include an error detection unit that outputs a, and the evaluation unit may evaluate the memory under test further based on the time-out signal.

The pattern generation unit sequentially inputs each test pattern into the memory under test at predetermined test cycles for each test pattern, and the error detection unit starts writing of each test pattern and then starts the test cycle corresponding to the test pattern. In the meantime, when the logic value of the MUT signal does not change from the first logic value to the second logic value, the timeout signal may be output.

The test apparatus may further include an initialization unit for initializing the count value of the period measuring unit for each test cycle. The period measuring unit may integrate the count values for each test pattern.

In the second aspect of the present invention, a test method for testing a memory under test includes: a pattern generating step of sequentially writing a plurality of test patterns into the memory under test, and writing of the test pattern into the memory under test; And a period measuring step of measuring the period until the memory under test becomes a state in which the next test pattern can be written by counting the number of pulses of the reference clock at a predetermined frequency. do.

Note that the above summary of the invention does not enumerate all of the necessary features of the present invention, and subcombinations of such feature groups can also be inventions.

EMBODIMENT OF THE INVENTION Hereinafter, although this invention is demonstrated through embodiment of invention, the following embodiment does not limit invention by a claim, and all the combination of the features demonstrated in embodiment are essential for the solution of this invention. It is not limited to this.

FIG. 1: is a figure which shows the outline | summary of the structure of the test apparatus 100 by embodiment of this invention. The test apparatus 100 is a device for testing a memory under test 200, such as a flash memory, which includes a controller 10, a test cycle generator 12, a pattern generator 14, a logic comparator 16, an input / output circuit 18, a cycle measurement unit 24, and a capture memory 26. , And bus 29. The control unit 10 controls the test period generation unit 12, the pattern generation unit 14, the logic comparison unit 16, the input / output circuit 18, the period measurement unit 24, and the capture memory 26 via the bus 29.

In addition, the test apparatus 100 writes predetermined data into the memory under test 200 and stores the data in the memory cell test and the memory under test 200 which determine whether the memory 200 under test is determined based on the data read from the memory under test 200. A function of inputting a predetermined signal and performing an operation completion time test for determining whether the memory under test 200 is successful based on the time from the busy state to the ready state returning to the ready state. It includes. Here, the busy state indicates a state in which the next signal cannot be input to, for example, the memory under test 200, and the ready state indicates, for example, a signal input to the memory under test 200. Indicates the state that can be.

First, the operation of the test apparatus 100 in the case of performing the memory cell test will be described. The control unit 10 controls each component of the test apparatus 100 based on a test program and a test pattern given in advance. For example, the control unit 10 generates a desired test pattern in the pattern generator 14 based on the test pattern. In addition, the control unit 10 generates a test cycle signal having a desired cycle in the test cycle generator 12 based on a test program given in advance. The pattern generator 14 inputs the data of the test pattern to the memory under test 200 via the input / output circuit 18 in accordance with the test cycle signal generated by the test cycle generator 12.

The input / output circuit 18 includes a driver 20 and a comparator 22. The driver 20 shapes the test pattern output by the pattern generator 14 and inputs it to the memory under test 200. The comparator 22 compares the signal output from the memory under test 200 with a predetermined threshold voltage and converts the output signal into digital data.

The logic comparator 16 compares the data output by the comparator 22 with the expected value data given from the pattern generator 14 to determine whether the memory 200 under test is successful. For example, the logic comparison unit 16 may compare the data value read from each address of the memory under test 200 with the expected value data corresponding to the address, and determine whether each address is good or bad. In addition, the pattern generator 14 may provide the logical comparator 16 with the same data as the test pattern written in the memory under test 200 as expected value data.

The capture memory 26 stores the determination result in the logic comparison unit 16. For example, the capture memory 26 stores the determination result for each address of the memory under test 200 corresponding to each address. By such an operation, it is possible to determine whether the memory cell of the memory under test 200 is valid. In addition, by acquiring the determination result into the capture memory 26, the failure analysis of the memory under test 200 can be performed.

Next, the operation of the test apparatus 100 in the case of performing the operation completion time test will be described. The pattern generator 14 sequentially inputs a plurality of test patterns for operating the memory under test 200 to the memory under test 200. In addition, the pattern generator 14 indicates a cycle for performing the test and outputs a measurement cycle signal. For example, the measurement cycle signal may be a signal indicating H logic from the timing at which the test should be started to the timing at which the test should be completed.

When each test pattern is received, the memory under test 200 outputs a MUT signal indicating whether or not the next test pattern can be input. For example, the MUT signal indicates a first logic value when the next test pattern cannot be written and indicates a second logic value when the next test pattern can be written. In this example, the case where the first logic value is L logic and the second logic value is H logic will be described.

The period measuring unit 24 starts writing the test pattern with respect to the memory under test 200, and then starts a cycle from the test memory 200 to a state where writing of the next test pattern becomes possible. The measurement is made by counting the number of pulses of the reference clock. For example, the period measuring unit 24 may be a counter that counts the number of pulses of the reference clock after the rising edge of the measurement cycle signal is input and when the logic value of the MUT signal changes from the L logic to the H logic.

The period measuring unit 24 may receive the MUT signal via the comparator 22. For example, the test apparatus 100 may include a plurality of input / output units 18 corresponding to the plurality of pins of the memory under test 200. The period measuring unit 24 may receive the MUT signal via a comparator 22 corresponding to the pin of the memory under test 200 that outputs the MUT signal.

In addition, the period measuring unit 24 may determine whether the memory under test 200 is good or not, based on the count result. The period measuring unit 24 may further include a function of receiving the clock signal output from the memory under test 200 via the comparator 22 and measuring the period of the clock signal. The control unit 10 may control which measurement the period measurement unit 24 performs. The capture memory 26 stores the counting result or the determination result in the period measuring unit 24. By such an operation, an operation completion time test can be performed.

2 is a diagram illustrating an example of a detailed configuration of the test apparatus 100. In FIG. 2, the structure which performs an operation completion time test is shown, and the test apparatus 100 which omitted the control part 10, the test period generation part 12, the pattern generation part 14, the logic comparison part 16, the input / output circuit 18, and the bus 29 is shown. do.

In addition to the configuration described with reference to FIG. 1, the test apparatus 100 includes a trigger generator 28, a divider clock selector 30, a counter clock selector 32, a register 34, a divider 36, a set reset latch 38, and pulse selection. The unit further includes an initialization unit 42, an error detection unit 54, and a measurement result transmission unit 56.

The trigger generation unit 28 generates a trigger signal for controlling the period measurement unit 24 based on the measurement cycle signal output from the pattern generation unit 14 and the test cycle signal given through the bus 29. For example, after the measurement cycle signal shows the H logic, the trigger generator 28 outputs the trigger signal in accordance with the pulse of the test cycle signal first given.

The set reset latch 38 generates a pulse signal based on the trigger signal and the MUT signal output from the memory under test 200. For example, the set reset latch 38 generates a pulse signal having a pulse width according to a period from which the logic signal of the MUT signal is changed from the L logic to the H logic after receiving the trigger signal. The set reset latch 38 supplies the pulse signal to the period measurement unit 24 via the pulse selector 40, and controls the pulse counting period in the period measurement unit 24.

The period measuring unit 24 counts the number of pulses of the reference clock given through the counter clock selection unit 32 and the period in which the pulse signal indicates the H logic. With such a configuration, it is possible to measure the time until the memory under test 200 returns from the busy state to the ready state.

The measurement result transmission unit 56 stores the measurement result in the period measurement unit 24 in the capture memory 26. In addition, the measurement result transmission unit 56 may determine whether the memory under test 200 is successful or not, based on the measurement result in the period measurement unit 24, and store the determination result in the capture memory 26.

In this example, the measurement result transmission unit 56 includes an evaluation unit 44, a first result selection unit 46, and a second result selection unit 48. The evaluation unit 44 determines whether the memory under test 200 is good or not, based on the measurement result in the period measuring unit 24. The first result selector 46 selects and outputs either the measurement result in the period measurement unit 24 or the evaluation result in the evaluation unit 44. With such a configuration, either the raw data of the measurement in the period measuring unit 24 or the evaluation result in the evaluation unit 44 can store desired data in the capture memory 26.

The second result selector 48 selects either the comparison result in the logic comparator 16 or the signal output from the first result selector 46 and stores it in the capture memory 26. With such a configuration, the desired test result can be stored in the capture memory 26 either in the memory cell test or the operation completion time test.

In addition, when a plurality of test patterns are sequentially input to the memory under test 200, and for each test pattern, the time from the busy state to the ready state is measured. The initialization unit 42 may reset the count value in the period measurement unit 24 to the initial value for each test pattern. Since each test pattern is input to the memory under test 200 in accordance with the test period, the initialization unit 42 may reset the count value in the period measuring unit 24 to the initial value in accordance with the test period.

In addition, the initialization part 42 may reset the measured value in the period measurement part 24 to an initial value for every some test pattern. In this case, the period measuring unit 24 can integrate the count values for each test pattern. That is, by not resetting the measured value in the period measurement part 24 for each test pattern, the count value with respect to a predetermined number of test patterns can be integrated. As a result, for example, in the case where the memory under test 200 includes a plurality of address blocks, and a test pattern is input for each address block, coefficient values for a predetermined number of address blocks can be accumulated.

In addition, the error detection unit 54 outputs a time-out signal when the MUT signal does not change from L logic to H logic until a predetermined period elapses after starting writing of the test pattern into the memory under test 200. . In this example, the error detection unit 54 detects the timing at which writing of the test pattern is started based on the measurement cycle signal and the test period. On the basis of the signal output from the set reset latch 38, it is detected whether or not the MUT signal is changed from L logic to H logic. The evaluation unit 44 may determine whether or not the memory 200 under test is judged based on the time-out signal.

In the case where the test apparatus 100 inputs and tests the same test pattern in parallel with respect to the plurality of memory under test 200, when the test device 100 detects the time-out signal with respect to any one of the memory under test 200, The test cycle using the test pattern may be completed, and the test using the next test pattern may be performed on the entire memory 200 under test. The predetermined period of time for detecting the timeout may be substantially the same length as the test period during which the test is to be performed. For example, the error detection unit 54 starts the input of the test pattern in synchronization with the test cycle signal, and then, until the MUT signal detects a pulse representing the next test cycle in the test cycle signal, the MUT signal is separated from the L logic. If it does not change to H logic, you may output a timeout signal.

The period measuring unit 24 may be a counter for clock period measurement included in a conventional test apparatus. In this case, in the conventional test apparatus, the measurement result of the counter was read out to the control unit 10 via the bus 29. On the other hand, the test apparatus 100 in this example can store the measurement result in the period measurement unit 24 in the capture memory 26 via the measurement result transmission unit 56. For this reason, the data processing after a measurement can be performed at high speed.

When the period of the clock signal output by the memory under test 200 is measured by using the period measuring unit 24, the pulse selector 40 receives the clock signal output by the memory under test 200 as the MUT signal, and receives the MUT signal. It selects and supplies it to the period measuring part 24. In this case, the pulse selector 40 may receive the clock signal via the comparator 22 (see FIG. 1) corresponding to the pin of the memory under test 200 which outputs the clock signal.

The period measuring unit 24 counts the number of pulses of the reference clock while the MUT signal indicates the H logic. With such a configuration, the cycle of the clock signal output from the memory under test 200 can be measured.

In addition, the period measuring unit 24 may receive a clock signal divided by a predetermined division ratio and count the pulse number of the reference clock in accordance with the signal. Thereby, in the said clock signal, the period for every predetermined | prescribed number of cycles determined by the said division ratio can be measured. In this case, the frequency divider 36 receives the clock signal through the frequency division clock selector 30 and divides the clock signal at the division ratio set in the register 34. The pulse selector 40 selects the divided clock output by the frequency divider 36 and supplies it to the period measuring unit 24.

According to the test apparatus 100 in this example, it is possible to accurately measure the time for the memory under test 200 to return to the ready state from the busy state. In addition, by including the set reset latch 38 and the pulse selector 40, the return time can be measured using a counter included in the conventional test apparatus. For this reason, the return time can be measured in a small circuit. In addition, by including the measurement result transmission unit 56, the measurement result can be stored in the capture memory 26. For this reason, data transfer and data processing can be performed at high speed.

3 is a diagram illustrating an example of the configuration of the evaluation unit 44. The evaluation unit 44 includes a comparison circuit 50 and a plurality of registers 52. The plurality of registers 52 store different reference values, respectively. The comparison circuit 50 compares the measurement result in the period measuring unit 24 with a plurality of reference values stored in each register 52, and evaluates the memory under test 200 in a plurality of steps. The capture memory 26 may store the evaluation by the plurality of steps.

4 is a diagram illustrating an example of a timing chart illustrating the operation of the test apparatus 100. When the memory cell test of the memory under test 200 is performed, the test period generator 12 generates test period signals having substantially the same period as shown in FIG. 4. The pattern generator 14 inputs test patterns, such as an address pattern and a data pattern, to the memory under test 200 in synchronization with the test period signal.

When the operation completion time test of the memory under test 200 is performed, the test cycle generator 12 generates a test cycle signal at a cycle corresponding to the period during which the test is to be performed. In addition, the pattern generator 14 outputs a measurement cycle signal having a pulse width corresponding to a period during which the test is to be performed.

As described above, the trigger generator 28 generates a trigger signal having a test cycle signal and a pulse corresponding to the measurement cycle signal. In addition, as described above, the memory under test 200 outputs a MUT signal indicating whether the next program is in an executable state after a predetermined program is input.

The set reset latch 38 generates a pulse signal having a pulse width from the timing of the trigger signal to the timing of the rising edge of the MUT signal. The period measuring unit 24 also counts pulses of the reference clock while the pulse signal indicates H logic. By such operation, the operation completion time of the memory under test 200 can be measured.

As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various changes or improvements can be made to the above embodiment. It is evident from the description of the claims that various modifications or improvements added thereto may be included in the technical scope of the present invention.

As is apparent from the above, according to the present invention, it is possible to accurately measure the time for the memory under test to return from the busy state to the ready state. Moreover, the said return time can be measured using the counter contained in the conventional test apparatus. For this reason, the return time can be measured in a small circuit. In addition, the measurement result can be stored in a capture memory included in a conventional test apparatus. For this reason, data transfer and data processing can be performed at high speed.

Claims (12)

A test apparatus for testing a memory under test, A pattern generator which sequentially writes a plurality of test patterns into the memory under test; The period from the start of writing the test pattern to the memory under test to the state under which the memory under test becomes a state in which the writing of the next test pattern becomes possible becomes the number of pulses of the reference clock at a predetermined frequency. A test apparatus including a period measuring unit for measuring by counting. The method of claim 1, The test memory indicates a first logic value when the test pattern is written and the next test pattern cannot be written, and a second test memory when the test pattern can be written. Outputs the MUT signal representing the logic value, The pattern generator outputs a measurement cycle signal indicating a start timing of writing of the test pattern, The period measuring unit is a test device for counting the number of pulses of the reference clock for a period from when the measurement cycle signal is received to when the logic value of the MUT signal is changed from the first logic value to the second logic value. . The method of claim 2, After receiving the measurement cycle signal, generate a pulse signal having a pulse width according to a period from the logic value of the MUT signal to the second logic value, and based on the pulse signal And a set reset latch for controlling the pulse counting period in the period measuring unit. The method of claim 2, And a capture memory for storing the measurement result in the period measuring unit. The method of claim 4, wherein An evaluation unit for evaluating the memory under test based on the measurement result in the period measuring unit; And a first result selector which selects one of the measurement result in the period measuring part or the evaluation result in the evaluation part and outputs the result to the capture memory. The method of claim 5, A logic comparator which determines whether or not each address of the memory under test is determined based on read data read out from the memory under test; And a second result selector which selects one of a determination result in the logic comparison unit or a signal output by the first result selector and stores the captured result in the capture memory. The method of claim 5, The evaluation unit, A plurality of registers storing different reference values, And a comparison circuit for comparing the respective reference values with the measurement results and outputting evaluation values according to the comparison results. The method of claim 5, When the logic value of the MUT signal does not change from the first logic value to the second logic value until a predetermined period elapses after starting writing of the test pattern into the test memory, Further comprising an error detection unit for outputting a signal, And the evaluation unit further evaluates the memory under test based on the timeout signal. The method of claim 8, The pattern generator is configured to sequentially input each test pattern to the memory under test at predetermined test cycles for each test pattern, After the error detection unit starts writing each of the test patterns, the logic value of the MUT signal is changed from the first logic value to the second logic value between the test periods corresponding to the test pattern. If not, the test device to output a time-out signal. The method of claim 9, And an initialization unit for initializing a coefficient value of the period measurement unit for each test cycle. The method of claim 1, The period measuring unit is a test device for integrating the coefficient value for each of the test pattern. In the test method for testing the memory under test, A pattern generation step of sequentially writing a plurality of test patterns into the memory under test, The period from the start of writing the test pattern to the memory under test to the state under which the memory under test becomes a state in which the writing of the next test pattern becomes possible becomes the number of pulses of the reference clock at a predetermined frequency. A test method comprising a cycle measurement step of measuring by counting.

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