KR100844094B1 - Semiconductor device with nano-wire structure, semiconductor memory device having the same, and method of manufacturing the semiconductor memory device - Google Patents

Semiconductor device with nano-wire structure, semiconductor memory device having the same, and method of manufacturing the semiconductor memory device Download PDF

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KR100844094B1
KR100844094B1 KR1020070016461A KR20070016461A KR100844094B1 KR 100844094 B1 KR100844094 B1 KR 100844094B1 KR 1020070016461 A KR1020070016461 A KR 1020070016461A KR 20070016461 A KR20070016461 A KR 20070016461A KR 100844094 B1 KR100844094 B1 KR 100844094B1
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source
nanowires
substrate
drain electrodes
memory device
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Korean (ko)
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최헌진
성한규
이정오
장현주
김주진
전은경
김병계
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연세대학교 산학협력단
한국화학연구원
전북대학교산학협력단
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82B—NANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
    • B82B3/00—Manufacture or treatment of nanostructures by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

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  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Nanotechnology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
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  • Crystallography & Structural Chemistry (AREA)
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  • Chemical Kinetics & Catalysis (AREA)
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  • Theoretical Computer Science (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

A nano wire semiconductor device, a semiconductor memory device having the same, and a manufacturing method thereof are disclosed. The disclosed semiconductor memory device includes an element formation substrate having a dielectric layer on a surface thereof, a plurality of nanowires arranged on the element formation substrate, and disposed on the plurality of nanowires, respectively, on the one nanowire. And source and drain electrodes spaced apart from each other by a predetermined distance, and silicide islands positioned in contact portions of the source and drain electrodes with the nanowires. At this time, the charge is captured and erased through the silicide island by the voltage applied to the semiconductor substrate and the voltage applied to the source / drain electrodes.

Description

Nano-wire semiconductor device, semiconductor memory device having the same and method for manufacturing the same {Semiconductor Device With Nano-Wire Structure, Semiconductor Memory Device Having The Same, And Method Of Manufacturing The Semiconductor Memory Device}

1 to 5 are perspective views for each process for explaining a nanowire semiconductor memory device according to an embodiment of the present invention,

6 to 8 are electron micrographs of the nanowires according to an embodiment of the present invention, FIG. 6 is a scanning micrograph showing a 50 μm nanowire, FIG. 7 is a transmission electron micrograph showing a 200 nm nanowire, and FIG. 8 High magnification transmission electron micrograph, showing silver 2nm nanowires

9 is an electron micrograph showing a semiconductor memory device having nanowires according to an embodiment of the present invention;

10 is a cross-sectional view taken along the line VII-VII 'of FIG. 5,

FIG. 11 is a cross-sectional view taken along the line XXX 'of FIG. 5;

12 is a graph showing a current flowing in nanowires when -100mV to 100mV is applied as a source-drain voltage Vsd of a nanowire semiconductor memory device according to an experimental example of the present invention;

FIG. 13 is a graph showing a current flowing in nanowires when -10V to 10V is applied as a substrate bias of a nanowire semiconductor memory device according to an experimental example of the present invention; FIG.

14 is a graph showing the current flowing through the nanowires when -2V to 2V and -2V to -2V are respectively applied as the source / drain voltages of the nanowire semiconductor memory device according to the experimental example of the present invention;

FIG. 15 is a graph showing a current flowing through a nanowire when -3V to 3V and 3V to -3V are respectively applied as a source / drain voltage of a nanowire semiconductor memory device according to an experimental example of the present invention;

16 is a graph showing a current flowing through a nanowire when -1.5V to 1.5V is applied as a source / drain voltage (Vsd) of a nanowire semiconductor memory device according to an experimental example of the present invention;

FIG. 17 is a graph showing a current flowing through nanowires when -8V to 8V are respectively applied as a source / drain voltage of a nanowire semiconductor memory device according to an experimental example of the present invention; FIG.

18 is an electron micrograph of a nanowire semiconductor device showing a case in which the channel length of the nanowire is set to 5 μm or less, and

FIG. 19 is a graph showing current characteristics of a semiconductor device having a channel length of 5 μm or less as shown in FIG. 18.

<Explanation of symbols for the main parts of the drawings>

100: single crystal substrate 110: nanowires

200 element forming substrate 220 dielectric layer

230: sacrificial layer 240a, 240b: source and drain electrodes

The present invention relates to a semiconductor device, a semiconductor memory device having the same, and a manufacturing method thereof, and more particularly, to a semiconductor device having a channel layer of a nanowire structure, a semiconductor memory device having the same, and a manufacturing method thereof. .

In general, semiconductor memory devices for storing data may be classified into volatile and nonvolatile memory devices. Volatile memory devices lose their stored data when their power supply is interrupted, while nonvolatile memory devices retain their stored data even when their power supplies are interrupted. Therefore, they are widely used in mobile phone systems and memory cards for storing music and video data. .

The nonvolatile memory device may be classified into a floating gate type device, a charge trap type device, and an element having a phase change layer (phase change device) according to the type of the memory storage layer constituting the unit cell.

The floating gate type device and the charge trap type device may include a control gate, a charge storage layer (a floating gate or a charge trap layer), a source, and a drain. The floating gate type device and the charge trap type device are controlled to allow charge storage and erasure by a control gate. However, the floating gate type device and the charge trap type device require a predetermined area because a control gate occupying a predetermined area is required.

On the other hand, the phase change element is a device for storing information by using the electrical conductivity or resistance difference between the crystalline phase and the amorphous phase of a particular phase change material, a semiconductor for addressing (addressing) and read / write drive It consists of a memory cell of the type electrically connected to a transistor element formed on a substrate. Since the information is stored using the conductivity difference according to the phase change of the memory layer, the data is substantially stored in the phase change element part including the phase change region. However, the phase change memory device has a problem that the power consumption required for the operation is too large because the write operation, particularly the reset operation for changing the crystal phase to the amorphous phase, requires heating above the melting point of the phase change material. This problem is associated with the fact that the smaller the size of the transistor device driving the phase change memory device, the smaller the amount of power that can be transferred to the phase change memory device through the transistor device, thereby integrating the entire phase change device. It is also the most serious problem that is constrained.

Therefore, it is urgent to manufacture a nonvolatile memory device having a low power consumption while occupying a small area.

Accordingly, it is an object of the present invention to provide a semiconductor device capable of high integration and having low power consumption.

In addition, another object of the present invention is to provide a semiconductor memory device capable of high integration and low power driving.

Further, another object of the present invention is to provide a method of manufacturing the semiconductor memory device described above.

In order to achieve the above object of the present invention, the semiconductor device of the present invention includes a device forming substrate, a nanowire arranged on the device forming substrate, the source and drain electrodes disposed on the nanowire, spaced a predetermined distance apart do. In this case, a channel layer is formed on the nanowires by the voltage swing between the source and drain electrodes.

In addition, the semiconductor memory device according to another embodiment of the present invention, a device forming substrate having a dielectric layer on the surface, a plurality of nanowires arranged on the device forming substrate, respectively disposed on the plurality of nanowires, And source and drain electrodes spaced apart from each other by a predetermined distance on one nanowire, and silicide islands positioned at contact portions of the source and drain electrodes with the nanowires. At this time, the charge is captured and erased through the silicide island by the voltage applied to the semiconductor substrate and the voltage applied to the source / drain electrodes.

The nanowires are Si, Ge, Sn, Se, Te, B, C (including diamond), B-Si, Si-C, Si-Ge, Si-Sn, Ge-Sn, SiC, BN / BP / BAs, AIN / AlP / AlAs / AlSb, GaN / GaP / GaAs / GaSb, InN / InP / InAs / InSb, ZnO / ZnS / ZnSe / ZnTe, CdS / CdSe / CdTe, HgS / HgSe / HgTe, BeS / BeSe / BeTe / MgS / MgSe, GeS, GeSe, GeTe, SnS, SnSe, SeTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, CuI, AgF, AgCl, AgBr, AgI, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSn2 ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag) (Al, Ga, In, Tl, Fe) (S, Se, Te) 2, Si3N4, Ge3N4, Al2O3, (Al, Ga, In) 2, (S, Se , Te) 3 and Al2CO may be a single crystal layer of one selected.

The device forming substrate may be a Si / SiO 2 substrate, and the source and drain electrodes may be composed of a single transition metal film or a multilayer transition metal film.

The source electrode and the drain electrode are preferably spaced apart from 5μm to 100μm, and the silicide island preferably includes both the components constituting the source and drain electrodes and the nanowire component.

Meanwhile, a method of manufacturing a semiconductor memory device according to another aspect of the present invention is as follows. First, nanowires are formed on a first substrate, and then nanowires formed on the first substrate are distributed on a second substrate. Subsequently, a source and a drain electrode are formed on the nanowire, and a silicide island is formed at a contact portion between the nanowire and the source and drain electrode.

In this case, the first substrate may be a single crystal substrate.

The forming of the nanowires may include forming a precursor on the first substrate, and supplying a reaction source on the first substrate on which the precursor is formed for a predetermined time to generate nanowires by chemical vapor deposition. It may include. In this case, the reaction source may include a germanium containing gas and / or a silicon containing gas.

In addition, distributing the nanowires on the second substrate may include preparing a second substrate having a dielectric layer coated on a surface thereof, separating the nanowires from the first substrate, and ethanol treatment on the second substrate. And dispersing and fixing the nanowires.

The forming of the source and drain electrodes may include applying a sacrificial layer on the second substrate on which the nanowires are distributed, and selectively removing the sacrificial layer to expose the source and drain electrode predetermined regions of the nanowires. The method may include forming a source and drain electrode on the sacrificial layer, and removing the sacrificial layer by a lift-off method to form the source and drain electrodes. In this case, the sacrificial layer may be a resist, and selectively removing the sacrificial layer may include exposing the sacrificial layer corresponding to the source and drain predetermined region by electron beam exposure, and developing and removing the exposed sacrificial layer. It may include a step.

In addition, the forming of the silicide island may include heat treating the source and drain electrodes to react with the nanowires.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

The present invention provides a semiconductor device and a semiconductor memory device using a nanowire as a channel layer or a charge storage layer. A semiconductor device having such a nanowire forms a source / drain electrode on the nanowire, and forms a silicide metal island on the nanowire through heat treatment between the source / drain electrode and the nanowire. The silicide island will serve to capture charge of the nanowires when voltage is applied from the source / drain electrodes to form a channel layer and a charge storage layer. Since a semiconductor device having such a nanowire does not require a separate gate electrode, a voltage applied to the gate electrode is also not required. Therefore, since the area of the gate electrode is not required and the gate voltage is not required, low power operation will be possible.

In the present embodiment, the semiconductor device and the semiconductor memory device having the nanowires have almost the same configuration, and depending on the application range of the source / drain voltage, it will be determined whether to operate as a channel layer or a charge storage layer. For example, if a channel for conducting the source electrode and the drain electrode is formed by the voltage of the source drain, it will be regarded as a semiconductor element, and if the charge is written to the source side or part of the drain side by the voltage applied to the source / drain. It will be considered as a semiconductor memory device. The voltage application range may be varied by the shape (diameter) of the nanowires, the distance between the source drain electrodes, and the line width.

In addition, while the present embodiment will refer to nanowires, the techniques described herein are applicable to other nanostructures, such as nanorods, nanotubes, nanonotetrapods, nanoribbons, and / or combinations thereof. It will also be appreciated that the fabrication techniques described herein can be used to generate any semiconductor device type and other electronic component types. In addition, these techniques will be suitable for electrical systems, optical systems, household appliances, industrial electronics, wireless systems, or any other application.

In addition, the "nano structure" used in the present invention is a structure having a diameter of less than 500 nm, for example, less than 200 nm, less than about 50 nm and even less than 20 nm. In general, the area or feature size is determined along the shortest axis of the structure. Examples of such structures include nanowires, nanorods, nanotubes, branched nanocrystals, nano tetrapods, nanotripods, bipods, nanocrystals, nanodots, quantum dots ), Nanoparticles and branched tetrapods. In addition, such nanostructures may be substantially homogeneous or heterogeneous in material properties, and may consist of crystalline, substantially single crystals.

In addition, the term “nanowire” as used herein may refer to any elongated semiconducting material having a diameter generally less than 500 nm and an aspect ratio (length: width) greater than about 10.

A semiconductor device having such a nanowire as a channel layer or a charge storage layer will be described in detail with reference to the accompanying drawings.

As shown in FIG. 1, a single crystal semiconductor substrate 100 is prepared. Si, SiGe, or Ge may be used as the single crystal semiconductor substrate 100. The single crystal semiconductor substrate 100 may be subjected to a buffered oxide etchant (BOE) treatment to remove a natural oxide film (not shown) that may be generated on the surface thereof.

Next, the nanowires 110 are grown on the single crystal semiconductor substrate 100. In this case, since the nanowires 110 are formed on the single crystal semiconductor substrate 100, they are grown in a single crystal state.

Such nanowires 110 may have a nanoscale of a precursor, for example, an Au precursor, on the single crystal semiconductor substrate 100 so as to be manufactured, for example, by a vapor-liquid-solid (VLS) mechanism. Deposited by sputtering method. In this case, the size of the quantum dot of the precursor is preferably about 20 to 30 nm. The substrate 100 on which the Au precursor is deposited is inserted into a horizontal reaction tube, and a reaction source, such as a Ge source and a Si source, is injected by a chemical vapor deposition method, and processed at a temperature range of about 600 to 700 ° C. to form a SiGe nanowire ( 110). The SiGe nanowires 110 may be formed in a shape perpendicular to the single crystal semiconductor substrate 100 as shown in the drawing, for example, having a diameter of 500 nm to 1 nm, more preferably 50 nm to less than 1 nm. It may have a fine cylindrical shape.

In this case, the SiGe nanowires 110 may be formed by using GeCl 4 as the Ge source and reacting for 30 minutes while maintaining the temperature of the reaction chamber at 550 to 650 ° C. while supplying SiCl 4 as the Si source.

In addition, instead of using the SiGe nanowires 110, only SiCl 4 may be supplied without supplying the Ge source, and the Si nanowires may be formed by reacting for 30 minutes while maintaining the temperature of the reaction chamber at 650 to 750 ° C. .

6 to 8 are photographs showing nanowires formed in accordance with an embodiment of the present invention, FIG. 6 is an electron micrograph showing a wire having a diameter of 50 μm, and FIG. 7 is a transmission electron micrograph showing a nanowire having a diameter of 200 nm. 8 is a scanning electron micrograph showing a 2 nm diameter nanowire. It can be seen that the nanometer wires of FIGS. 7 and 8 are free of defects compared to the micrometer wires of FIG. 6 and have a complete crystalline form. The shape and composition of the nanowires 110 may be controlled by the amount and reaction time of a reaction source, for example, a Ge source.

Referring to FIG. 2, the nanowires 110 formed on the single crystal substrate 100 are dispersed and fixed on the substrate 200 on which the device is to be formed. That is, the nanowires 110 are separated from the single crystal substrate 100 and dispersed and fixed on the element formation substrate 200 by ethanol treatment. In addition, the worker may check the position of the nanowires 110 distributed on the element formation substrate 200 by ethanol treatment. In this case, the device forming substrate 200 is insulated from the nanowires 110, and a dielectric film 220 is provided on a surface thereof to provide a smooth transistor operation thereafter. In this embodiment, for example, a multilayer structure substrate of Si (210) / SiO 2 220 is used as the element formation substrate 200.

Referring to FIG. 3, the sacrificial layer 230 is formed on the element formation substrate 200 so that the source / drain predetermined regions S and D may be exposed. For example, a resist material may be used as the sacrificial layer 230. Selective opening of the source / drain predetermined regions S and D by the sacrificial layer 230 may be achieved by an electron beam lithography process. That is, the sacrificial layer 230 is coated on the entire surface of the device formation substrate 200 on which the nanowires 110 are formed, and then an electron beam is applied to a portion corresponding to the source / drain predetermined regions S and D. Irradiate and expose. Next, by developing the exposed portion, only the source / drain predetermined regions S and D are opened. In this case, 4% of a copolymer / PMMA may be used as the resist material used as the sacrificial layer 230, and a MIBK: IPA = 1: 1 solution may be used as a developer. .

Next, in order to remove a natural oxide film (not shown) that may be generated on the exposed nanowire 110 surface, it is treated with a BOE solution as described above or immersed in a 3% HF solution for 5 to 20 seconds. The oxide film can be removed.

An electrode layer is deposited on the element formation substrate 200 on which the sacrificial layer 230 is formed. For example, the electrode layer may be formed of a laminated film of a Ni layer of 100 to 200 nm and an Au layer of 10 to 100 nm, and the electrode layer may be formed by an electron beam deposition method. Thereafter, the sacrificial layer 230 positioned below the electrode layer is removed with an acetone solution at a temperature of about 40 to 60 ° C. to lift off the electrode layer on the sacrificial layer 230. Accordingly, as illustrated in FIG. 4, source / drain electrodes 240a and 240b are formed in the source / drain predetermined regions S and D in which the sacrificial layer 230 is not formed. At this time, the source / drain electrodes 240a and 240b may be spaced at intervals of 5 μm or more, preferably 5 μm to 100 μm.

9 is an electron micrograph showing the source / drain electrodes 240a and 240b formed by the lift-off method as described above. 9, it can be seen that source / drain electrodes 240a and 240b are spaced apart from each other at both edges of the nanowire 110.

Next, in order to reduce the contact resistance of the nanowires 110, as shown in FIG. 5, the resultant of the device forming substrate 200 is heat-treated. The heat treatment is performed for about 5 to 15 minutes in a furnace at a temperature of 200 ℃ to 400 ℃ having an Ar atmosphere. Alternatively, the heat treatment may be rapid heat treatment for 30 to 60 seconds in a rapid heat treatment chamber at 350 ° C. to 450 ° C. having a vacuum or nitrogen atmosphere.

By the heat treatment process, silicide islands 150 are formed on portions of the nanowires 110 overlapping the source / drain electrodes 240a and 240b, as shown in FIGS. 5 and 10. The silicide island 150 may then capture charges using nanocrystals (in a similar principle to floating gates) when applying source / drain voltages to erase and store charges, or to cause channels depending on the magnitude of the applied voltage. Can be.

The operation of the nanowire device having such a structure will be described.

Referring to FIG. 11, when a predetermined voltage is applied to the source / drain electrodes 240a and 240b on the nanowires 110, the nanowires 110 may be formed by the source-drain electrodes 240a and the voltage ranges. As a channel between 240b) or the charge provided from the electrodes 240a and 240b by the nanocrystals of the silicide island 150 are stored, the memory operation is performed. This memory operation can be written and erased by voltages applied to the source / drain electrodes 240a and 240b and the substrate 200, similarly to general nonvolatile memory devices.

Here, in the case where the silicide film is generally formed by the metal electrode on the thin film provided on the upper surface of the semiconductor substrate, even though the silicide metal islands formed at the contact interface between the electrode and the thin film are formed because the entire thin film serves as a conducting channel, The effect has little effect on the flow of conduction.

On the other hand, when using nanowires as in the embodiment of the present invention, since the diameter of the conductive channel is very small within 50 nm, the formation of silicide islands generated at the interface contact portion with the source / drain electrodes has a great influence on the overall conduction flow. Memory operation is observed.

In addition, in the case of the conventional thin film, a large amount of defects may be found because stress and deformation are already applied due to structural and thermal differences from the device forming substrate 200. Such stresses, strains, and defects cancel the interface effect between the electrode and the thin film.

However, the nanowires 110 according to the present exemplary embodiment are grown with the influence of the substrate minimized, and are placed in a free standing state by the dielectric 210 even when the device is fabricated. The device fabricated as a base is in a materially relaxed state without the influence of the substrate. Therefore, memory operation is observed by the silicide islands inside the nanowires.

Experimental Example 1

Referring to FIG. 11, a voltage of -100 mV to 100 mV was swinged on the source / drain electrodes 240a and 240b and −10 V was applied to the substrate voltage VBB.

Then, as shown in FIG. 12, when the charge is captured from the silicide island 150 and the source / drain voltage Vsd increases from −100 mV to 100 mV, the nano wire 110 flows through the nano wire 110. It can be seen that the current gradually increases from -180nA to 130nA in proportion to the source / drain voltage. On the other hand, when 10V is applied as the substrate bias VBB, no current is generated as shown in FIG. Through this graph, it can be predicted that the nanowire of the present embodiment has the same operation and memory characteristics as the PMOS transistor.

FIG. 13 is a graph showing the current flowing through the nanowires relative to the substrate voltage. In the period of -10V to 0V, the substrate bias VBB generates a current based on the source / drain voltage Vsd, and the substrate bias VBB. ) Shows that there is no current flow in the nanowire in the positive section, that is, the 0V to 10V section.

Experimental Example 2

FIG. 14 is a graph illustrating a current state of nanowires when −2V to 2V and 2V to −2V are respectively applied as a source / drain voltage Vsd of a nanowire semiconductor device according to an embodiment of the present invention. Is a graph showing the current state of the nanowires when -3V to 3V and 3V to -3V are respectively applied as the source / drain voltage (Vsd) of the nanowire semiconductor device according to the embodiment of the present invention. Here, the nanowires were SiGe nanowires having a Ge content of 5%.

First, as shown in FIG. 14, when -2V to 2V is applied as the source / drain voltage Vsd, the current of the nanowire is gradually increased, and the source / drain voltage Vsd is 2V. When the current is reduced to -2V, the current of the nanowire also gradually decreases to perform the memory operation.

Similarly, even if the source / drain voltage Vsd is increased to -3V to 3V and 3V to -3V, the swing range of the voltage shows the same result as shown in FIG. 15. However, in the case of FIG. 15, the current rise time may be required to charge the voltage when the voltage swings from -3V to -2V due to the expansion of the swing range of the voltage. However, as shown in FIG. 14, the memory operation is performed. can do.

Experimental Example 3

FIG. 16 is a graph showing a current state of nanowires when −1.5 V to 1.5 V is applied as a source / drain voltage Vsd of a nanowire semiconductor device according to an embodiment of the present invention, and FIG. 17 is a graph of the present invention. When the -8V to 8V are respectively applied as the source / drain voltage (Vsd) of the nanowire semiconductor device according to the embodiment, it is a graph showing the current state of the nanowires. Here, as the nanowires, Si 0.7 Ge 0.3 alloy nanowires in which silicide islands 150 were formed by the rapid heat treatment method were used.

16 and 17, graphs show that the memory / drain voltage Vsd performs a reproducible memory operation when both swinging from a relatively narrow -1.5V to 1.5V or swinging a relatively wide -8V to 8V. Can be.

Experimental Example 4

18 is an electron micrograph showing a case where the channel length of the nanowire is set to 5 μm or less. As shown in FIG. 18, when the channel length, that is, the length between the source / drain electrodes 240a and 240b is 5 μm or less, the channel between the source / drain electrodes 240a and 240b simultaneously with the heat treatment and the application of the source / drain voltage is shown in FIG. 20. As shown in FIG. 2, conduction occurs. Therefore, such a semiconductor device having a short channel nanowire can be used as a switching device rather than a memory device.

The present invention is not limited to the above embodiments. In the present invention, SiGe nanowires or Si nanowires were used as the nanowires, but are not limited thereto, and Ge, Sn, Se, Te, B, C (including diamonds), B-Si, Si-C, Si-Sn , Ge-Sn, SiC, BN / BP / BAs, AIN / AlP / AlAs / AlSb, GaN / GaP / GaAs / GaSb, InN / InP / InAs / InSb, ZnO / ZnS / ZnO / ZnTe, CdS / CdSe / CdTe , HgS / HgSe / HgTe, BeS / BeSe / BeTe / MgS / MgSe, GeS, GeSe, GeTe, SnS, SnSe, SeTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, CuI, AgF, AgCl, AgBr , AgI, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag) (Al, Ga, In, Tl, Fe) (S, Se, Te) 2, Si3N4, Ge3N4, Al3 It can be obtained from (Al, Ga, In) 2, (S, Se, Te) 3 or Al 2 CO.

In this embodiment, although a Ni / Au film is used as the source / drain electrode pattern, a transition metal film capable of forming silicide through heat treatment with the nanowires, for example, transition metals such as Ti, Pt, Ta, Cu, etc. All acts are included here, of course.

In addition, in the present embodiment, a heat treatment through a furnace and a rapid heat treatment method are employed as a method for forming silicide islands. However, the present invention is not limited thereto, and the reaction may be performed while improving the contact resistance between the metal film and the nanowires, such as laser heat treatment. Any method that can be derived is included in the present invention.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. .

As described in detail above, according to the present invention, source / drain electrodes are formed at predetermined intervals on semiconductor nanowires having nano diameters. When the heat treatment is performed to increase the contact resistance between the nanowires and the source / drain electrodes, silicide islands are formed to trap electric charges at the contact portions of the nanowires and the source / drain electrodes. Such silicide islands can trap or erase charges by appropriate voltage application of the source / drain electrodes, and can also be utilized as channel layers, and thus can be used as semiconductor devices and even as next-generation semiconductor memory devices.

In addition, since the nanowire device of the present invention does not require a separate gate electrode and a gate voltage applied thereto, it is possible to perform low power driving and to secure a pattern margin.

Claims (23)

An element formation substrate; Nanowires arranged on the device formation substrate; Source and drain electrodes disposed on the nanowires and spaced apart from each other by a predetermined interval; And A silicide island formed at a contact portion of the source and drain electrodes with the nanowire, The nanowire surface between the source and drain electrodes is exposed, And a channel layer formed on the nanowires by the voltage swing between the source and drain electrodes. The method of claim 1, wherein the nanowires are Si, Ge, Sn, Se, Te, B, C (including diamond), B-Si, Si-C, Si-Ge, Si-Sn, Ge-Sn, SiC, BN / BP / BAs, AIN / AlP / AlAs / AlSb, GaN / GaP / GaAs / GaSb, InN / InP / InAs / InSb, ZnO / ZnS / ZnSe / ZnTe, CdS / CdSe / CdTe, HgS / HgSe / HgTe, BeS / BeSe / BeTe / MgS / MgSe, GeS, GeSe, GeTe, SnS, SnSe, SeTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, CuI, AgF, AgCl, AgBr, AgI, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag) (Al, Ga, In, Tl, Fe) (S, Se, Te) 2, Si3N4, Ge3N4, Al2O3, (Al, Ga, In) 2, (S, Se, Te) 3 and Al 2 CO is a semiconductor device. delete The semiconductor device of claim 1, wherein the device forming substrate is a semiconductor substrate having a dielectric film on a surface thereof. The semiconductor device of claim 1, wherein the source and drain electrodes are a single transition metal film or a multilayer transition metal film. The semiconductor device of claim 1, wherein the source and drain electrodes are spaced apart from 5 μm to 100 μm. An element formation substrate having a dielectric layer on a surface thereof; A plurality of nanowires arranged on the element formation substrate; Source and drain electrodes disposed on the plurality of nanowires, respectively, and spaced apart from each other by a predetermined distance; And A silicide island located at a contact portion of the source and drain electrodes with the nanowire, Charges are captured and erased through the silicide island by a voltage applied to the element formation substrate and a voltage applied to the source / drain electrodes. The method of claim 7, wherein the nanowires are Si, Ge, Sn, Se, Te, B, C (including diamond), B-Si, Si-C, Si-Ge, Si-Sn, Ge-Sn, SiC, BN / BP / BAs, AIN / AlP / AlAs / AlSb, GaN / GaP / GaAs / GaSb, InN / InP / InAs / InSb, ZnO / ZnS / ZnSe / ZnTe, CdS / CdSe / CdTe, HgS / HgSe / HgTe, BeS / BeSe / BeTe / MgS / MgSe, GeS, GeSe, GeTe, SnS, SnSe, SeTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, CuI, AgF, AgCl, AgBr, AgI, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu, Ag) (Al, Ga, In, Tl, Fe) (S, Se, Te) 2, Si3N4, Ge3N4, Al2O3, (Al, Ga, In) 2, (S, Se, Te) 3, and a semiconductor memory device which is a single crystal layer of one selected from Al2CO. 8. The semiconductor memory device of claim 7, wherein the element formation substrate is a Si / SiO2 substrate. 8. The semiconductor memory device according to claim 7, wherein the source and drain electrodes are composed of a single transition metal film or a multilayer transition metal film. The semiconductor memory device of claim 10, wherein the source electrode and the drain electrode are spaced apart from 5 μm to 100 μm. The semiconductor memory device of claim 10, wherein the silicide island comprises both a material constituting the source and drain electrodes and a material constituting the nanowires. Forming nanowires on the first substrate; Distributing nanowires formed on the first substrate on a second substrate; Forming a source and a drain electrode on the nanowire; And Forming a silicide island at a contact portion of the nanowire with a source and a drain electrode. The method of claim 13, wherein the first substrate is a single crystal substrate. The method of claim 13, wherein forming the nanowires, Forming a precursor on the first substrate; And And supplying a reaction source on the first substrate on which the precursor is formed for a predetermined time to generate nanowires by chemical vapor deposition. The method of claim 15, wherein the reaction source is germanium containing gas or silicon containing gas. The method of claim 13, wherein distributing the nanowires to the second substrate comprises: Preparing a second substrate coated with a dielectric layer on a surface thereof; Separating the nanowires from the first substrate; And Method of manufacturing a semiconductor memory device comprising the step of dispersing and fixing the nanowires by ethanol treatment on the second substrate. The method of claim 13, wherein the forming of the source and drain electrodes comprises: Applying a sacrificial layer on the second substrate on which the nanowires are distributed; Selectively removing the sacrificial layer to expose source and drain electrode predetermined regions of the nanowires; Forming conductive layers for source and drain electrodes on the sacrificial layer; And Removing the sacrificial layer by a lift-off method to form a source and a drain electrode. The method of claim 18, wherein the sacrificial layer is a resist. The method of claim 19, wherein selectively removing the sacrificial layer, Exposing the sacrificial layer to an electron beam such that predetermined regions of the source and drain electrodes are exposed; And And developing and removing the exposed sacrificial layer. The method of claim 13, wherein forming the silicide island is And heat treating the source and drain electrodes to react with the nanowires. The method of claim 21, wherein the heat treatment is performed for 5 to 15 minutes in a furnace at 200 ° C. to 400 ° C. having an Ar atmosphere. The method of claim 21, wherein the heat treatment is performed in a rapid heat treatment chamber at 350 ° C. to 450 ° C. having a vacuum or nitrogen atmosphere for 30 to 60 seconds.
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