JP4162280B2 - Memory device and memory array circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory device capable of large-scale integration for manufacturing a memory cell array.
[0002]
[Background Art and Problems to be Solved by the Invention]
In a conventional semiconductor memory, 1-bit information is represented by a group of electrons stored in a static capacitor in each memory cell. The binary number “1” is represented by a shortage of N electrons, and “0” is represented by a neutral charge state. In a typical 16 Mbit dynamic random access memory (DRAM), the number of electrons N is about 800,000. In order to increase the memory capacity, it is necessary to reduce the size of each memory cell, but this cannot be achieved only by reducing the size of the conventional memory cell. This is because the value of N has a lower limit. The number of electrons N is limited by the need to accept the effects of leakage current from the cell, internal noise, and incident alpha particles. These factors do not decrease in proportion to the reduction in the area of the memory cell. For a 16 Gbit DRAM, N can be estimated to be more than 130,000 (which corresponds to about one sixth of that for a 16 Mbit DRAM). However, the cell size required for the 16 Gbit DRAM needs to be reduced at a rate of three digits compared to the 16 Mbit DRAM. Therefore, this reduced cell size cannot accommodate the number of electrons required for satisfactory operation. In an attempt to keep the value of N large enough, three-dimensional capacitors with trenches or deposited structures and high dielectric capacitor films have been studied, but the proposed structure and manufacturing process obtained thereby are extremely complex. Become. In addition, power consumption increases significantly. This is because a relatively large number N of electrons in the cell need to be refreshed within the storage time (which tends to be shorter as the device scales down).
[0003]
Another type of memory device is known as flash memory that exhibits non-volatility. In such devices, SiO having a thickness typically on the order of 10 nm.₂About 10 5 electrons are injected into the floating gate through the tunnel barrier formed by. This accumulated charge forms an electric field that affects the current flowing in the source-drain path. By applying an electric field through the control gate, charge is written to the floating gate or erased from the floating gate. A relatively high electric field is applied during erase and write cycles, resulting in SiO₂The film degrades and the memory lifetime is limited to a predetermined number of erase / write cycles (typically on the order of 10 5 cycles). Furthermore, typical erase / write times are a few milliseconds, which is four orders of magnitude slower than that of conventional DRAMs. Such low characteristics limit the application of flash memory devices.
[0004]
So far, other techniques have been employed to provide memory devices that operate with a small and accurate number of electrons, known as single-electron memory devices. A single electronic memory device is disclosed in the applicant's PCT / GB93 / 02581 (WO-A-94 / 15340). Under the control of the applied gate voltage, the correct number of electrons pass through the multiple tunnel junctions into and out of the memory node, and the electronic state of the memory node is detected by an electrometer. The However, the disadvantage of this device is that each memory node requires a significant amount of circuitry, and this device currently only operates at low temperatures (liquid helium temperature 4.2 K or lower). Other single-electron memory devices are described in IEEE Transactions on Electron Devices, September 1994, Vol. 41, No. 9, pp. 1628-1638, K. Yano, T. Ishii, T. Hashimoto, T. Kobayashi, F. Murai and By K.Seki and at IEEE International Solid-State Circuits Conference, 1996, FP16.4, P.266, by K.Yano, T.Ishii, T.Sano, T.Mine, F.Murai and K.Seki, Proposed and documented. This device uses a polycrystalline film extending between a source and a drain to which a gate voltage is applied. A small number of electrons are accumulated in the granular structure of the polycrystalline silicon film. This memory size is relatively small compared to the structure of PCT / GB93 / 02581 described above and can operate at room temperature. Moreover, this memory has several advantages over conventional memories. That is, erasing / writing is faster due to a small number of stored electrons and low-volgate tunnel injection is used rather than high-field electron injection. This extends the operating life. However, the time for reading the stored information is relatively long, on the order of a few microseconds. This is because the resistance between the source and the drain needs to be sufficiently high in order to guarantee a long accumulation time of electrons in the grains.
[0005]
Other structures are described in Applied Physics Letters, 4 March 1996, Vol 68, No. 10, pp.1377-1379 by S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, EFCrabbe and K. Chan. Also, in Applied Physics Letters, 26 August 1996, Vol 69, No. 9, pp.1232-1234 by S. Tiwari, F. Rana, K. Chan, L. Shi and H. Hanafi, HIHanafi, S IEEE Transactionson Electron Devices, 9 September 1996, Vol 43, No. 9, pp1553-1558 by .Tiwai and I.Khan. This memory device uses silicon nanocrystals located under the gate of the transistor device. Electrons are injected into the silicon nanocrystals (5 nm in size) from the silicon substrate through a thin tunneling oxide layer on the order of 1.1-1.8 nm. The accumulated electrons shift the threshold voltage of the transistor. The time for reading the stored information is relatively short, on the order of tens of nanoseconds. This is because the transistor channel has a high electron mobility. The endurance cycle for writing and reading information is significantly improved compared to conventional flash memory devices. However, the erase time is unacceptably long, on the order of a few milliseconds. This is because the conduction band alignment is not so favorable that electrons pass from the nanocrystal to the bulk silicon.
[0006]
Other memory devices that operate according to the principle of flash memory are described in IEEE Electron Device Letters, Vol. EDL-1, No. 9, September 1980, pp.179-181, Electrically-Alterable by DJDiMaria, KMDeMeyer, and DWDong. It is described in Memory Using a Dual Electron Injector Structure. In this device, the conductivity of the source / drain path is controlled by the charge written or erased from the floating gate through the tunneling barrier from the gate electrode. However, the disadvantages of this device are that the write / erase time is slow (on the order of milliseconds) and the lifetime of the tunnel barrier is limited. This is because Fowler-Nordheim high electric field injection is used as in the case of the conventional flash memory.
[0007]
In order to overcome these problems and drawbacks, the present invention is intended to store a charge for generating a path for charge carriers and an electric field that alters the conductivity of the path.Charge accumulationNoDoWhen,Electrodes,Charge carriers in response to a given voltageFrom the electrodeSaidCharge accumulationAccumulate in nodeOr discharged from the charge storage node to the electrodeTunnel barrier structure that passes throughConstructionA memory device is provided. This tunnel barrier structure isSuppress the joint tunneling effectHas a high barrier heightShiAt least one dimensionally narrowFirstBarrier formationMinWhen,Compared to the first barrier component for inelastic scattering of electronsHas a low barrier heightShiDimensionally wideSecondBarrier formationMinAnd exhibiting an energy band profile.
[0008]
The present invention can optimize all of the memory device write, read and erase times.
[0009]
The barrier component having a relatively wide energy band profile serves as a barrier for accumulating charge on the node for a long time. The wide barrier component can be selectively raised or lowered so that charge is written to or erased from the node through the relatively narrow barrier component.
[0010]
The component of the energy band profile with a relatively high barrier height is provided by elements with a width of 3 nm or less. It may have a plurality of relatively high barrier components, which advantageously form a multi-tunnel junction structure.
[0011]
thisMultiple tunnel junctionThe structure can be manufactured by various methods. this is,ElectricAlternate layers of air conductive and insulating materials may be included. These layers generally have an energy band profile,LowHigh barrier height component and individual insulation layersHighIt brings about a barrier component. The alternating layers can be composed of polysilicon and silicon nitride, respectively, but other materials can be used.
[0012]
Instead of thisMultiple tunnel junctionThe structure may be constituted by a Schottky barrier with alternating layers of electrically conductive material and semiconductor material.
[0013]
The charge storage node can be constituted by a layer of electrically conductive material between the barrier structure and the path. This node may be composed of a plurality of conductive islands. As an alternative to these, islands can be interspersed within the barrier structure and their charge energy can result in the relatively low barrier component of the energy band profile. These islands have a diameter of 5 nm or less. These islands may be arranged in a plurality of layers separated by an insulating material.
[0014]
The islands can be formed by several different methods. The island can be composed of nanocrystalline semiconductor material. Alternatively, the islands can be made of metal, for example by sputtering, so as to be interspersed within the insulating metal oxide. Further, it may be constituted by particles precipitated from a colloidal solution of metal or semiconductor particles.
[0015]
The tunnel barrier structure is disposed between the path and the control electrode, and the amount of charge passing through the charge storage node can be controlled by changing the voltage of the control electrode. In another configuration of the invention, a gate electrode is provided, thereby controlling the charge passing through the node by applying an additional electric field to the charge barrier structure.
[0016]
The amount of charge that can be stored in a node is limited to a discrete number of electrons by the Coulomb blockade effect.
[0017]
In use, the tunnel barrier structure exhibits a blocking voltage range in which charge carriers passing through the node are blocked, and a control means is provided for increasing or decreasing the blocking voltage range to control the amount of charge accumulated in the node. . The amount of charge that can be stored at a node is limited to multiple distinct electronic states. The control means operates to increase or decrease the blocking voltage range so that only one selected of those states exists at the node.
[0018]
Alternatively, the control means may operate to change the width of the voltage blocking range.
[0019]
The memory device according to the present invention is suitable for manufacturing as an array of rows and columns on a conventional substrate.
[0020]
Data can be selectively read from individual cells, new data can be written to the cells, or the stored data can be refreshed. This memory cell array precharges a sense line for detecting a current flowing in a path of each column of memory cells, a word line, a data line for controlling the barrier structure of the memory cell in each column, and the sense line. The sense line is stored in a charge storage node of a specific one cell of the cells in the column, which is read in response to a read voltage applied to the corresponding word line. The memory cell array further includes a read / write circuit that transfers the voltage level of the sense line to the corresponding word line of the column, and the data level in response to the voltage level of the data line. Data output for generating output data corresponding to the data stored in the read cell, and the word line of the read cell By applying a write voltage and a data refresh means so that data corresponding to the voltage level on the data line is written back to the previous read cell. The array also includes means for writing the input data into the cell by changing the voltage level on the data line after operation of the read / write circuit in response to the input data to be written into the cell. You may have.
[0021]
The peripheral circuit of this array can be formed on the same substrate as the memory cell, and the source and drain of the transistors in the peripheral circuit are the same process used to form the source and drain regions in the cells of this array. It can be formed by steps.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
In order that the present invention may be more fully understood, embodiments of the present invention will now be described by way of example with reference to the accompanying drawings.
[0023]
In the following description, embodiments of the memory device according to the present invention can be classified into three different types.
[0024]
Type 1
FIG. 1 shows a schematic configuration of a first type memory device according to the present invention. Memory node 1 and barrier structure 2 are integrated in the control electrode of a field effect transistor having source connection S and drain connection Y and control electrode connection X. When storing information, the charge carriers pass through the barrier structure 2 to the memory node 1 and the device acts as a storage capacitor. As a result, charge is held at the node 1. To read the information, the conductivity of the source / drain paths S, Y is monitored. This conductivity varies between a relatively high conduction state and a low conduction state depending on the level of charge stored in the memory node 1.
[0025]
FIG. 2 shows the current-voltage characteristics of the barrier structure 2. Here, V is a memory node voltage. The electron current I passing through the barrier structure from the connection X has a threshold voltage of ± V_CBlocking range V between_BIs strongly deterred. However, outside this blocking voltage range, depending on the polarity of the bias voltage Vx applied to the connection X, charge carriers can pass through or through the barrier structure to or from the memory node 1. The barrier structure can be regarded as a multiple tunnel junction in which two or more tunnel junctions are connected in series.
[0026]
The memory device shown in FIG. 1 is in an array of memory devices arranged in a matrix as shown in FIG. 3 with associated word lines X1, X2, etc. and bit lines S1, Y1, etc .; S2, Y2, etc. Can be used as one memory cell. In other words, this array has memory cells Mmn. Here, m and n represent the number of rows and columns, respectively.
[0027]
First embodiment
The structure of the first embodiment of the memory cell Mmn will be described with reference to FIG. 4, FIG. 5, and FIG. FIG. 4 is a plan view of the memory cell, and FIGS. 5 and 6 are cross-sectional views of the cell M11 taken along lines A-A 'and B-B' in FIG. 4, respectively.
[0028]
As shown in FIG. 5, the device is formed on a substrate 3. In this example, the substrate 3 is made of a p-type semiconductor substrate, and the conduction path 4 is n.⁺It extends between the source 5 and the drain 6. SiO₂Insulating region 7 separates the cell from neighboring cells in the array. The substrate is insulating SiO₂Covered by layer 8. The memory node 1 and the covered tunnel barrier structure 2 are formed in a region surrounded by the layer 8. The conduction control electrode 9 covers the tunnel barrier structure 2. This control electrode 9 forms a word line X1 extending along the rows of the array. Source region 5 and drain region 6 form bit lines S1, Y1 extending along the columns of the array shown in FIG. It will be appreciated that other cells in the array also have corresponding word lines and bit lines.
[0029]
The memory node 1 consists of nanometer-scale dots or grains that limit the number of electrons that can be stored by charging through the barrier structure 2 (resulting in a uniform electric field in the lateral direction of the node).
[0030]
Hereinafter, the process of selectively writing and reading data in the memory cell M11 will be described with reference to FIGS. In this process, the word line X1 and bit lines S1, Y1 associated with memory cell M11 are activated while the other word lines and bit lines are grounded. When information is written to M11, positive peak Vx^(w)And negative peak-Vx^(w)Is applied to the word line X1. When "0" is written, the height V_Y ^(w)Positive voltage pulse is applied to the bit lines Y1, S1. On the other hand, when “1” is written, the peak voltage −V_Y ^(w)Is applied to the bit lines Y1, S1. These pulses need to overlap for a period of time ΔT. For example, Vx^(w)= 1.2V, V_Y ^(w)= 1.8V, and ΔT = 10 nsec.
[0031]
In FIG. 8, the number of electrons that can exist in the memory node 1 is limited by the size of the voltage blocking region of the tunnel barrier structure 2. That is, the node voltage cannot exceed ± Vc. In FIG. 8 (a), the binary data bit “1” is represented by the positively charged state 11 (depletion of electrons) on the memory node 1, and “0” is negatively charged on the node 1. It is represented by state 12 (excess of electrons). In this example, the memory node voltages in the “1” and “0” states are + 0.4V and −0.4V, respectively. A process of writing “0” to the node 1 will be described with reference to FIGS. Where V_SY= V_S= V_YAnd the black dot represents the final electronic state that occurs at each step. As shown in FIG. 8A, the positive voltage V_Y ^(w)When (1.8V) is applied to the bit line S1, Y1, the two states 11 and 12 are respectively pointed along the line of constant electrons on the memory node as shown in the following equation: 1.6V) and move to point 14 (0.8V).
[0032]
V = (Cg / C_Σ) V_SY+ V₀                      (1)
Where C_ΣIs the total capacity of the memory node, Cg is the capacity between the memory node and the terminals Y1 and S1, V₀Is V_SYMemory node voltage when = 0 (−C_ΣV₀/ Q is the number of excess electrons on the memory node. Here, q is an elementary charge. In this embodiment, C_Σ/Cg=1.5.
[0033]
As shown in FIG. 8B, the negative voltage −Vx^(w)When (-1.2V) is applied to the word line X1, the blocking region V_BShift as shown. And state 13 shifts to state 14. This is because state 13 goes outside the blocking area but cannot exist here.
[0034]
As shown in FIG. 8C, the positive voltage Vx^(w)When (1.2 V) is applied to the word line X1, this state is maintained. Thereafter, as shown in FIG. 8D, the word line and the bit line are grounded, and the state 14 shifts to the “0” state 12 along the line of a certain number of electrons on the memory node 1.
[0035]
Note that any electronic state between the “0” state 11 and the “1” state 12 is refreshed by the process going into the “0” state. The corresponding process for writing the “1” state 11 is shown in FIGS. In this sequence, any electronic state between “0” state 11 and “1” state 12 is changed to a refreshed “1” state.
[0036]
It will be appreciated that this write process requires a write waveform to be applied simultaneously to the bit line and word line associated with a particular memory cell. Memory cells can be individually addressed. During the writing process, the blocking region is sequentially shifted up and down so that the electronic state of the node selectively takes a “1” or “0” value. However, if the write signal is applied to the word line X1 and not applied to the bit lines S1 and Y1, or if the write signal is applied to the bit line and not applied to the word line, writing does not occur and the current on the node 1 The state of is maintained.
[0037]
To read the stored information, the positive gate voltage Vx^(r)Is applied to the word line X1, and the current I between S1 and Y1_SYIs detected. As shown in FIG. 9, the threshold voltage of the transistor is V when the memory node 1 is negatively charged (“0”)._TWhen the memory node is positively charged (“1”), V_T-ΔV_TGiven by. These threshold voltages V_TAnd V_T-ΔV_TIs positive, no current flows between S and Y in a non-selected memory cell (Vx = 0). The gate voltage Vx of the selected word line^(r)Is V_TAnd V_T-ΔV_TAnd selected. So for "1" I_SY> 0, for "0" I_SY= 0. Therefore, the gate voltage Vx is applied to the word line V1.^(r)Is applied, a current detector (not shown) can be used to detect the current flowing between bit lines S1, Y1 (and other corresponding bit line pairs in the array). In order to read data from the entire memory array, this process is repeated sequentially for the other wordlines X of the array. In this embodiment, Vx^(r)= 0.8V, V_T-ΔV_T= 0.4V and V_T= 1.2V.
[0038]
According to the present invention, the tunnel barrier structure 2 improves the storage time and read / write performance. The accumulation time of the node 1 is the blocking region V of the current-voltage characteristic shown in FIG._BIs determined by the ability of the tunnel barrier structure 2 to inhibit the current flowing through The accumulation time ts is approximately given as follows.
[0039]
ts = tw exp (-qVc / kT) (2)
Here, k is the Boltzmann constant, T is the absolute temperature, q is the basic charge, and tw is the writing time. If ts is designed for 10 years and tw is 10 nanoseconds, Vc must be greater than 1V to operate at room temperature. When using the single electron charging effect, this requires that the barrier structure 2 be composed of metal particles of a size smaller than 1 nm. This size cannot be easily achieved with today's manufacturing technology.
[0040]
Another way that the blocking voltage Vc can be increased is to use a band bending effect on the charge barrier structure 2. This effect is discussed for multiple tunnel junctions in Applied Physics Letters, 5 June 1995, Vol. 66, No. 23, pp. 3170-3172 by K. Nakazato and H. Ahmed. The characteristics required for the tunnel junction for store (store) and write (write) cycles can be considered separately. The height and width of the tunnel junction can be represented by φs and ds in the store cycle and can be represented by φw and dw in the write cycle, respectively. In order to retain the accumulated information for more than 10 years, the barrier height φs must be greater than 1.8 eV to suppress the thermally generated Pool-Frenkel emission current, and the tunnel barrier thickness Ds is 8 nm x {φs (eV)} to control the tunnel leakage current.^-1/2Must be thicker. However, to obtain a short writing time of about 10 nanoseconds, the tunnel barrier width φw is 2 nm x {φw (eV)}.^-1/2Must be thinner. Here, φw is the barrier height for the write cycle.
[0041]
A barrier structure 2 that can satisfy these criteria is shown in FIG. It consists of layers 15 and 16 of insulating material and non-insulating material, respectively. In this example, the insulating layer 15 has a thickness of 1 to 3 nm (desirably 1 nm, but can be 1 to 3 nm)._ThreeN_FourThe non-insulating layer 16 is made of polysilicon having a thickness of 3 to 10 nm (desirably 3 nm, but can also be 3 to 10 nm).
[0042]
FIG. 11 shows a conduction energy band diagram obtained for the barrier structure 2 shown in FIG. This has a first relatively wide barrier component 17 of width Bw1 corresponding to the combined thickness of all the layers 15, 16 forming the barrier structure 2. Furthermore, each insulating layer 15 provides relatively narrow barrier components 18a, b, etc., each having a width Bw2 that are spaced apart from each other due to depletion regions formed in the polysilicon layer 16 during use. The relatively wide barrier component 17 has a relatively narrow barrier height Bh1, while the barrier components 18a, b, etc. provide higher barriers Bh1a, Bh2b.
[0043]
These two components 17, 18 of the barrier play different roles. The narrow and high barrier 19 functions as a tunnel barrier that suppresses co-tunneling effects (ie, spontaneous tunneling for two or more tunnel barriers due to quantum mechanical effects). As a result, the electrons pass through only one barrier 18 at a time, while staying in that region for some time. At this stop, electrons are scattered inelastically toward a local equilibrium state governed by the energy of the wide barrier component 17. In this way, the movement of electrons is strongly influenced by the wide barrier component 17. The width and height of high and narrow barrier components cannot be changed by an external bias. The reason for this is that they are determined by the material forming the barrier structure 2. However, the wide and low barrier component can be modulated by an external bias.
[0044]
FIG. 11A shows a band diagram when the voltage Vx is not applied. When no voltage is applied to the control electrode 9, in order for leakage from the charge storage node 1 to occur, the electrons 20 on the node 1 must pass through the entire width of the relatively wide barrier component 17, so that charge leakage is It turns out that it is strongly deterred. However, when a voltage is applied to the electrode 9, the conduction energy band diagram of the barrier 2 changes to a state as shown in FIG. From this figure, the following can be understood. That is, when a voltage is applied, a relatively wide barrier component 17 forms a slope inclined downward toward the charge storage node 1, and as a result, a relatively narrow barrier component 18 is used to reach the storage node. Just go through. Thus, this barrier structure provides a relatively wide barrier component 17 that stores electrons on node 1 for a long time. During the write process, it is not necessary to apply an extremely high voltage to the electrode 9 in order to pass electrons to the node 1.
[0045]
In layer 16, the polysilicon particles have a diameter approximately the same as their thickness. The particle size in the memory node 1 can be larger than the size of the layer 16, so that the electrons are stably accumulated on the memory node 1 and operate reliably. In the configuration of FIG. 10, the memory node 1 has a thickness of 5 to 30 nm (preferably 5 nm, but may be 5 to 30 nm) and is made of polysilicon. As a variant, the node 1 may be doped in order to improve the stability of the electronic state at the node. From the above, when storing information, the polysilicon layer 17 forms a depletion region and increases ds. On the other hand, in the light process, the layer 16 does not function as a barrier, and this configuration results in a potential gradient that accelerates electrons from the electrode 9 toward the node 1. This facilitates fast writing of electrons onto the node.
[0046]
Hereinafter, the manufacturing method of the present device will be described in detail with reference to FIG. A P-type silicon wafer having a resistivity of 10 Ωcm is used. For example, 500 nm thick SiO₂After the isolation region 7 is formed, a 5 nm gate oxide film 21 is grown on the top surface of the p-type silicon substrate 3 by thermal oxidation. Next, the layer forming the memory node 1 is deposited. Layer 1 consists of n-type Si deposited to a thickness of 5-10 nm (preferably 5 nm, but can be up to 10 nm), the surface of which is preferably NH at a temperature of 900 ° C._ThreeIn the atmosphere of silicon. The thickness of the silicon nitride formed in this way is self-limited to 1 to 2 nm (preferably 1 nm but possible up to a thickness of 2 nm). This corresponds to the nitride layer 15a shown in FIG. Thereafter, undoped silicon is grown to a thickness of 3-5 nm (desirably 3 nm, but possible to a thickness of 5 nm) nm to form a covering layer 16a (FIG. 10). This layer is further nitrided to form a silicon nitride layer 15b of the next 1-2 nm thickness (preferably 1 nm but possible up to 2 nm thickness). This process is repeated a plurality of times to build the barrier structure 2.
[0047]
Next, an n-type doped silicon film 22 having a thickness of 20 nm is deposited on the barrier structure layer 2. On this film 22, SiO 2 is deposited by chemical vapor deposition (CVD).₂Film 23 is grown to 20 nm.
[0048]
Various layers of the silicon film are grown in an amorphous state, but CVD deposited SiO₂During the nitridation and densifying process of layer 23, it is converted to polycrystalline silicon. Next, the topmost SiO₂The membrane 23 is CHF_ThreeAnd patterned by conventional lithographic techniques and reactive ion etching in an argon atmosphere.
[0049]
This patterned SiO is then₂By using layer 23 as a mask, the polysilicon and silicon nitride layers 22, 2 and 1 are used to produce a gate structure 24 as shown in FIG._ThreeEtching is performed by reactive ion etching using A typical length l of this gate structure 24 is 0.15 μm.
[0050]
As shown in FIG. 12 (c), the wafer is then heated to 30 nm thick thermal SiO.₂Oxidized to form the outer layer 25. Thereafter, the source region 5 and the drain 6 are formed by ion implantation with arsenic ions.
[0051]
Next, as shown in FIG.₂A film 26 is deposited. This film is covered with a layer of optical photoresist 27 that is thick enough to obtain a flat top surface, in this example 1500 nm thick. Photoresist 27 is then exposed from its surface to SiO.₂Etch until layer 26 protrudes. This etching is O₂It is performed by sputtering in an atmosphere. The structure thus obtained is shown in FIG.
[0052]
SiO₂The top 26a of the film 26 is WF until the top of the polysilicon film 22 is exposed, as shown in FIG.₆It is removed by reactive ion etching in a gas atmosphere.
[0053]
After removing the optical photoresist 27, a metal is deposited on the surface that appears and patterned by conventional lithography techniques. Thereby, the control electrode 9 for forming the word line X1 is provided.
[0054]
It will be appreciated that the memory device can be modified in various ways. For example, the thickness of the electrically conductive layer 15 may not be the above-mentioned value of 5 nm (desirably 3 nm, but possible up to a thickness of 5 nm). Generally speaking, the thickness is 10 nm or less. It ’s enough. The thickness of the insulating layer 16 is not limited to the above-mentioned value of 2 nm (preferably 1 nm, but possible to a thickness of up to 2 nm), but it is sufficient if it is in the range of 3 nm or less. 18 can be generated. However, in the manufacturing process described above, it is necessary to strictly control the thickness of each layer 16 so as to be on the order of 2 nm (preferably 1 nm, but possible up to a thickness of 2 nm). Further, the number of pairs of layers 15 and 16 may be different from “7” in the above example as long as the number is sufficient to obtain a satisfactory wide and low barrier component 17 in the barrier structure 2.
[0055]
Second embodiment
As a modification, the barrier structure 2 shown in FIG. 10 can be replaced with a Schottky barrier structure as shown in FIG. In this case, instead of using the insulating silicon nitride layer 15, a multi-layered structure of Schottky diodes stacked using the metal layer 18 is formed. The metal layer 28 is made of W or CoSi.₂Such a silicide film is formed between the undoped polycrystalline films 16.
[0056]
Next, still another embodiment of the memory device according to the present invention will be described. In this embodiment, the tunnel barrier structure 2 is composed of a plurality of nanometer-scale islands dispersed in a matrix of electrically insulating material. In the following example, the nanoscale islands have a diameter of 5 nm or less and are isolated by the nanoscale thickness (eg, 3 nm or less) of the electrically insulating material in the matrix. As a result, a narrow and high barrier component having a tunnel barrier structure can be obtained. The charge storage node is formed by a plurality of conductive islands so as to be distributed not in the independent layer 1 as described above but in the entire barrier structure. As described below, several different manufacturing processes can be used to form such a multiple tunnel barrier structure.
[0057]
Third embodiment
FIG. 15 shows a schematic cross-sectional view of another embodiment of a memory device according to the invention. In this embodiment, the memory node 1 and the barrier structure 2 are surrounded by surrounding SiO.₂This is realized by a composite composed of nanoscale crystals dispersed in a matrix. In FIG. 15, the substrate 3 is provided with source and drain regions 5 and 6 and a path 4 therebetween. This path 4 is covered by a gate oxide layer 29. This layer 29 has a thickness of 5 nm and is formed by a thermal oxidation process of the substrate. Thereafter, a 6 nm thick silicon layer is deposited by electron beam evaporation or CVD. Furthermore, rapid thermal oxidation and crystallisation is performed on this layer. This process is described in J. Appl. Phys. Vol. 74, 1993, pp. 4020-4025 by EHNicollian and R. Tsu, and Extended abstracts of M. 1996 International Conference on Solid State Devices and Materials, Yokohama, 1996, pp.175-178. This forms an island in the form of a 3 nm average diameter Si nanocrystal configured as a layer 30, which is covered by a 2 nm thick tunneling oxide layer 31. The self-capacitance of the 3 nm Si crystal results in a charging energy of about 100 meV. This energy is sufficient to limit the number of electrons inside each nanocrystal by Coulomb blockade at room temperature. Rapid thermal oxidation and crystallization following the deposition of layer 29 is repeated several times to create a composite layer of sufficient thickness. In this embodiment, this process is repeated five times to form a 20 nm thick composite layer. Five nanocrystal layers 30 are included in this thickness. Thereafter, an n-type silicon contact layer 32 is formed on the top surface. It will be understood that the gate structure thus completed can be incorporated into the memory device manufacturing process described above with reference to FIGS. However, the memory node 1 is not provided as an independent layer, but provides an electron storage location in which nanocrystals as each layer 30 are dispersed in the insulating oxide layers 29 and 31.
[0058]
Fourth embodiment
FIG. 16 illustrates the process steps for forming another embodiment of the memory device. In this embodiment, by using a porous Si film, silicon nanocrystals and SiO surrounding the silicon nanocrystals are used.₂A layer composite is formed. As shown in FIG. 16A, the porous Si film 33 having a thickness of 20 nm is formed by anodizing p-type Si. This anodization was performed at 10 mA / cm for 5 seconds in a 25% aqueous hydrofluoric acid solution diluted with ethanol.²It is executed by the direct current anode current. As a result, SiO₂A composite film in which nanocrystal Si of 4 to 5 nm is embedded in the matrix is formed. This method is known per se and is described in detail in Phys. Rev. vol. B48, 1993, p2827 by Y. Kanemith et al.
[0059]
Next, as shown in FIG. 16B, the porous silicon film 33 is thermally oxidized to form a gate oxide film 34 having a thickness of 5 nm, and a top oxide layer 35 having a thickness of about 7 nm is formed. This process also shrinks the diameter of each nanocrystal in the porous Si film by annealing and shrinks the thickness of the porous layer 33 itself. After this annealing process, the porous Si layer 33 is 14-16 nm thick and the average particle diameter is reduced to about 3 nm. The charging energy corresponding to the nanocrystalline silicon particles is about 100 meV, which limits the number of electrons that can enter the node by Coulomb blockade, as described above. The film thus obtained is shown as reference numeral 36 in FIG. 16 (b) and contains about 3 to 4 nanocrystalline particles in the thickness direction. This provides a multiple tunnel junction (MTJ) when considering vertical electron movement relative to this layer.
[0060]
Thereafter, the top oxide layer 35 is removed and a gate 32 of polysilicon material is deposited as described above. Using this polysilicon gate 32 as a mask, the composite film 36 and the underlying gate oxide 34 are removed by conventional etching techniques. Thereafter, the source and drain regions 5 and 6 are implanted by the method described with reference to FIG. This method has the following advantages over the method described in FIG. That is, multiple tunnel junctions are formed by a single anodization process, reducing the number of Si deposition and oxidation steps required.
[0061]
Fifth embodiment
The nanocrystals and the surrounding matrix can be formed by other methods using different materials. One example is described in Physical Review vol. B50, No. 12, 1994, pp8961-8964 by E. Bar-Sadeh et al. In this method, as an alternative to the porous silicon layer shown in FIG.₂O_ThreeA layer containing Au particles in the matrix can be used. 30 nm thick Au and Al₂O_ThreeThis composite film can be formed by co-sputtering gold and aluminum on a silicon oxide layer having a thickness of 5 nm formed by thermal oxidation of the substrate 3. Subsequent device manufacturing steps are the same as those in the fourth embodiment. The sputtering conditions for forming the composite film are selected so that the gold ratio is 0.4. Under these conditions, isolated Au particles with a diameter on the order of 3-5 nm are obtained in the composite film. Therefore, the 30 nm film includes 5 to 10 Au particles in the thickness direction, and this constitutes a vertical MTJ. It will be appreciated that this can be used to replace the porous silicon layer of FIG.
[0062]
Other noble metals such as Ag and Pt are made of SiO.₂Or Cr₂O_ThreeA composite film combined with another metal oxide matrix such as can be formed by this co-sputtering.
[0063]
The metal island-oxide matrix composite film can also be formed by thermal decomposition of a precursor metal oxide. For example, as described in L. Maya et al., J. Vac. Sci. Tchnol. Vol. B14, 1996, pp. 15-21, gold oxide as a precursor metal oxide is an Au-Si alloy in oxygen plasma. It can be formed by reactive sputtering of the target.
[0064]
Sixth embodiment
FIG. 17 shows a method of forming a composite nanocrystal / insulating tunnel barrier from a colloidal solution by chemical deposition. As shown in FIG. 17A, an oxide layer 21 having a thickness of 5 nm is formed on the p-type substrate 3 by a thermal oxidation process. Then, as described in detail by J. Vac. Sci. Technol vol. B11, 1993, pp. 2823-2828 by M.J. Lercel et al.₂A single layer 37 of octadecyltrichlorosilane (OTS) is formed on the layer 21. More specifically, SiO₂The substrate 3 with the layer 21 is immersed in a 1 mM hexadecane solution of OTS for 12 hours or more. Thereby, the OTS single layer 37 is spontaneously formed. OTS molecules are exposed to SiOk by irradiating a 60 kV electron beam.₂Can be removed from the surface. In this way, a window pattern is formed in the OTS on the single layer 37 by conventional electron beam lithography. After the window is formed in the OTS, it is immersed in a 1% aqueous solution of hydrofluoric acid for 30 seconds, and the residue of the OTS irradiated with the electron beam is rinsed away to leave the window 38. The edge region of this window is shown enlarged in the broken line frame 39. An example of the OTS molecule 40 is shown in the figure. It has a siloxane bond at one end and a methyl group at the other end. As shown in the enlarged region 39, the molecules 40 are composed of SiO.₂Layer 21 and siloxane bonds are formed to form a densely packed covalent network. The methyl group at the top is substantially inert and is therefore highly resistant to chemical attack during substrate processing.
[0065]
Subsequently, the substrate with the patterned OTS monolayer 37 is made for 10 minutes under reflux conditions (eg, heated to about 110 ° C.) with 3 mercatopropyl trimethoxysilane. Place in diluted (0.05%) dry toluene solution. The substrate is then cured for 30 minutes in a 105 ° C. oven with siloxane bonds. The result is shown in FIG. This procedure allows the SiO in the region of the window 38 to be₂A monolayer 41 of alkane thiol is formed on the layer 21. The structure of each molecule 42 forming this alkanethiol monolayer has a siloxane bond at one end of the alkane chain and a mercaptan group at the other end. This process is described in more detail in Langmuir, Vol. II, 1995, pp. 1313-1317 by A. Doron et al. The OTS molecule remains outside the window region 38 without being affected. The arrangement of the molecules 37, 42 can be understood more clearly from the enlarged view of the edge of the window shown in the dashed frame 43. In principle, this surface change is caused at one end by alkoxy silane ((CH_ThreeO)_ThreeSi- or (C₂H_FiveO)_ThreeIt can also be performed with other alkanethiols terminated with Si-).
[0066]
Subsequently, a single layer of colloidal gold particles 44 is deposited in the window region 38 by immersing the substrate in a colloidal gold solution at room temperature for at least 5 hours. This reduction occurs only in the window region where the surface is terminated by a mercaptan group (—SH). This is due to the strong affinity of sulfur for gold. The average diameter of colloidal gold particles is 2 nm.
[0067]
It is well known that gold colloidal particles of good size distribution, typically with a standard deviation of 10%, can be prepared chemically. Such nanoparticles are deposited on the mercaptan group-terminated surface by forming a covalent bond between the sulfur atom on the substrate and the gold atom on the gold colloid particle surface. This particle precipitation automatically stops when the layer is almost monolayer. This is because the electrostatic force due to the surface charge of the gold particles caused by the ionization of gold colloidal particulate adsorbates is greater than (or in close proximity to) the already deposited particles on the surface of the substrate. This is because it prevents the colloidal particles from adhering. For a more detailed description, see the inventors' EP 96300779.4 filed February 6, 1996. Colloidal suspensions of such particles are commercially available and are available at Nanoprobes Inc, NY 11790-3350, Stony Brook, 25E Loop Road Ste 124, USA, with a predetermined average particle size and diameter range distribution. The particles are provided in an aqueous suspension. The absorbed citrate ions give a negative charge to the Au particles.
[0068]
After the gold particles are precipitated from the colloidal solution described above, the substrate is immersed in a 5 mM ethanol solution of dithior (ie, 1,6-hexaneditiol). One of the two sulfur atoms of dithiol replaces the surface adsorbate of the gold particle with dithiol and forms an Au-S bond with the gold colloid surface. At the same time, the other end of the sulfur atom of the dithiol faces away from the gold surface in the form of a free mercaptan group. This configuration is shown in FIG. 18 (d) with the dithiol molecule as reference number 45. Thereafter, the gold particle surface is converted into a mercaptan group-coated surface. The surface coated with this mercaptan group can accept an additional layer of gold particles.
[0069]
Next, the dithiol treated surface is immersed in a colloidal gold solution and again a further layer is deposited. By repeating this process five times, five layers of 2 nm gold particles are formed. These are connected by the alkane chain of dithiol. Two gold layers 46 and 47 are shown in the enlarged portion 48 of FIG. The resulting five-layer gold structure is indicated by reference numeral 49 in FIG. 18 (d) and has a thickness on the order of 10 nm.
[0070]
Thereafter, as shown in FIG. 19 (e), the gold deposition process is further repeated five times with a gold colloid solution containing gold particles having a larger diameter (for example, 40 nm). By this treatment, a 40 nm gold particle composite layer 50 having a thickness of 150 nm is formed on the layer 49. Since the particles forming the layer 50 have a larger diameter, they exhibit a negligibly small charging energy on the order of 1 neV, and as a result, the electronic conduction of the composite layer 50 exhibits an ohmic character. This is different from the case of smaller diameter particles that form layer 49 that exhibits conduction characteristics governed by the Coulomb blockade effect. Therefore, the large-diameter gold composite layer 50 functions as a normal gold layer, and thus functions as a gate similar to the polysilicon gate 22 in the above-described embodiment, for example.
[0071]
Thereafter, the OTS layer 37 and the gate oxide layer 21 are dry-etched using the gold composite layer 50 as a mask. Thus, the source and drain regions 5 and 6 can be implanted into the substrate 3 by the conventional ion beam technique.
[0072]
Type 2
FIG. 20 shows a schematic configuration of another type of memory device according to the present invention. This device is similar to that shown in FIG. 1 and like parts bear the same reference numbers. The device of FIG. 17 further has a control gate 51. This is to change the tunnel barrier characteristics by selectively applying an electric field to the barrier structure 2. That is, when a voltage is applied to the terminal Y, the electric field of the gate 51 can be changed by changing the voltage of the terminal X. As a result, the electric field changes the tunnel barrier characteristics of the barrier 2. The effect of the electric field applied by the gate 51 can be understood from the graph of FIG. As shown in FIGS. 21A and 21B, the device can be switched between the “ON” state and the “OFF” state using the voltage on the gate 51. The voltage applied to the gate 51 is the blocking voltage V_BChange the width of. As shown in FIG. 21A, when the “ON” voltage Vx is applied to the gate 51, the blocking voltage is relatively small and does not exist in some cases. In FIG. 21 (a), the blocking voltage V_BIs -V_CLTo + V_CLIt is in the range. On the other hand, when the gate 51 has another “OFF” voltage, the blocking region is a wider region of −V._CHTo + V_CHIt becomes. Therefore, when the device is switched to the “ON” state, charges can pass through to the memory node 1 and are accumulated during the “OFF” state. During the “OFF” state, V, as described in K. Nakazato and H. Ahmed, Applied Physics Letters, 5 June 1995, Vol. 66, No. 23, pp. 3170-3172,_CHIn order to increase the bias, a bias voltage may be applied to the gate gate 51. The electric field generated by the voltage Vx applied to the word line 51 is given to the tunnel barrier structure 2 from the side, and as can be seen from a comparison between FIGS. Squeeze.
[0073]
Next, modulation of the voltage blocking region of the tunnel barrier 2 by the gate 51 will be described in detail with reference to FIGS. FIG. 22 shows a cross-sectional view of the memory node 1, the tunnel barrier structure 2, and the connection portion Y. Although the gate 51 is omitted in FIG. 21, it will be described later. The tunnel barrier structure is formed by the method described above with reference to FIG. 10 and has a thickness of 3 to 10 nm (preferably 3 nm, but can be 3 to 10 nm) and a thickness of 1 to 3 nm (preferably It consists of alternating layers 15 and 16 of silicon nitride (1 nm, but can also be 1 to 3 nm). The memory node 1 is composed of an n-type doped polysilicon layer having a thickness of 5 to 30 nm (preferably 5 nm, but may be 5 to 30 nm), and is covered with an undoped polysilicon layer 52 having a thickness of 30 nm. A corresponding undoped layer 53 is deposited under the 30 nm thick n-type undoped polysilicon layer 54 on the other side of the barrier structure.
[0074]
As can be seen from the energy band diagram of FIG. 23, the seven insulating silicon nitride layers 15 provide a relatively wide but low barrier with a corresponding relatively narrow and relatively high barrier component 18 in the same manner as described in FIG. Ingredient 17 is provided. The effect of applying a voltage to the gate 51 is to selectively raise or lower the barrier component 17 and to drag the barrier component 18 up and down accordingly.
[0075]
In the write process, the voltage Vx applied to the terminal X (FIG. 20) is set to the write voltage Vw (0 V), and as a result, the height of the barrier component 17 (which substantially corresponds to the internal potential in the barrier structure). ) Is on the order of 0.2 V, which is a relatively small value in this example. Therefore, electrons can pass through the narrow barrier component 18 and are not inhibited by the low and wide barrier component 17a. As a result, electrons pass from the terminal Y to the memory node 1.
[0076]
The charge accumulated in the node is set to the standby (standby) voltage Vx._SB(In this example, it can be held by raising to -5V). This raises the overall height of the relatively wide barrier component 17 to a level 17b (in this example on the order of 3V). This raised barrier component 17 height prevents charge carriers from tunneling out of the memory node 1, thereby allowing information to be retained on the node for as long as 10 years. Become.
[0077]
In order to read the information, the voltage Vx is set to the read voltage V_R(In this example, the order of −4V). As will be described later, this retains the charge stored in the memory node 1 and allows information to be read from the source / drain path of the device during a relatively short read cycle (˜110 ns). As shown in FIG. 23, the barrier component 17 has a shape 17c.
[0078]
Seventh embodiment
A more detailed configuration of the array of devices as described above will be described below with reference to FIG. FIG. 24 shows a plan view of a rectangular array of four cells. 25 and 26 are cross-sectional views of one cell taken along lines A-A ′ and B-B ′ in FIG. 24, respectively. As shown in FIG. 25, the schematic configuration of each memory cell is the same as that of the first type shown in FIG. 5, but a gate 51 is added. The same parts bear the same reference numbers. In FIG. 25, the p-type substrate 3 has a conduction path 4 between a source region 5 and a drain region 6, and an insulating region 7 for isolation from an adjacent cell. The device has a bit line consisting of a memory node 1 and a covered barrier structure 2 formed as shown in FIG. 22, a covered undoped polysilicon layer 53, and an n-type doped polysilicon layer. The bit line 54 is electrically insulating CVDSiO, as will be described in detail below.₂55 and SiO₂Covered by a wall 56. The side gate 51 of this cell consists of a 100 nm thick n-doped polysilicon layer, which extends across the bit line and covers the side edges of the barrier structure 2.
[0079]
Referring to FIG. 24 again, it can be seen that the drains 6 of adjacent memory cells in a row share the drain region 6, thereby reducing the memory cell size.
[0080]
A write voltage Vw is applied to the word line X1 (51) for a certain cell, for example, the memory cell M11 of FIG. Information can be written by applying an appropriate voltage. As a result, charges are written into the memory node 1 of the memory cell M11 in correspondence with the binary value “0” or “1” corresponding to the voltage of the bit line Y1. This data is not written to other memory cells in the column. Because other cells have their word line X₂Standby voltage V_SBBecause it receives. Thereafter, the standby voltage V is applied to the word line X1 in order to hold the data of the node 1 of the cell M11._SBIs applied. It is not necessary to apply a voltage to the bit line. When reading stored data from the cell M11, the standby voltage V_SBLower lead voltage V_RIs applied to the word line X1. A peripheral circuit (not shown) detects the source / drain conductivity of the cell M11 by detecting the current flowing between the lines S1 and G (lines 5 and 6). The other memory cells in the column have their word line X₂Etc. Standby voltage V_SBIs applied to be biased off so that these cells are not addressed (designated) by reading M11.
[0081]
Furthermore, other methods for operating the circuit similar to the normal methods employed in conventional DRAMs can be used. This is to transfer the accumulated information to the peripheral circuit and replace it with new information written in each memory node. This method uses the voltage blocking region V_BProvides a wide tolerance for the design value of V_CLAnd V_CHIt has the advantage of allowing a large change in the value of. The binary value “1” is the memory node voltage V_HThe binary value “0” is represented by the memory node voltage V_LIs represented by What the circuit needs is simply V_CHV_HLarger, V_CLV_LSmaller (ie V_CH> V_H> V_L> V_CL) Only. In practice, it is not necessary to specify these values. This wide design tolerance allows many memory cells to be integrated in one chip.
[0082]
Details of this operation method will be described below with reference to FIGS. FIG. 27 is a schematic circuit diagram of a memory cell array corresponding to FIG. 24, and also shows peripheral circuits incorporated on the same substrate 3 as the memory cell array. Each of the memory cells M11 to Mmn corresponds to the above-described second type memory device. However, this circuit has two transistors Q_R, Qw is shown as an equivalent circuit. Memory node 1 is indicated by N. FIG. 27 shows these configurations for the memory cell M11. This chip has a column decoder / driver 58, a row decoder / driver 59, and an on-chip voltage converter VC. This voltage converter VC generates several control voltages to be described later from an external voltage source Vcc which is a 5V power source in this example. Each column of the memory cell array has an associated precharge circuit 60 (PC) and a read / read / rewrite circuit 61 (RWC). The PC 60 and the RWC 61 are shown in detail for the column n = 1 of the memory cell array, and the corresponding circuit in the column n is shown by a broken line frame.
[0083]
The data input / output circuit 62 receives data from an external signal source and outputs data from the memory array to the outside by a method described in detail below.
[0084]
The symbols of various signals, lines, and components used in FIGS. 27, 28, and 29 are summarized below.
[0085]
table
Item Name
M11 to Mmn memory cells
m Row in memory cell array
n Memory cell array columns
S1 ~ Sn sense line
Y1-Yn data input line
X1-Xm word line
φy1 to φyn Column selection signal
I / O Column data input / output
PC precharge circuit
φp Precharge signal
RWC read / write circuit
φrw Read / write signal
a_xi            Row address signal
a_yi            Column address signal
CE chip enable signal
Din data input
Dout data output
WE Write enable signal
VC on-chip voltage converter
V_R             Lead power supply voltage
Vw Light power supply voltage
Vp Precharge power supply voltage
V_SB            Standby power supply voltage
Vcc externally applied voltage
IOC data input / output circuit
When the chip enable signal CE is at the voltage Vcc (hereinafter referred to as “high”), the chip is in an inactive state. In this state, since the precharge signal φp is “high” and the transistor of the PC 60 is in the “on” state, S1... Sn, Y1... Yn and I / O are precharged to the voltage Vp. . When CE changes from “high” to 0 voltage (hereinafter referred to as “low”), the chip becomes active. Next, φp becomes “low”, and the transistor of the PC 60 is turned “off”. At this time, the voltages of the lines S1... Sn, Y1. The word line sends a row address signal (a_xi) Is selected. Lead voltage V_RIs applied to X1, the memory cell M of the first row₁₁~ M_1nAnd the output signal appears on the corresponding sense lines S1 to Sn. For example, the memory cell M₁₁As an example, when the voltage of the memory node N is Vp, the transistor Q_RIs turned on, and the corresponding sense line S1 is discharged to 0V. Conversely, when the voltage of the memory node is 0V, the transistor Q_RIs in the "off" state, so S1 is maintained at Vp. After the voltage of S1 falls to 0V or Vp, the read / write signal φrw becomes “high”, and the information of S1 is transferred to Y1 via the RWC 61. That is, when S1 is 0V, Y1 is maintained at VpV. Because Q_DIs in the “off” state. However, when S1 is Vp, Y1 is discharged to 0V. Because both transistors Q_D, Q_TThis is because both are in the “on” state. Next, the applied column address signal (a_yi), Φy1 selectively becomes high, so that Q_Y1Turns on. Therefore, the voltage change of Y1 is transferred to the data output Dout via the input / output lines I / O and IOC62. After Y1 falls to 0V or Vp, the voltage of the word line X1 is changed to the write voltage Vw. As a result, the transistor Qw is turned on, and the voltage of Y1 is restored to the memory node N. In this way, the information is refreshed to 0V or Vp even if there is any variation in the memory node voltage during the read operation. This read and rewrite operation is performed by other cells M in the same row.₁₂... M_1nCell M₁₁The read information is not transferred to the I / O line as in the case of. When the read and rewrite operations are completed, CE becomes high and X1 becomes the standby voltage V._SBIn addition, φp becomes high.
[0086]
Next, the write operation will be described. As an example, the memory cell M₁₁FIG. 29 shows the write operation. By the same operation as described in the read operation, M₁₁Stored information is transferred to S1 and Y1. Thereafter, a voltage corresponding to the input data Din is applied to the I / O, and the read information of Y1 is replaced by this voltage. This is then stored in the memory node N by applying the write voltage Vw to the word line X1. Another cell M in the same row₁₂... M_1nCan be refreshed during the same operation. It will be appreciated that this process is repeated sequentially row by row to write data to all cells of the memory array.
[0087]
A method of manufacturing the memory cell according to the embodiment shown in FIGS. 24 to 26 will be described below with reference to FIG.
[0088]
As shown in FIG. 30A, a 10 Ωcm p-type silicon substrate wafer 3 is thermally oxidized to form a 5 nm thick SiO₂Layer 21 is formed. Next, an n-type doped silicon film 1 having a thickness of 5 to 10 nm (desirably 5 nm but can be up to 10 nm) for forming a memory node is deposited on the layer 21. This is covered by an undoped silicon film 52 with a thickness of 30 nm. The surface of the film 52 is desirably NH having a temperature of 700 ° C._ThreeA first layer of the layer 15 shown in FIG. 22 is formed by changing to a silicon nitride layer having a thickness of 1 nm in the environment. The thickness of the silicon nitride layer can be changed depending on the growth temperature from 2.5 nm at 1000 ° C. to 1 nm at 700 ° C. Subsequently, an undoped silicon layer 16 is deposited and nitrided to form another silicon nitride layer 15 having a thickness of 1 nm. This process is sequentially repeated six times to form a multiple tunnel junction 2 composed of seven sets of coating layers 15 and 16 shown in detail in FIG. Next, an undoped silicon film 53 with a thickness of 30 nm is deposited. This is a further 20 nm thick Si_ThreeN_FourCovered with a membrane 63. This film 63 is deposited for masking purposes, and lithography and CHF._ThreeAnd patterned by etching in argon gas. The silicon and silicon nitride layers 53, 15, 16, 52 are then etched away using a dry etching method known per se.
[0089]
In FIG. 30B, Si_ThreeN_FourBy using the film 63 as a mask, the surface of the wafer is oxidized together with the side edges 64a on the vertical side surface of the barrier structure 2, for example, SiO 2 having a thickness of 30 nm.₂64 is formed. Arsenic ions are implanted into the source and drain regions 5 and 6.
[0090]
Next, as shown in FIG._ThreeN_FourThe film 63 is removed, an n-type doped silicon film 54 having a thickness of 30 nm is deposited by a conventional CVD process, and an SiO film having a thickness of 50 nm is further deposited.₂A film 55 is deposited. Next, layer 55 is patterned by conventional lithography and dry etching. The width of the bit line, that is, the width of the line Y1 (54) shown in FIG. 24 is selected to be 60 nm. Thereby, good control of the internal potential of the device can be performed. The thicknesses of the various layers of the bit line Y1 can be selected according to the size of the memory cell array. These layers should be thicker for wider bit lines. Resist and SiO₂Using film 55 as a mask, Cl until the first silicon nitride layer of tunnel barrier structure 2 appears₂The layers 54 and 55 are selectively etched in a gas atmosphere.
[0091]
In FIG. 30 (d), CVD SiO with a thickness of 30 nm.₂Layer and CHF_ThreeThen, the side wall 56 is formed by dry etching in an atmosphere of argon gas.
[0092]
In FIG. 30 (e), a polycrystalline silicon layer 51 is then deposited and patterned by conventional lithography and dry etching to form word lines.
[0093]
The n-type and p-type MOS transistors used in the peripheral circuits 60 and 61 as shown in FIG. 27 can be formed on the same substrate 3 by a conventional method. The source and drain regions of the n-type MOS transistor can be formed simultaneously with the formation of the source and drain regions 5 and 6 of the memory cell Mmn described with reference to FIG.
[0094]
In the present embodiment, in order to maintain the stored information in each memory node 1, the standby voltage V on the word line_SBMust be applied. This can be achieved by using an external battery or capacitor when the device is turned off. Except for a leakage current that is negligibly small, no significant current flows, so that non-volatile characteristics can be obtained effectively. As a modification described later, an external battery or a capacitor can be omitted by shifting all voltages in the positive direction by + 5V. In this case, the standby voltage is 0 V, so no external battery is required.
[0095]
Eighth embodiment
FIG. 31 shows one method for shifting the standby voltage. In this case, the p-type doped region 65 is formed under the contact region of the word line. This structure can be considered as a modification of that shown in FIG. After the process steps shown in FIG.₂The p-type doped region 65 is formed by implanting boron ions using 55 and 56 as a mask. The voltage on the word line shifts by about 1V at room temperature. This structure has the other advantage that the internal potential, ie the conduction energy band edge, can be controlled more effectively. The effective bit line width is sufficiently narrower than the actual bit line width due to the effect of the implanted boron ions spreading laterally and the built-in potential of the implanted pi junction formed thereby. can do. As a result, a bit line width of 1 μm is sufficient to realize this memory device instead of the bit line width of 0.06 μm in the seventh embodiment. In this structure, V_SB= -4V, V_R= -3V, Vw = 1V.
[0096]
Ninth embodiment
Furthermore, as shown in FIG. 32, a thin p-type doped layer 66 can be formed inside the barrier structure, thereby obtaining a larger built-in potential. The structure shown in FIG. 32 can be considered as a modification of the structure shown in FIG. Such a p-type layer 66 can be easily formed by depositing a p-type silicon film or implanting boron ions at an intermediate stage for forming a barrier structure. This is because this layer can be formed by repeated vapor deposition. In order to reduce the diffusion of boron, the p-type doped layer 66 is sandwiched between thin tunnel barriers 15 as shown in FIG. In this case, the word line voltage directly controls the internal potential and thus the conduction energy band edge. Thereby, the voltage difference of the word line between the standby cycle and the write cycle can be reduced. In this structure, V_SB= -2V, V_R= -1V, Vw = 1V.
[0097]
Tenth embodiment
In this embodiment, a thicker tunnel barrier of the order of 5 nm is used as shown in FIG. The structure shown in FIG. 33 can be considered as a modification of the structure shown in FIG. This barrier structure can be incorporated into the devices described in FIGS. The memory node 1 in FIG. 33 is covered with an undoped polysilicon layer 52 having a thickness of 30 nm. The layer 52 itself is made of Si._ThreeN_FourIt is covered with a single barrier layer 67 made of the following materials. This Si_ThreeN_FourThe film can be formed by a plasma nitriding method at a temperature of 550 ° C. with high frequency power of 300 to 500 W. This layer is further covered by a 30 nm thick undoped Si layer 53 described with reference to FIG. FIG. 34 shows a conduction energy band diagram of the barrier structure formed thereby. This conduction energy band diagram has a relatively wide barrier component 17 with a relatively low barrier height and a relatively narrow barrier component 18 with a relatively high barrier height produced by layer 67. In this example, the barrier height is on the order of 2 volts and the insulating Si_ThreeN_FourProduced by a 5 nm thick layer. During the write operation, a write voltage is applied to the side gate 51 (not shown) in FIG. In this example, the write voltage Vw = 5V lowers the barrier structure in the transient state so that the relatively wide barrier component becomes the component 17a in FIG. In order to read the data, the voltage V so that the barrier is 17b._RIs applied to the gate 51. In this configuration, data can be read from the memory device. In order to store information, 0V is applied to the word line X so that the structure 17c actively prevents charge leakage from the memory node 1 so that the standby voltage V_SB= 0V.
[0098]
Type 3
Eleventh embodiment
FIG. 35 shows another type of memory device according to the present invention. This device is generally similar to the embodiment described in FIGS. 4 and 5, with like elements having the same reference numerals. In the embodiment of FIG. 35, the barrier structure is constituted by lateral dots 68 in the horizontal plane. These dots are produced by ionization beam deposition methods as described in W. Chen, H. Ahmed and K. Nakazato, Applied Physics Letters, 12 June 1995, Vol. 66, No. 24, pp. 3383-3384. Can be formed by a variety of different methods, or by monoatomic lithography as described by H. Ahmed in Third International Symposium on New Phenomena in Mesoscopic Structures, December 1995. Further, the dots 68 in the horizontal plane are formed by particles in the polycrystalline silicon film as described in the above-mentioned Yano et al., And as described in the methods of the third, fourth, and fifth embodiments. It can be replaced by nanocrystals, and further by colloidal particles as described in the method of the sixth embodiment.
[0099]
Many variations and modifications are within the scope of the present invention. For example, the various regions of n-type and p-type material can be interchanged to produce a device having conductive properties complementary to those described above. Different thicknesses of conductive and insulating materials can be mixed to form a tunnel barrier configuration. Different insulating materials can also be used. For example, silicon oxide can be used instead of silicon nitride as a tunnel barrier. In addition, other semiconductor manufacturing systems can be used for different basic substrates such as silicon on insulator, SiGe, Ge, GaAs, and others well known to those skilled in the art. In addition, various different embodiments of the barrier structure described above for use in the first type of memory device of the present invention and variations thereof are also used in the second type of embodiment having the side gate 51. can do. This second type of embodiment can be modified to use without side gates or by applying a fixed voltage to the side gates so as to operate according to the principle of the first type.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of a first type memory device according to the present invention;
FIG. 2 is a graph of current versus voltage characteristics of the barrier structure 2 shown in FIG.
FIG. 3 is a schematic circuit diagram showing an array of the memory device shown in FIG. 1;
4 is a schematic plan view showing the structure of the memory array circuit shown in FIG. 3; FIG.
FIG. 5 shows a memory cell M along FIG.₁₁FIG.
6 shows a memory cell M along the line B-B ′ of FIG. 4;₁₁FIG.
FIG. 7 is an explanatory diagram of a method for writing / reading data to / from individual cells of a memory array.
FIG. 8 shows the source of the device during the writing of the binary value “0” ((a) to (d)) and the writing of the binary value “1” ((e) to (h)); At the drain, the voltage V_SYIs a graph of voltage V at memory node 1 of the memory device plotted against.
FIG. 9 shows drain-source current I plotted against control gate voltage Vx for binary values “1” and “0” stored in memory node 1;_SYIt is a graph of.
FIG. 10 is a cross-sectional view showing the barrier structure 2 of the memory device in more detail.
FIG. 11 is a conduction energy band diagram (a) of the barrier structure 2 when charge carriers are accumulated in the memory node 1 and the corresponding energy when charge carriers are written into the node 1 by tunneling from the control electrode terminal X. It is a band diagram (b).
FIG. 12 is a cross-sectional view corresponding to the line A-A ′ of FIG. 4 showing various manufacturing steps for manufacturing the memory device.
FIG. 13 is a cross-sectional view corresponding to the line A-A ′ of FIG. 4 showing various manufacturing steps for manufacturing the memory device following FIG. 12;
FIG. 14 is a schematic cross-sectional view of a Schottky barrier structure that can alternatively be used in the present memory device.
FIG. 15 is a schematic cross-sectional view of an alternative barrier structure with nanometer-scale conductive islands for a third embodiment of a memory device according to the present invention.
FIG. 16 Nanometer scale silicon crystal is SiO₂FIG. 6 shows a series of manufacturing steps for manufacturing memory devices according to the present invention distributed throughout.
FIG. 17 is a process flow diagram for constructing another embodiment in which the barrier structure includes nanometer-scale gold molecules deposited from a colloidal solution.
FIG. 18 is a process step diagram following FIG. 17;
FIG. 19 is a process step diagram following FIG. 18;
FIG. 20 is a schematic structural diagram of a second type memory device according to the present invention;
FIG. 21 shows the voltage V applied to the terminal Y when there is a voltage applied to the terminal X (“ON” state) and when there is no such voltage (“OFF” state)._YFIG. 21 is a graph of current flowing through the barrier structure of FIG. 20 as a function of
22 is an enlarged schematic cross-sectional view of the barrier structure shown in FIG.
FIG. 23 shows a conduction band energy diagram of the barrier structure shown in FIG.
FIG. 24 is a schematic plan view of a memory cell array incorporating the second type memory device shown in FIG. 20;
25 is a cross-sectional view taken along line A-A ′ of FIG. 24. FIG.
FIG. 26 is a sectional view taken along line B-B ′ of FIG.
27 is a schematic circuit diagram of the memory cell structure of FIGS. 24, 25, and 26, shown with on-chip drivers and other peripheral devices. FIG.
FIG. 28 shows a memory cell M.₁₁It is a wave form diagram for demonstrating the process which reads information from.
FIG. 29 shows a memory cell M.₁₁It is a wave form diagram for demonstrating the process which writes data in.
30 is an explanatory diagram of the process steps for manufacturing the memory device shown in FIGS. 24 to 26; FIG.
FIG. 31 is a schematic cross-sectional view of a modification of the present memory device.
FIG. 32 is a schematic cross-sectional view of still another modification of the device.
FIG. 33 is a schematic cross-sectional view of another barrier configuration for use in a second type of memory device according to the present invention.
34 is a conduction energy band diagram corresponding to the barrier structure shown in FIG. 33. FIG.
FIG. 35 is a schematic cross-sectional view of a third type of memory device according to the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Memory node, 2 ... Barrier, 3 ... Substrate, 4 ... Conduction path, 5 ... Source region, 6 ... Drain region, 7 ... SiO₂Insulating region, 8 ... insulating SiO₂Layer, 9 ... conduction control electrode.

Claims (12)

A memory device having a source region , a drain region , and a control electrode,
The source region and the drain region formed in a semiconductor substrate;
A conduction path extending between the source region and the drain region;
A memory node that is provided on an insulating layer covering the substrate, and stores a charge that generates an electric field that changes conductivity of the conduction path for charge carriers between the source region and the drain region ;
It said memory node and provided between said control electrode, depending on the polarity of the voltage applied to the control electrode, to the memory node from the control electrode, or to move from said memory node to said control electrode in, and a tunneling barrier structure is a multiple tunnel junction structure in which the conductive load passes through, has,
The tunnel barrier structure is
It has alternating layers of electrically conductive material and insulating material layers, the electrically conductive material layer is 3-10 nm in thickness, and the insulating material layer is thick Is a relatively wide first corresponding to a combined thickness of all of the alternating layers of electrically conductive material and insulating material forming the tunnel barrier structure . A barrier component and a barrier higher than the first barrier component having a relatively narrow width, each corresponding to a respective layer of insulating material , and functioning as a tunnel barrier that suppresses the cooperative tunneling effect . A memory device characterized by exhibiting an energy band profile having two barrier components. The memory device of claim 1 , comprising:
The electrically conductive material is polysilicon;
The memory device, wherein the insulating material is silicon nitride. The memory device of claim 1 , comprising:
The memory device, wherein the insulating material layer has a thickness on the order of 1 nm. The memory device of claim 1, comprising:
The memory node, a memory device, characterized in that constituted by a layer of electrically conductive material formed between the conductive path and the tunneling barrier structure. The memory device of claim 1 , comprising:
The memory node comprises a layer of doped semiconductor material. The memory device of claim 1, comprising:
A memory device, wherein an amount of charge that can be stored in the memory node is limited by a Coulomb blockade effect. A memory array circuit having a substrate and a plurality of memory cells arranged in a matrix on the substrate,
Memory array circuit in which the memory cells, characterized in that it is a memory device according to any one of claims 1 to 6. The memory array circuit according to claim 7 ,
Of the charge, in order to control the passage of the tunneling barrier structure of the memory cell, a bit line formed by connecting the source regions and the respective drain regions of the plurality of memory cells arranged in a column direction,
A memory array circuit comprising: a word line formed by connecting the control electrodes of a plurality of memory cells arranged in a row direction . The memory array circuit according to claim 7 ,
A memory array circuit comprising means for selectively reading stored data from the plurality of memory cells and refreshing the stored data. The memory array circuit according to claim 9 , wherein
A memory array circuit comprising means for selectively storing data individually in the plurality of memory cells. The memory array circuit according to claim 7 ,
A memory array circuit comprising a peripheral circuit formed on the substrate. The memory array circuit according to claim 11 , comprising:
The memory circuit according to claim 1, wherein the peripheral circuit includes a transistor having a region formed by the same process step as used to form a corresponding region in the memory cell.

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