KR100828973B1 - Detecting method of downward modulating form, control method of downward modulator using thereof, and downward modulator - Google Patents

Abstract

A detecting method of a downward modulating form, a control method of a downward modulator using the same, and the downward modulator are provided to perform modulation by itself inside the downward modulator without additional information for a downward signal by detecting the downward modulation form through a trial and error method. A detecting method of a downward modulating form comprises the following steps of: receiving a signal on a downward modulator; comparing a unique synchronization pattern in a frame synchronization sequence of the signal with a first critical value set according to the downward modulating form(S2); determining the downward modulating form according to the compared result; and outputting the determined downward modulating form(S3,S4). A step of comparing an FEC(Frame Error Correction) frame of the signal with a second critical value set according to the downward modulating form(S5) is further comprised in the detecting method.

Description

TECHNICAL FIELD DETECTING METHOD OF DOWNWARD MODULATING FORM, CONTROL METHOD OF DOWNWARD MODULATOR USING THEREOF, AND DOWNWARD MODULATOR}

1 is a block diagram showing the structure of a downlink demodulator according to an embodiment of the present invention;

2 is a block diagram showing a structure of a frame error correction frame according to an embodiment of the present invention;

3 is a block diagram showing an input sequence of a trellis coded modulation encoder according to an embodiment of the present invention;

4 is a block diagram illustrating a structure of a frame sync sequence detector and remover according to an embodiment of the present invention;

5 is a block diagram showing the structure of the pattern filter 1 and the pattern filter 2 according to an embodiment of the present invention;

6 is a graph showing the output of the pattern filter 1 and the pattern filter 2 as an experimental result performed according to an embodiment of the present invention,

7 is a block diagram illustrating an example of an output value and a counter value of the pattern filter 1 and the pattern filter 2 according to an embodiment of the present invention;

8 is a structure of a frame error correction frame decompressor according to an embodiment of the present invention;

9 is a flowchart illustrating a flow of a detection method of a downlink modulation method according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

26: multiplexer 1 block 27: pattern filter 1 block

28: pattern filter 2 block 29: multiplexer 2 block

30: Comparator 1 Block 31: Counter 1 Block

32: comparator 2 block 33: counter 2 block

34: Comparator 3 Block 35: Timer Block

36: FEC Frame Restorer

The present invention relates to a detection method of a down-modulation method that enables self demodulation within a down-level demodulator without additional information on a downlink signal, a control method of a down-down demodulator, and a down-down demodulator.

In the modulation and demodulation method of wireless communication, modulation and demodulation is a structure in which a signal to be sent is carried on a carrier and the signal is recovered on the receiving side. There are three types of modulation methods: amplitude modulation (ASK, Amplitude Shift Keying), frequency modulation (FSK, Frequency Shift Keying), and phase modulation (PSK, Phase Shift Keying).

Quadarature Amplitude Modulation (QAM) is a method of doubling the effective frequency band by combining two orthogonal modulated signals into one channel, and is an international organization for fostering combination standards of communication equipment and systems. In the International Telecommunications Union-Telecommunication Standarization Sector (ITU-T), ITU-T J.83 Annex B, which is the standard for downlink signals of CATV (Cable TV), uses 64QAM and 256QAM as the downlink modulation methods. use.

In each case of the 64QAM and 256QAM schemes, a frame sync sequence is inserted, and the frame sync sequence includes a unique sync pattern, an interleaver control word and a reserved phrase. reserved). The frame synchronization sequence of 64QAM is 42 bits in total, and the frame synchronization sequence of 256QAM is 40 bits in total.

Here, in the case of 64QAM, the unique sync pattern uses “75 2C 0D 6C” as a hex value, and in case of 256QAM, “71 E8 4D D4” is used.

However, since the downlink demodulator cannot be known in the downlink demodulator, a downlink demodulation method is conventionally used based on a signal-to-interference ratio of a received signal.

More specifically, Korean Patent Publication No. 2006-0029243 discloses amplitude information on in-phase and quadrature phase components of a signal received over a plurality of symbols in order to detect multilevel quadrature amplitude modulation (M-QAM). After the collected and averaged absolute values of the amplitude information of the in-phase and quadrature components have been determined over a number of symbols, reference is made to the determined mean absolute values of the in-phase and quadrature phase components and the estimated signal-to-band of the received signal. By generating a bias corrected decision boundary estimate based on the interference ratio, the modulated signal is detected.

The present invention was devised to propose a new method for finding the downlink modulation scheme. The present invention proposes that a unique synchronization pattern is different according to the downlink modulation scheme of the downlink modulator, and thus demodulates itself in the downlink demodulator without additional information about the downlink signal. The present invention relates to a detection method of a downlink modulation method for controlling an internal block of a downlink demodulator, and a control method of a downlink demodulator and a downlink demodulator based on this.

In order to achieve the above object, the present invention provides a method for detecting a down-modulation method of wireless communication, comprising: receiving a signal by a down-level demodulator, a threshold set according to a frame sync sequence and a down-modulation method of a signal; Comparing the value 1, determining a downlink modulation scheme according to a result of the comparison, and outputting the determined downlink modulation scheme.

In addition, the present invention provides a method for controlling a downlink demodulator in a wireless communication, the method comprising arbitrarily setting a downlink modulation method of a signal received by a downlink demodulator, a unique sync pattern in a frame sync sequence of a signal. sync. pattern) and threshold 1 according to the arbitrarily set down modulation scheme are compared, and if it is determined that the comparison is the same, the arbitrarily set down modulation scheme is determined and determined not to be the same. If so, a step of switching the arbitrarily set down modulation scheme.

In addition, in the downlink demodulator of the wireless communication, a multiplexer 1 block for receiving an output of the trellis coded modulation decoder and selecting an input signal, a multiplexer 2 block for selecting a pattern filter, and an output of the multiplexer 2 block are selected. Comparator for comparing whether the unique sync pattern in the frame sync sequence of the signal received by the downlink demodulator and the threshold value 1 according to a randomly set downlink modulation scheme with respect to the signal are the same. Contains 1.

DETAILED DESCRIPTION A detection method of a downlink modulation method, a control method of a downlink demodulator, and a downlink demodulator according to the present invention for realizing the above object will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a structure of a downlink demodulator according to an embodiment of the present invention, FIG. 2 is a block diagram showing a structure of a frame error correction frame according to an embodiment of the present invention, and FIG. 4 is a block diagram illustrating an input sequence of a trellis coded modulation encoder according to an embodiment of the present invention. FIG. 4 is a block diagram illustrating a structure of a frame sync sequence detection and removal unit according to an embodiment of the present invention. 6 is a block diagram showing the structure of the pattern filter 1 and the pattern filter 2 according to an embodiment of the invention, Figure 6 shows the output of the pattern filter 1 and the pattern filter 2 as an experimental result performed according to an embodiment of the present invention 7 is a block diagram illustrating an example of an output value and a counter value of the pattern filter 1 and the pattern filter 2 according to an embodiment of the present invention, and FIG. 8 is a frame error correction frame decompressor according to an embodiment of the present invention. The structure of Figure 9 FIG. Is a flowchart illustrating a flow of a detection method of a downlink modulation method according to an embodiment of the present invention.

As shown in FIG. 1, the down modulator includes a down modulator 10 and a down demodulator 24. The downlink modulator 10 reads an MPEG framer block 1 and an MPEG-2 TS byte stream that have received a byte stream of an MPEG-2 transport stream. Solomon) RS encoder block (2) for encoding symbols, interleaver block (3) for interleaving RS symbols, randomizer block (4) for interleaving interleaved signals, frame for inserting frame synchronization sequences Synchronization sequence insertion block (5), TCM encoder block (5) that performs Trellis-Coded Modulation (TCM), Pulse Shaping Filter (8) and digital signals as analog signals A digital-to-analog conversion (D / AC) block 11 for converting. In addition, the interleaver block 3 can operate in 16 modes by the control tool 2 shown in FIG. 2, and the deinterleaver block 21 of the downlink demodulator 24 shown in FIG. It should operate in the same mode as the interleaver block 3 of the downlink modulator.

The downlink demodulator 24 includes an analog-digital conversion (ADC) block 12 for converting an analog signal into a digital signal, and a timing recovery block for recovering a symbol clock from the received downlink signal. (13), an automatic gain control (AGC) block 14 for automatically controlling gain, and a carrier recovery (CR) block for compensating for phase offset of carriers between the down-modulators 10 and 24; 15, an equalizer (EQ) block 16 to compensate for the characteristics of the channel, a TCM decoder block 13 to decode the TCM, a frame sync.sequence detector and remover ) Block 19, derandomizer block 20, deinterleaver block 21, and RS decoder block 22.

As shown in FIG. 2, the signal viewed at "d" in FIG. 1 carries a 42-bit frame sync trailer after one frame error correction frame (FEC frame) in case of 64QAM. In addition, one frame error correction frame is composed of 60 RS blocks, and one RS block is composed of 128 RS symbols. In the case of 256QAM, one frame error correction frame (FEC frame) followed by a 40-bit frame sync trailer (frame sync. Trailer), one FEC frame is composed of 88 RS blocks, one The RS block consists of 128 RS symbols.

As shown in FIG. 3A, the 64QAM trellis group of “d” of FIG. 1 has five TCM QAM symbols composed of a total of 28 bits. Here, the unique sync pattern is continuously located after the data sample, whereby one FEC frame has 53802 (128 * 60 * 7 + 42) bits.

In addition, as shown in (b) of FIG. 3, the 256QAM trellis group of “d” of FIG. 1 is a unique sync with a non-sync trellis group that does not include a unique sync pattern. Includes a sync. Trellis group containing patterns. Since the synchronous trellis group includes 8 sync trailer bits, 5 sync trellis groups are required to include 40 sync trailer bits, and one FEC frame. Has 78888 (128 * 88 * 7 + 40) bits. However, in the case of 256QAM, unlike the case of 64QAM, the sync trailer bits are not continuously inserted. As a result, as shown in FIG. 5, the pattern filter 1 and the pattern filter 2 are configured differently.

As shown in FIG. 4, the frame sync. Sequence detector and remover of the frame sync sequence detection and removal block 19 of FIG. 1 includes a multiplexer (MUX, MUltipleXer) 1 block 26, Multiplexer 2 block (29), Comparator 1 block (30) to select the pattern filter 1 block 27, the pattern filter 2 block 28, the pattern filter 1 block 27 and the pattern filter 2 block 28. , A counter 1 block 31, a comparator 2 block 32, a counter 2 block 33, a comparator 3 block 34, a timer block 35, and an FEC frame regenerator block 36. .

Here, an exemplary embodiment of the threshold thr used in the comparator 1 block 30, the comparator 2 block 32, and the comparator 3 block 34 is shown in Table 1 below.

64QAM 256QAM Threshold 1 (thr 1) 28 32 Threshold 2 (thr 2) 53801 78887 Threshold 3 (thr 3) 3 3

In addition, one embodiment of the signal output from the FEC frame recovery block 36, its use and definition is shown in Table 2 below.

Output signal Purpose and definition FEC frame Received FEC Frame Data Interleaving Mode (InterLv_mode) 4-bit control for controlling the deinterleaver Frame Start (Frame_Start) Signal indicating the start of the received FEC, used to initialize the RS decoder and derandomizer. QAM mode (QAM_Mode) Signal distinguishing between 64QAM and 256QAM, "0" is 64QAM and "1" is 256QAM.

A detailed description of a method for detecting a downlink modulation method, a method for controlling a downlink demodulator, and an apparatus thereof according to the present invention will be described in detail with reference to FIGS. 4, 5, or 9 as follows.

First, the initial operation of the frame synchronization sequence detection and removal starts in the state where the QAM mode is "0" (the state is 64QAM) (S1).

The multiplexer 1 block 26 selects the output signal " a " of the TCM decoder block 19 in FIG. 1 according to the QAM mode and inputs it to the pattern filter 1 block 27 or the pattern filter 2 block 28. FIG. Each specific configuration of the pattern filter 1 block 27 and the pattern filter 2 block 28 is as shown in FIG.

More specifically, as shown in (a) of FIG. 5, in the case of 64QAM, a pattern filter 1 block (reference numeral 27 of FIG. 4) is selected, and the pattern filter 1 block 27 includes 28 registers ( R27 to R0) (37, 38, 39), 28 unique sync pattern bits (S27 to S0) (40, 41, 42), 28 exclusive NOR (XNOR, eXclusive NOR) (43, 44, 45) and An adder (+) 46 that sums the XNORs. In addition, as shown in (b) of FIG. 5, in the case of 256QAM, the pattern filter 2 block (reference numeral 28 of FIG. 4) is selected, and the pattern filter 2 block 28 includes 140 registers (R139 to R0). (47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59), 32 unique sync pattern bits (S31 to S0) (60, 61, 62, 63, 64, 65), an adder (+) 72 that sums 32 XNORs (66, 67, 68, 69, 70, 71) and XNOR

Equations calculated in the pattern filter 1 block (reference numeral 27 of FIG. 4 and FIG. 5A) and the pattern filter 2 block [reference number 28 in FIG. 4 and (B) in FIG. 4) are respectively represented by Equation 1 below. And Equation 2.

은 도 5에 도시되어 있는 패턴 필터 1 및 2의 출력신호,

는 프레임 동기 트레일러 내의 유니크 동기 패턴 비트,

는 TCM 디코더의 출력신호를 저장하는 레지스터를 나타내고 연산부호

는 배타적 부정 논리합(XNOR, eXclusive NOR)을 나타낸다.here,

Is an output signal of the pattern filters 1 and 2 shown in FIG.

Is a unique sync pattern bit within a frame sync trailer,

Denotes a register that stores the output signal of the TCM decoder and an operation code.

Denotes an exclusive negated logical sum (XNOR, eXclusive NOR).

For reference, as shown in FIG. 6, the pattern filter 1 block (reference numeral 27 of FIG. 4 and (a) of FIG. 4) and the pattern filter 2 block (reference numerals 28 and 5 of FIG. 4) according to the QAM mode. As shown in (a) of FIG. 6, threshold value 1 of Table 1, which is the maximum value in the case of 64QAM, appears in 53802 cycles as shown in FIG. As shown in (b) of FIG. 6, in the case of 256QAM, it was confirmed that the threshold value 1 of Table 1, which is the maximum value, appeared in 78888 cycles.

As shown in Fig. 4 or 9, the output of the pattern filter 1 block 27 and the pattern filter 2 block 28, "b" is the comparator 1 block 30 by the multiplexer 2 block 29 according to the QAM mode. ) Is entered. Comparator 1 block 30 compares the input value with threshold 1 (thr 1) (S2 in Fig. 9) and outputs "1" when the same, and initializes counter 1 (cnt 1) to "0". S3 of FIG. 9 compares the input value with the threshold 1 (thr 1) and outputs "0" when it differs, and increases the counter 1 (cnt 1) by 1 (S4 of FIG. 9). The comparator 2 block 32 receives the value of the counter 1 (cnt 1) and the output value of the comparator 1 block 30, the value of the counter 1 (cnt 1) is equal to the threshold 2 (thr 2), and the comparator 1 block ( If the output value of 30 is " 1 " (S5 in FIG. 9), the counter 2 (cnt 2) is incremented by one (S6 in FIG. 9). Otherwise, counter 2 (cnt 2) is initialized (S7 in FIG. 9). FIG. 7 illustrates 64QAM and 256QAM for the values of the comparator blocks 30, 32, 34 and the counter blocks 31, 33 described above.

As shown in FIG. 4 or FIG. 9, in the comparator 3 block 34, when the value of the counter 2 cnt 2 exceeds the threshold value 3 (S8 in FIG. 9), the current 64QAM is maintained (S9 in FIG. 9). If not, turn the timer (Timer) of the timer block 35 (S10 in FIG. 9) to switch the QAM mode to 1 when the value of the counter 2 is "0" (S11 in FIG. 9) for a predetermined time ( Switch to 256QAM) (S12 in FIG. 9). Here, if the value of the counter 2 is not " 0 " (S11 in FIG. 9) for a predetermined time by turning the timer Timer of the timer block 35 (S10 in FIG. 9), the current QAM mode is maintained (FIG. 9). S9). Here, if the output value of the pattern filter 2 block 28 in the comparator 2 block 32 is equal to the threshold 1 (thr 1) in Table 1 (S13 in FIG. 9), the counter 1 (cnt 1) is set to "0." "1" is outputted ("S3" in FIG. 9), and if it is different, counter 1 (cnt 1) is incremented by 1 and "0" is outputted.

As shown in FIG. 8, the internal structure of the FEC frame recovery block 36 includes a frame sequence removal block 73, a RAM block 75, and a counter block 74. The counter block 74 receives the QAM mode and the output of the comparator 1 block 30 of FIG. 4, determines the exact position of the unique sync pattern, and turns the counter based on the counter value to remove the counter sync frame 73. Enter In addition, a read / write address is generated and input to the RAM block, and a frame start signal indicating a start point of a received FEC frame is generated. Accordingly, the frame synchronizing sequence removing block 73 receives the counter value of the counter block 74 and the TCM decoder output value "a" and outputs "c" for the continuous FEC frame signal.

The present invention finds the downlink modulation method by a trial and error method in consideration of different unique synchronization patterns according to the downlink modulation method of the downlink modulator, thereby demodulating itself in the downlink demodulator without additional information on the downlink signal. Has the effect of making it possible.

Claims (12)

delete In the down-modulation detection method of wireless communication, The downstream demodulator receives a signal, Comparing a unique sync pattern in a frame sync sequence of the signal with a threshold value 1 set according to the downlink modulation scheme; Determining the downlink modulation method according to a result of the comparison, and Outputting the determined downlink modulation scheme Containing Downlink modulation detection method. The method of claim 2, And comparing a frame error correction frame (FEC frame) of the signal with a threshold value 2 set according to the downlink modulation method. Downlink modulation detection method. In the down-modulation detection method of wireless communication, The downstream demodulator receives a signal, Arbitrarily setting a downlink modulation scheme of the signal; Comparing a unique sync pattern in a frame sync sequence of the signal with threshold 1 according to the arbitrarily set down modulation scheme; and If it is determined that the comparison is the same, determining the arbitrarily set downlink modulation scheme; and if it is determined that it is not the same, switching the arbitrarily set downlink modulation scheme. Containing Downlink modulation detection method. The method of claim 4, wherein Comparing whether a unique sync pattern in a frame sync sequence of the signal and a threshold value 1 according to the arbitrarily set down modulation scheme are equal to each other may be unique. In the case of equal to the threshold value 1 set according to the synchronization pattern and the arbitrarily set down modulation scheme, the counter 1 is initialized and the output value 1 is outputted; otherwise, the counter 1 is incremented and the output value 2 is outputted. Increasing the counter 2 if the value of the counter 1 is equal to the predetermined threshold 2 and the output value is the output value 1; Downlink modulation detection method. The method of claim 5, wherein Determining whether the value of the counter 2 exceeds a predetermined threshold value 3; Determining whether the value of the counter 2 is initialized for a predetermined time when the value of the counter 2 does not exceed the threshold 3; If the value of the counter 2 is initialized for the predetermined time, further comprising setting a downlink modulation scheme different from the arbitrarily set down modulation scheme for the signal; Down-modulation Detection Method In the control method of the downlink demodulator of wireless communication, Arbitrarily setting a downlink modulation scheme of a signal received by the downlink demodulator; Comparing a unique sync pattern in a frame sync sequence of the signal with threshold 1 according to the arbitrarily set down modulation scheme; and Determining that the arbitrarily set downlink modulation scheme is determined if it is determined to be the same as a result of the comparison; and switching the arbitrarily set downlink modulation scheme when it is determined that the setup method is not identical. Containing Control method of downlink demodulator. The method of claim 7, wherein Comparing whether a unique sync pattern in a frame sync sequence of the signal and a threshold value 1 according to the arbitrarily set down modulation scheme are equal to each other may be included in the frame sync sequence. In the case of equal to the threshold 1 set according to the unique synchronization pattern and the arbitrarily set down modulation scheme, the counter 1 is initialized and the output value 1 is outputted; otherwise, the counter 1 is incremented and the output value 2 is outputted. Increasing the counter 2 if the value of the counter 1 is equal to the predetermined threshold 2 and the output value is the output value 1; otherwise, the counter 2 is further initialized. Control method of downlink demodulator. The method of claim 8, Determining whether the value of the counter 2 exceeds a predetermined threshold value 3; If the value of the counter 2 does not exceed the threshold 3, determining whether the value of the counter 2 is initialized for a predetermined time; If the value of the counter 2 is initialized for the predetermined time, setting the downlink modulation scheme different from the arbitrarily set downlink modulation scheme for the signal; Control Method of Downward Demodulator In the down demodulator of wireless communication, A multiplexer 1 block for receiving an output of the trellis coded modulation decoder and selecting an input signal; A multiplexer 2 block to select a pattern filter, A unique sync pattern within a frame sync sequence of a signal input to the downlink demodulator by receiving the output of the multiplexer 2 block and a threshold value according to an arbitrarily set downlink modulation scheme for the signal. Comparator to compare whether 1 is equal 1 Containing Downward demodulator. The method of claim 10, The comparator 1 for comparing the unique sync pattern in the frame sync sequence of the signal with the threshold 1 according to the arbitrarily set down modulation scheme is the frame sync sequence. In case of equal to the threshold value 1 set according to the unique synchronization pattern and the arbitrarily set down modulation scheme, the counter 1 is initialized and the output value 1 is outputted. Otherwise, the counter 1 is increased and the output value 2 is outputted. And a comparator 2 for increasing the counter 2 when the value of the counter 1 is equal to the predetermined threshold 2 and the output value is the output value 1. Otherwise, the counter 2 is initialized. Downward demodulator. The method of claim 11, A comparator 3 for determining whether the value of the counter 2 exceeds a predetermined threshold value 3; If the value of the counter 2 does not exceed the threshold 3, it is determined whether the value of the counter 2 is initialized for a predetermined time, and if the value of the counter 2 is initialized for the predetermined time, And a timer for setting a downlink modulation scheme different from the arbitrarily set downlink modulation scheme. Downward demodulator.

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