KR100821125B1 - Apparatus and method for buffer management and processing of receiving interrupt between MAC hardware and software - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to an apparatus and method for buffer management and reception interrupt processing between a media access control hardware and a software processing apparatus.

2. The technical problem to be solved by the invention

The present invention provides buffer management and reception between media access control hardware and software processing devices to reduce the complexity of buffer management for reception interrupts that occur continuously between the media access control hardware and software processing devices, and to reduce losses such as discarding received frames. Its purpose is to provide an apparatus and method for interrupt handling.

3. Summary of Solution to Invention

The present invention relates to a buffer management and reception interrupt processing device between a MAC hardware processing device and a MAC software processing device, wherein a hardware internal address of the MAC software processing device is decoded when a hardware interrupt occurs due to frame reception. Address decoding means for concatenating into blocks; Interrupt status information providing means for constructing and providing a bitmap with information indicating the received frame storage status of each storage means as many bits as the number of storage means; Interrupt access information providing means for providing the MAC hardware processing apparatus with information for controlling the access (simultaneous write) of the MAC hardware processing apparatus when updating the interrupt status information providing means of the MAC software processing apparatus; A plurality of storage means for storing the received frame; Receiving frame length information providing means for constructing a bitmap with the length information of the receiving frame stored in each storage means as many bits as the number of storage means, and providing the read frame when the receiving device reads (reads) the MAC software processing apparatus; Hardware interrupt control means for controlling the storage of the received frame in the empty storage means based on the information provided by the interrupt status information providing means.

4. Important uses of the invention

The present invention is used in the buffer management and reception interrupt processing system of the media access control hardware processing apparatus.

Media Access Control, Zigbee, IEEE 802.15.4, Wireless LAN, Receive Interrupt, Multi-Buffer, IEEE 802.11

Description

Apparatus and method for buffer management and processing of receiving interrupt between MAC hardware and software}

1 is a configuration diagram of an apparatus for buffer management and reception interrupt processing between a medium access control (MAC) hardware and a software processing apparatus according to the present invention;

2 is a flowchart illustrating a buffer management and reception interrupt processing method of a media access control hardware processing apparatus according to the present invention;

3 is a flowchart illustrating a buffer management and reception interrupt processing method of a media access control software processing apparatus according to the present invention;

4 is a diagram illustrating an embodiment of a buffer management and reception interrupt processing method of a media access control hardware processing apparatus according to the present invention;

5 is a diagram illustrating another embodiment of a buffer management and reception interrupt processing method of a media access control hardware processing apparatus according to the present invention.

* Explanation of symbols on the main parts of the drawing

10: media access control hardware processing apparatus 110: address decoding unit

120: Receive frame length register 130: Interrupt access register

140: interrupt status register 150: hardware interrupt control

20: media access control software processing device

The present invention relates to an apparatus and method for buffer management and reception interrupt processing between a medium access control hardware and a software processing apparatus, and more particularly, to a reception continuously generated between a medium access control hardware and a software processing apparatus of a wired / wireless communication system. An apparatus and method for buffer management and reception interrupt processing between a medium access control hardware and a software processing device, which can reduce the complexity of buffer management for interrupts and can efficiently handle a reception interrupt using a multi-buffer.

In general, when the media access control hardware processing apparatus receives a frame received from the modem by analyzing the header information of the received frame and receives the frame transmitted to itself, and the received frame is to be delivered to the media access control software processing apparatus, Store the received frame in the receive buffer. When the received frame is stored in the receive buffer, the media access control hardware processor delivers the receive interrupt to the media access control software processor.

Subsequently, the media access control software processor receiving the interrupt from the media access control hardware processor reads the received frame from the receive buffer in the media access control hardware processor and transfers it to its internal memory. At this time, if another frame is received from the modem while the media access control software processor reads the received frame, the media access control hardware processor discards the frame, or the receiving buffer in the media access control hardware processor has multiple frames. In the case of the dual port RAM having the capacity to process the continuous reception frame is continuously stored. At this time, when the media access control hardware processor generates an interrupt for every received frame, an interrupt is generated again in the process of processing the first received frame. The control hardware processor must use internally pending methods.

In both cases, however, the address of the dual port RAM and the length of the received frame should be stored at every interrupt occurrence. In this case, the media access control hardware processing apparatus may manage the dual port RAM in a ring buffer format, or discard a received frame when the dual port RAM exceeds a specific threshold.

However, the method of managing in a ring buffer format has a problem of high complexity of buffer management, and the method of discarding received frames has a problem of lowering performance of the entire system due to high data loss rate. In addition, the media access control hardware processing apparatus stores the received frame in the dual port RAM to process the received frame in real time. The frame does not need to be transmitted to the media access control software processing apparatus while analyzing the received frame header information. If it turns out or a Cyclic Redundancy Checking (CRC) error occurs, it must move back to the previous Dual Port RAM address.

By performing such buffer management in the media access control hardware processing device as described above, the logic becomes very complicated and the probability of error increases, and it is impossible to schedule the received frames by processing the received frames in order. There is a problem.

The present invention has been proposed to solve the above problems, and media access control for reducing the complexity of the buffer management for the reception interrupt generated continuously between the media access control hardware and software processing apparatus, and reducing the loss of discarding the received frame, etc. It is an object of the present invention to provide an apparatus and method for buffer management and reception interrupt processing between hardware and software processing devices.

It is another object of the present invention to provide an apparatus and method for buffer management and reception interrupt processing between a media access control hardware and a software processing apparatus for scheduling prioritizing received frames.

Other objects and advantages of the present invention can be understood by the following description, and will be more clearly understood by the embodiments of the present invention. Also, it will be readily appreciated that the objects and advantages of the present invention may be realized by the means and combinations thereof indicated in the claims.

In accordance with another aspect of the present invention, there is provided a buffer management and reception interrupt processing device between a media access control (MAC) hardware processing apparatus and a MAC software processing apparatus, wherein the hardware of the MAC software processing apparatus is generated when a hardware interrupt occurs due to frame reception. Address decoding means for decoding an internal address and concatenating it into a corresponding block; Interrupt status information providing means for constructing and providing a bitmap with information indicating the received frame storage status of each storage means as many bits as the number of storage means; Interrupt access information providing means for providing the MAC hardware processing apparatus with information for controlling access (simultaneous write) of the MAC hardware processing apparatus when updating the interrupt status information providing means of the MAC software processing apparatus; A plurality of storage means for storing the received frame; Receiving frame length information providing means for constructing a bitmap with the length information of the receiving frame stored in each storage means as many bits as the number of storage means, and providing the read frame when the receiving device reads (reads) the MAC software processing apparatus; On the basis of the information provided by the interrupt state information providing means, characterized in that it comprises a hardware interrupt control means for storing and controlling the received frame in the empty storage means.

Meanwhile, the present invention provides a buffer management and reception interrupt processing method between a media access control (MAC) hardware processing apparatus and a media access control (MAC) software processing apparatus. Confirming, selecting an empty receive buffer; The MAC hardware processing apparatus storing a received frame in the selected receive buffer; When the MAC hardware processing apparatus checks the interrupt access register and the MAC software processing apparatus does not write the interrupt status register, the receiving frame storage state (in the interrupt status register bit corresponding to the receiving buffer storing the receiving frame) Recording '1'); And performing a logical sum (OR) bit operation on all bits of the interrupt status register to connect to an interrupt output pin, and forwarding a hardware interrupt to the MAC software processor.

The present invention also provides a buffer management and reception interrupt processing method between a MAC hardware processing device and a MAC software processing device, the method comprising: detecting generation of a hardware interrupt indicating frame reception by the MAC software processing device; Checking, by the MAC software processor, an interrupt status register and selecting one of the interrupt status register bits corresponding to a receive buffer storing a received frame; Blocking, by the MAC software processor, access to the MAC hardware processor by displaying 'information indicating that the MAC software processor is writing the interrupt status register' in an interrupt access register; And reading the received frame by the frame length from the receive buffer corresponding to the selected bit by the MAC software processing device, and writing a received frame storage state ('0') to the interrupt status register bit. It is characterized by.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, whereby those skilled in the art may easily implement the technical idea of the present invention. There will be. In addition, in describing the present invention, when it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an embodiment of a buffer management and reception interrupt processing between a medium access control (MAC) hardware and a software processing apparatus according to the present invention.

As shown in FIG. 1, the apparatus 11 for buffer management and reception interrupt processing between the medium access control (MAC) hardware processing apparatus 10 and the medium access control (MAC) software processing apparatus 20 includes a frame reception. When the hardware interrupt occurs, the address decoding block 110 for decoding the hardware internal address of the MAC software processing unit 20 and connecting the corresponding blocks 120 to 160, and each receiving buffer 160 Update of the interrupt status register 140 of the medium access control (MAC) software processing device 20 and the interrupt status register 140 configured to provide a bitmap with bits indicating the number of reception buffers. At the same time, an intermediary providing information for controlling the access (simultaneous write) of the media access control (MAC) hardware processing apparatus 10 to the media access control (MAC) hardware processing apparatus 10. A bitmap is configured by using the interrupt access register 130, the plurality of receive buffers 160 storing the received frames, and the length information of the received frames stored in each receive buffer 160 as many bits as the number of receive buffers. On the basis of the information provided in the reception frame length register 120 and the interrupt status register 140 provided when the medium access control (MAC) software processing device 20 receives (reads) the received frame, the received frame is empty. A hardware interrupt control block 150 for controlling the storage in the receive buffer 160.

In FIG. 1, when a hardware interrupt indicating that a frame has been received has occurred, the media access control (MAC) software processing apparatus 20 sets the interrupt access register 130 to '1' to set the media access control (MAC) hardware processing apparatus ( After preventing 10 from writing the interrupt status register 140, check the interrupt status register 140 to see which receive buffer 160 has a receive frame. In this case, each of the registers 120 to 140 and the receiving buffer 150 has a hardware internal address so that the media access control (MAC) software processor 20 can access each block using the hardware internal address. Accordingly, the address decoding block 110 decodes the address information of the medium access control (MAC) software processing apparatus 20 and connects the corresponding block to the corresponding block.

The operation of each component of the apparatus 11 for buffer management and reception interrupt processing between the media access control hardware and the software processing apparatuses 10 and 20 having the above configuration will be described in more detail.

The interrupt access register 130 is introduced to solve a conflict problem that may occur when the media access control software processor 20 and the media access control hardware processor 10 try to write the interrupt status register 140 at the same time. As a register, the media access control hardware processor 10 sets the interrupt access register 130 bit to '1' when the media access control software processor 20 attempts to update the interrupt status register 140 bits. Updating the interrupt status register 140 bits at the same time as the media access control software processing device 20 can be prevented.

In addition, the interrupt status register 140 is a register indicating whether the reception data is currently stored in the reception buffer 160. The interrupt status register 140 includes bits as many as the number of the reception buffer 160. In this case, each bit represents an ID (ID) of the reception buffer 160 in a bitmap form. That is, the first bit of the interrupt status register 140 represents the state of the first receive buffer 160, and the Nth bit represents the state of the Nth receive buffer 160. Accordingly, when the bit of the interrupt status register 140 is set to '1', it means that a receive frame exists in the receive buffer 160 indicated by the bit.

Based on this, the media access control hardware processing apparatus 10 checks the interrupt status register 160 and stores the received frame in the empty receive buffer 160. If the interrupt access register 140 is '0', the interrupt status is interrupted. Update the corresponding bit in register 140 to '1'. The OR bit-operated interrupt status register 140 bits are coupled to the receive frame hardware register output pins and delivered to the media access control software processing device 20 as an interrupt. That is, if any one of the bits of the interrupt status register 140 has a value of '1', the interrupt is transmitted to the media access control software processing device 20.

Meanwhile, the reception buffer 160 has a size capable of supporting one medium access control maximum frame size. For example, the reception buffer 160 has a size of 2346 bytes or more in a wireless LAN, and has a size of 128 bytes or more in a Zigbee. In particular, each receive buffer 160 may store only the same type of receive frames, and the number of such receive buffers 160 may be arbitrarily determined according to the size, type, and transmission rate of the system. Since only one receiving frame of the same type is stored in one receiving buffer 160, the media access control hardware processing apparatus 10 does not have to perform complicated address management. The processor 20 may store the received frame in another receive buffer 160 while the processing device 20 reads (reads) the frame from one receive buffer 160. In addition, the media access control hardware processing apparatus 10 may give priority to the reception buffer 160 so that the media access control software processing apparatus 20 reads (reads) a received frame stored in a specific reception buffer preferentially. .

On the other hand, the receiving frame length register 120 is composed of as many bits as the number of the receiving buffer 160, each bit stores the length information of the receiving frame stored in each receiving buffer (160). Based on this, when the media access control software processing apparatus 20 reads the reception frame from the reception buffer 160, the media access control software processing apparatus 20 reads length information from the reception frame length register 120 and reads the reception frame by the corresponding frame length. .

Meanwhile, the hardware interrupt control unit 150 performs a function related to interrupt control when receiving a frame of the media access control hardware processing apparatus 10. That is, when the media access control hardware processing unit 10 receives a frame from the modem, the hardware interrupt control unit 150 checks the interrupt status register 140 to indicate a receive buffer indicated by the empty interrupt status register 140 bit ( If the received frame is a frame that does not need to be transmitted to the media access control software processing device 20 or a frame in which a CRC error occurs, the address of the receive buffer 160 is returned to its initial value. .

2 is a flowchart illustrating a buffer management and a reception interrupt processing method of a media access control hardware processing apparatus according to the present invention.

First, when the frame is received from the modem (201), the medium access control hardware processing apparatus 10 filters the address, frame type, etc. from the header information of the received frame (202), checks the interrupt status register 140 and receives it. The storage process of the received frame is started in the buffer 160 (203).

In this case, the media access control hardware processing apparatus 10 determines whether the received frame stored in the reception buffer 160 is a frame to be transmitted to the media access control software processing apparatus 20 (204), and stored in the reception buffer 160. If the received frame is a frame that does not need to be transmitted to the media access control software processing apparatus 20, after initializing the address of the receive buffer 160 (211), the frame returns to the frame receiving standby state (201), and receives the receive buffer ( If the received frame stored in 160 is a frame to be transmitted to the media access control software processing apparatus 20, the media access control hardware processing apparatus 20 performs a CRC check on the received frame (205). It is checked whether the frame is a frame in which a CRC error occurs (206).

As a result of the check 205, if the received frame is a frame in which a CRC error has occurred, the media access control hardware processing apparatus 10 initializes the address of the receive buffer 160 (212), and returns to a frame reception waiting state (2). If the received frame is a frame in which a CRC error does not occur, the received frame is stored in the receive buffer 160 (207).

That is, the media access control hardware processing apparatus 10 checks the interrupt status register 140 when receiving a frame from the modem, stores the received frame in the receive buffer 160 indicated by the empty interrupt status register bit, and processes the media access control software. The address of the reception buffer 160 is initialized when a frame does not need to be transmitted to the device 20 or when a CRC error occurs.

At this time, when storing the received frame in the reception buffer 160, the media access control hardware processing apparatus 10 checks the state of the interrupt access register 130 (208), the interrupt access register 130 is '0' If set to 0, the bit in the interrupt status register 140 that stores the received frame is set to '1' (209).

At this time, if the interrupt access register 130 is set to '1', the medium access control software processing apparatus 20 is updating the interrupt status register 140, and thus the medium access control hardware processing apparatus 10 Wait until the interrupt access register 130 becomes '0'.

Subsequently, the media access control hardware processing apparatus 10 connects the OR bit bits of the interrupt status register 140 to the interrupt output pin and transmits an interrupt to the media access control software processing apparatus 20 (210). In step 201, the apparatus returns to the frame receiving standby state.

3 is a flowchart illustrating a buffer management and reception interrupt processing method of a media access control software processing apparatus according to the present invention.

First, when the media access control software processing apparatus 20 detects a hardware interrupt that the frame has been received from the media access control hardware processing apparatus 10 (301), the media access control software processing apparatus 20 processes the media access control hardware processing. Checking the interrupt status register 140 of the device 10 (302) selects one of the bits set to '1' of the interrupt status register 140 (303).

In this case, the media access control software device 20 may preferentially read the received frames stored in the specific reception buffer 160 according to the priority designated by the media access control hardware processing device 10.

The media access control software processing apparatus 20 sets the interrupt access register 130 bit of the media access control hardware processing apparatus 10 to '1' to set the interrupt status register of the media access control hardware processing apparatus 10. 140, block access to the bit (304).

Finally, the media access control software processing apparatus 20 receives the received frame from the receive buffer 160 corresponding to the interrupt status register 140 bits selected based on the frame length information of the receive frame length register 120 bits. After reading as long as the frame length (305), the interrupt status register 140 bit of the corresponding reception buffer 160 is set to '0' (306), and returns to the interrupt reception waiting state.

4 is a diagram illustrating an embodiment of a buffer management and reception interrupt processing method of a media access control hardware processing apparatus according to the present invention.

As shown in FIG. 4, the media access control hardware processing apparatus 10 stores the first 'Frame 1' received from the modem in the 'Receive Buffer 1', which is the frame following the 'Frame 1' received from the modem. 'Frame 2' is stored in 'Receive Buffer 2', which is the next buffer after 'Receive Buffer 1', and 'Frame 3', which is the frame after 'Frame 2' received from the modem, is sequentially stored in 'Receive Buffer 3.' In this manner, frames received from the modem are sequentially stored in the reception buffer 160.

At this time, the interrupt access register 130 bit is set to '1' or '0' to indicate whether the media access control hardware processing apparatus 10 can update the interrupt status register 140 bit. That is, when the interrupt access register 130 bit is set to '1', the medium access control hardware processing apparatus 10 cannot update the status information of the reception buffer 160 in the interrupt status register 140 bit, If the interrupt access register 130 bit is set to '0', the media access control hardware processor 10 may update the status information of the receive buffer 160 in the interrupt status register 140 bit.

Meanwhile, the interrupt status register 140 bit sets the bits of the 'receive buffer 1', 'receive buffer 2', and 'receive buffer 3', in which the current frame is stored, to '1', and the current frame is not stored. The remaining receive buffer ('receive buffer N-1', 'receive buffer N') bits are set to '0' to indicate the state of the current receive buffer 160.

On the other hand, the reception frame length register 120 bit is a frame length '80 of 'receive buffer 1', 'receive buffer 2', 'receive buffer 3' stored 'frame 1', 'frame 2', 'frame 3' ',' 64 ', and' 120 'are stored in the corresponding bits, but' 0 'is stored in the corresponding bits because no frames are stored in the' receive buffer N-1 'and' receive buffer N '.

The method as shown in FIG. 4 may be used in the method of storing the initial frame in which the media access control hardware processing apparatus 10 receives the first frame from the modem and stores the received first frame in the reception buffer 160. Can be.

5 is a diagram illustrating another embodiment of a buffer management and reception interrupt processing method of a media access control hardware processing apparatus according to the present invention.

5 illustrates a method of designating four types of frame-specific receive buffers 160 defined in the IEEE 802.15.4 media access control standard and storing the same type of frames in one receive buffer 160. FIG.

As illustrated in FIG. 5, the media access control hardware processing apparatus 10 stores the 'beacon frame' received from the modem in the 'receive buffer 1', and receives the 'media access control command frame' received from the modem. Buffer 2 ',' data frame 'received from modem is stored in' receive buffer 3 ', and' ACK frame 'is stored in' receive buffer N-1 '. In this manner, the received frames are stored in the receive buffer 160 according to the type of the frames received from the modem.

At this time, the interrupt access register 130 bit is set to '1' or '0' to indicate whether the media access control hardware processing apparatus 10 can update the interrupt status register 140 bit. That is, the interrupt status register 140 bit sets the bits of 'Receive Buffer 1', 'Receive Buffer 2', 'Receive Buffer 3', and 'Receive Buffer N-1' where the current frame is stored as '1'. The remaining receive buffer ('receive buffer N') bit in which the current frame is not stored is set to '0' to indicate the state of the current receive buffer 160.

On the other hand, the interrupt status register 140 bits set the bits of 'Receive Buffer 1', 'Receive Buffer 2', 'Receive Buffer 3', and 'Receive Buffer N-1' where the current frame is stored to '1'. The remaining receive buffer ('receive buffer N') bit in which the current frame is not stored is set to '0' to indicate the state of the current receive buffer 160.

On the other hand, the reception frame length register 120 bits include 'receive buffer 1', 'receive buffer 2', and 'receive' stored 'beacon frame', 'media access control command frame', 'data frame', 'ACK frame'. The frame length '80', '64', '120', and '5' of buffer 3 'and' receive buffer N-1 'are stored in the corresponding bits, but no frame is stored in' receive buffer N '. Therefore, '0' is stored in the corresponding bit.

The media access control hardware processing apparatus 10 assigns a priority to the reception buffer 160 based on the method of FIG. 5, which designates the reception buffer 160 for each type of reception frame, thereby processing the media access control software. The device 20 may cause the received frame to be read according to the priority of the designated receive buffer 160.

As described above, the method of the present invention may be implemented as a program and stored in a recording medium (CD-ROM, RAM, ROM, floppy disk, hard disk, magneto-optical disk, etc.) in a computer-readable form. Since this process can be easily implemented by those skilled in the art will not be described in more detail.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited by the drawings.

As described above, the present invention reduces the complexity of the buffer management for the reception interrupt processing generated by using a single buffer between the media access control hardware and the software processing device, and solves the problem of discarding the received frame, such as the overhead of retransmission. By reducing, there is an effect that can improve the performance of the communication system.

In addition, the media access control hardware processor stores the same type of receive frames in each receive buffer and gives priority to each receive buffer so that the medium access control software processor can read the received frames according to the priority of the receive buffer. It is effective.

Claims (15)

A buffer management and reception interrupt processing device between a MAC and a MAC software processing device, Address decoding means for decoding a hardware internal address of the MAC software processing unit and connecting the block to a corresponding block when a hardware interrupt occurs due to frame reception; Interrupt status information providing means for constructing and providing a bitmap with information indicating the received frame storage status of each storage means as many bits as the number of storage means; Interrupt access information providing means for providing the MAC hardware processing apparatus with information for controlling access (simultaneous write) of the MAC hardware processing apparatus when updating the interrupt status information providing means of the MAC software processing apparatus; A plurality of storage means for storing the received frame; Receiving frame length information providing means for constructing a bitmap with the length information of the receiving frame stored in each storage means as many bits as the number of storage means, and providing the read frame when the receiving device reads (reads) the MAC software processing apparatus; Hardware interrupt control means for storing and controlling the received frame in an empty storage means based on the information provided by the interrupt state information providing means Apparatus for buffer management and reception interrupt processing between the media access control hardware and software processing apparatus comprising a. The method of claim 1, The plurality of storage means, Media access control hardware and software processing apparatus having a size that can support one MAC maximum frame size, the number is determined according to the system size and type, transmission rate, each storage means stores the received frame sequentially Device for managing buffers and receiving interrupts between nodes. The method of claim 1, The plurality of storage means, Media access control hardware and software processing having a size that can support one MAC maximum frame size, the number is determined according to the system size, type, and transmission rate, and the same type of receiving frame is stored for each storage means. Device for buffer management and receive interrupt handling between devices. The method of claim 3, wherein Each of the plurality of storage means, Apparatus for buffer management and reception interrupt processing between a medium access control hardware and a software processing device, characterized in that the read (read) priority is different. The method according to any one of claims 1 to 4, The interrupt access information providing means, When the MAC software processor updates the interrupt status information providing means, the MAC hardware processor informs the information for preventing the interrupt status information providing means from being updated at the same time, so that the MAC software processor and the MAC are updated. An apparatus for buffer management and reception interrupt processing between a media access control hardware and a software processing apparatus, which can solve a conflict problem that may occur when a hardware processing apparatus attempts to simultaneously use the interrupt status information providing means. The method of claim 5, wherein Each bit of the bitmap in the interrupt state information providing means, A device for buffer management and receive interrupt processing between a media access control hardware and a software processing device, characterized by indicating the ID of the storage means. The method of claim 6, Each bit of the interrupt status information providing means, And an OR operation, connected to a receiving frame hardware register output pin and delivered to the MAC software processing unit as an interrupt, for buffer management and receiving interrupt processing between the medium access control hardware and the software processing unit. The method of claim 7, wherein The hardware interrupt control means, Checking the interrupt status information providing means upon receiving a frame, the received frame is stored in a storage means indicated by a bit of the empty interrupt status information providing means and does not need to be transmitted to the MAC software processing device or a cyclic redundancy check (CRC). An apparatus for buffer management and reception interrupt processing between a medium access control hardware and a software processing apparatus, characterized in that the address of the storage means is initialized when an error occurs. In the buffer management and reception interrupt processing method between a MAC (Media Access Control) hardware processing unit and a MAC (Media Access Control) software processing unit, Upon receipt of a frame, the MAC hardware processor checking an interrupt status register to select an empty receive buffer; The MAC hardware processing apparatus storing a received frame in the selected receive buffer; When the MAC hardware processing apparatus checks the interrupt access register and the MAC software processing apparatus does not write the interrupt status register, the reception frame storing status (in the interrupt status register bit corresponding to the receiving buffer storing the receiving frame) Recording '1'); And The MAC hardware processor performing an OR bit on all bits of the interrupt status register and connecting them to an interrupt output pin to deliver a hardware interrupt to the MAC software processor; A buffer management and reception interrupt processing method between a media access control (MAC) hardware processing apparatus and a media access control (MAC) software processing apparatus. In the buffer management and reception interrupt processing method between a MAC (Media Access Control) hardware processing unit and a MAC software processing unit, Detecting, by the MAC software processor, the occurrence of a hardware interrupt indicating frame reception; Checking, by the MAC software processor, an interrupt status register and selecting one of the interrupt status register bits corresponding to a receive buffer storing a received frame; Blocking, by the MAC software processor, access to the MAC hardware processor by displaying 'information indicating that the MAC software processor is writing the interrupt status register' in an interrupt access register; And After the MAC software processor reads a received frame from the receive buffer corresponding to the selected bit by the frame length, and writes a received frame storage state ('0') to the interrupt status register bit. A buffer management and reception interrupt processing method between a media access control (MAC) hardware processing apparatus and a media access control (MAC) software processing apparatus. The method according to claim 9 or 10, The reception buffer is, It has a size that can support one MAC maximum frame size, and the number is determined according to the system size, type, and transmission rate, and each receive buffer stores receive frames sequentially or the same type of receive frames are stored for each receive buffer. And a buffer management and reception interrupt processing method between a media access control (MAC) hardware processing apparatus and a media access control (MAC) software processing apparatus. The method of claim 11, Each of the receive buffers, A buffer management and receive interrupt processing method between a medium access control (MAC) hardware processing device and a medium access control (MAC) software processing device, characterized by different read (read) priorities. The method of claim 11, The interrupt access register, When the MAC software processor updates the interrupt status register, the MAC hardware processor blocks the MAC status processor from simultaneously updating the interrupt status register. MAC) A method for managing buffers and receiving interrupts between software processing devices. The method of claim 13, The interrupt status register, Provides information indicating the reception frame storage state of each reception buffer by configuring a bitmap with the number of bits of the reception buffer, wherein each bit of the bitmap indicates an ID of the corresponding reception buffer. (MAC) A buffer management and receive interrupt processing method between a hardware processing unit and a media access control (MAC) software processing unit. The method of claim 9, The OR bit operation is If any one of the bits of the interrupt status register has a value of '1', a hardware interrupt is transmitted to the MAC software processing device. How to manage buffers and receive interrupts between devices.

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