KR100819744B1 - 3d structure laminated compound semiconductor solid-state image sensor and a method for manufacturing the same - Google Patents

3d structure laminated compound semiconductor solid-state image sensor and a method for manufacturing the same Download PDF

Info

Publication number
KR100819744B1
KR100819744B1 KR1020070013620A KR20070013620A KR100819744B1 KR 100819744 B1 KR100819744 B1 KR 100819744B1 KR 1020070013620 A KR1020070013620 A KR 1020070013620A KR 20070013620 A KR20070013620 A KR 20070013620A KR 100819744 B1 KR100819744 B1 KR 100819744B1
Authority
KR
South Korea
Prior art keywords
type
photodiode
signal detection
region
layer
Prior art date
Application number
KR1020070013620A
Other languages
Korean (ko)
Inventor
한건희
김보경
윤일구
명재민
Original Assignee
연세대학교 산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 연세대학교 산학협력단 filed Critical 연세대학교 산학협력단
Priority to KR1020070013620A priority Critical patent/KR100819744B1/en
Application granted granted Critical
Publication of KR100819744B1 publication Critical patent/KR100819744B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H01L27/14607—Geometry of the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14692—Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Nanotechnology (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

A 3-dimensional structure laminated compound semiconductor solid-state image sensor and a method for manufacturing the same are provided to reduce the degradation of photosensitive efficiency and charge capacity and to implement a micro pixel by maximizing a photoresist area of a photodiode to increase the amount of incident light. A photodiode region(206) is formed on a first conductive type semiconductor substrate(204) and comprised of a second conductive type impurity layer. A signal detection region(208) is separated from the photodiode region and comprised of a second conductive type impurity layer. Plural metal lines(203) are electrically connected to the signal detection region. A transfer gate(202) is formed on the first conductive type semiconductor substrate. The transfer gate is connected to transmit charges between the photodiode region and the signal detection region. Plural interlayer dielectrics(210) are formed on the first conductive type semiconductor substrate including the photodiode region, the transfer gate, and the signal detection region. A compound semiconductor epi layer(201) is formed by implanting P type and N type impurities into a space between each interlayer dielectric. The space is formed by etching the interlayer dielectric.

Description

3차원 구조의 화합물 반도체 적층형 이미지센서용 포토다이오드 및 그 제조방법{3D structure laminated compound semiconductor solid-state image sensor and a method for manufacturing the same}3D structure laminated compound semiconductor solid-state image sensor and a method for manufacturing the same}

도 1은 종래의 이미지센서의 개략적 구조도 및 APS 회로도,1 is a schematic structural diagram and APS circuit diagram of a conventional image sensor;

도 2는 본 발명에 따른 3차원 구조의 화합물 반도체 적층형 이미지센서용 포토다이오드의 일실시예로서, 그 제조 공정을 설명하는 단면도.2 is a cross-sectional view illustrating a manufacturing process of the photodiode for the compound semiconductor stacked image sensor having a three-dimensional structure according to the present invention.

<도면의 주요한 부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

101 : 전달게이트101: transfer gate

102 : 포토다이오드영역102: photodiode area

103 : 신호검출 회로부103: signal detection circuit

201 : 화합물 반도체 에피층201: compound semiconductor epi layer

202 : 전달게이트202: transfer gate

203 : 메탈라인203 metal line

204 : 반도체기판204: semiconductor substrate

206 : 포토다이오드 영역206: photodiode region

208 : 신호검출영역208: signal detection area

210 : 층간절연층210: interlayer insulating layer

본 발명은 3차원 구조의 화합물 반도체 적층형 이미지센서용 포토다이오드 및 그 제조 방법에 관한 것으로서, 더욱 상세하게는 빛의 수광 면적을 극대화시킨 구조의 3차원 구조의 화합물 반도체 적층형 이미지센서용 포토다이오드 및 그 제조 방법에 관한 것이다.The present invention relates to a photodiode for a compound semiconductor stacked image sensor having a three-dimensional structure and a manufacturing method thereof, and more particularly to a photodiode for a compound semiconductor stacked image sensor having a three-dimensional structure having a structure in which a light receiving area is maximized. It relates to a manufacturing method.

주지된 바와 같이, 이미지 인식 소자로 사용되는 이미지센서는 빛을 감지하는 광감지 부분과 감지된 빛을 전기 신호로 바꾸어 처리해주는 회로 부분으로 구성되어 있다.As is well known, an image sensor used as an image recognition element is composed of a light sensing portion for detecting light and a circuit portion for converting and processing the detected light into an electrical signal.

상기 광감지부는 단위화소로 입사하는 빛을 전자정공쌍으로 바꾸어 주는 포토다이오드로 이루어져 있으며, 통상 포토다이오드는 실리콘 기판 내부에 불순물 이온 주입 공정을 통하여 형성된다.The light sensing unit includes a photodiode for converting light incident on a unit pixel into an electron hole pair, and a photodiode is usually formed through an impurity ion implantation process in a silicon substrate.

이렇게 구성된 포토다이오드에서는 불순물 접합층에 가해지는 역방향 바이어스에 의하여 공핍층이 형성되고, 시간이 지남에 따라 상기 공핍층에 누적되는 전하의 양을 회로적으로 읽어냄으로써 영상신호를 복원해낼 수 있다.In the photodiode configured as described above, the depletion layer is formed by the reverse bias applied to the impurity junction layer, and the image signal can be restored by reading out the amount of charge accumulated in the depletion layer over time.

따라서, 상기 포토다이오드의 공핍층에 충분한 전하가 누적되기 위해서는 포토다이오드의 넓은 면적 확보가 중요하며, 이를 통하여 이미지센서의 우수한 광감도 특성을 얻어낼 수 있다.Therefore, in order to accumulate sufficient charge in the depletion layer of the photodiode, it is important to secure a large area of the photodiode, thereby obtaining excellent light sensitivity characteristics of the image sensor.

그러나, 상술한 종래의 이미지센서에서는 포토다이오드가 단위화소 안에 신호 검출을 위한 회로 부분과 동일한 평면에 형성되기 때문에, 포토다이오드의 면적 확보에 한계가 있고, 그로 인하여 우수한 광감도 특성을 얻어내기 어려운 문제점이 있다.However, in the above-described conventional image sensor, since the photodiode is formed on the same plane as the circuit portion for detecting the signal in the unit pixel, there is a limit in securing the area of the photodiode, which makes it difficult to obtain excellent light sensitivity characteristics. have.

첨부한 도 1은 종래의 이미지센서의 개략적 구조 및 APS 회로를 도시하고 있다.1 shows a schematic structure and APS circuit of a conventional image sensor.

도 1에 도시된 종래의 이미지센서는 단위화소 안에 포토다이오드 영역(102)과, 신호 검출을 위한 신호검출 회로부(103)가 동일한 평면에 형성되어 있고, 그 사이에는 신호 교환을 위한 전달게이트(101)가 형성되어 있다.In the conventional image sensor shown in FIG. 1, a photodiode region 102 and a signal detection circuit 103 for signal detection are formed on the same plane in a unit pixel, and a transfer gate 101 for signal exchange therebetween. ) Is formed.

또한, 상기 신호검출 회로부(103) 즉, 4개의 트랜지스터를 갖는 4T APS 회로는 리셋단자(RST), 전달게이트(TX), 소스팔로워(SF), 열선택단자(Sel)를 포함하고 있다.In addition, the signal detection circuit unit 103, that is, a 4T APS circuit having four transistors includes a reset terminal RST, a transfer gate TX, a source follower SF, and a column select terminal Sel.

한편, 도 1에 도시된 통상적인 이미지센서의 포토다이오드는 이온 주입 공정을 통하여 실리콘기판 내부에 불순물이 주입되어 형성된다.Meanwhile, the photodiode of the conventional image sensor illustrated in FIG. 1 is formed by implanting impurities into a silicon substrate through an ion implantation process.

상기 이미지센서의 동작을 보면, 입사된 빛(L)이 포토다이오드 영역(102)의 공핍층 부분에서 전자정공쌍으로 변환되고, 빛의 세기에 비례하여 형성되는 전자정공쌍의 양은 신호검출 회로부(103)을 통하여 신호로 얻어진다.Referring to the operation of the image sensor, the incident light L is converted into the electron hole pair in the depletion layer portion of the photodiode region 102, and the amount of the electron hole pair formed in proportion to the light intensity is the signal detection circuit unit ( Through 103).

그러나, 도 1에 도시된 종래의 이미지센서에 사용되는 포토다이오드는 전술한 바와 같이, 공핍층에 충분한 전하가 누적되기 위해서는 포토다이오드의 넓은 면적 확보가 중요하며 이를 통하여 이미지센서의 우수한 광감도 특성을 얻어낼 수 있지만, 포토다이오드가 단위화소 안에 신호 검출을 위한 회로 부분과 동일한 평면에 형성되어 있기 때문에, 결국 포토다이오드의 면적 확보에 한계가 있고, 그로 인하여 우수한 광감도 특성을 얻어내기 어려운 단점이 있다.However, as described above, in the photodiode used in the conventional image sensor illustrated in FIG. 1, it is important to secure a large area of the photodiode in order to accumulate sufficient charge in the depletion layer, thereby obtaining excellent light sensitivity characteristics of the image sensor. However, since the photodiode is formed on the same plane as the circuit portion for signal detection in the unit pixel, there is a limit in securing the area of the photodiode, which makes it difficult to obtain excellent light sensitivity characteristics.

이에, 포토다이오드의 넓은 면적을 확보하여, 빛을 보다 용이하게 수광할 수 있는 구조의 포토다이오드의 개발이 요구되고 있다.Accordingly, there is a demand for developing a photodiode having a structure in which a large area of the photodiode can be secured and light can be more easily received.

본 발명은 상기와 같은 종래 이미지센서에 사용되는 포토다이오드의 면적 확보와 관련된 문제점을 해결하기 위하여 안출된 것으로서, 이미지센서용 포토다이오드의 감광 면적을 극대화하여 입사하는 빛의 양을 극대화시켜줌으로써, 반도체 칩이 소형화됨에 따라 나타나는 광감응 효율의 저하 및 전하 용량의 저하를 개선시켜줄 수 있고, 포토다이오드에 입사하는 빛의 투과도를 높임으로써, 특히 투과도가 낮은 단파장 빛에 대한 광감응 효율을 높여줄 수 있도록 한 3차원 구조의 화합물 반도체 적층형 이미지센서용 포토다이오드 및 그 제조방법을 제공하는데 그 안출의 목적이 있다.The present invention has been made to solve the problems associated with securing the area of the photodiode used in the conventional image sensor as described above, by maximizing the amount of light incident by maximizing the photosensitive area of the photodiode for the image sensor, the semiconductor As the size of the chip becomes smaller, it is possible to improve the photosensitive efficiency and the lowering of the charge capacity, and to increase the light transmittance incident on the photodiode. It is an object of the present invention to provide a photodiode for a compound semiconductor stacked image sensor having a three-dimensional structure and a manufacturing method thereof.

상기한 목적을 달성하기 위한 본 발명의 3차원 구조의 화합물 반도체 적층형 이미지센서용 포토다이오드는: To achieve the above object, a photodiode for a compound semiconductor stacked image sensor having a three-dimensional structure of the present invention is:

제1도전형(P형) 반도체기판과; 상기 제1도전형(P형) 반도체기판 위에 형성되며, 제2도전형(N형)의 불순물층으로 이루어진 포토다이오드 영역과; 상기 포토다이오드 영역과 이격 형성되며, 제2도전형(N형) 불순물층으로 이루어진 신호검출영역과; 상기 신호검출영역에 전기적으로 연결되는 복수의 메탈라인과; 상기 제1도전형(P형) 반도체기판 위에 형성되며, 상기 포토다이오드 영역과 신호검출영역간에 전하를 전송하기 위하여 연결된 전달게이트와; 상기 포토다이오드 영역 및 전달게이트, 신호검출영역을 포함하는 상기 제1도전형(P형) 반도체기판 위에 형성된 복수의 층간절연층과; 상기 층간절연층이 식각되어 형성된 각 층간절연층의 사이공간에 P형 및 N형 불순물 주입으로 이루어진 화합물 반도체 에피층; 을 포함하여 구성된 것을 특징으로 한다.A first conductive type (P type) semiconductor substrate; A photodiode region formed on the first conductive type (P type) semiconductor substrate and formed of an impurity layer of a second conductive type (N type); A signal detection region formed spaced apart from the photodiode region and formed of a second conductivity type (N-type) impurity layer; A plurality of metal lines electrically connected to the signal detection area; A transfer gate formed on the first conductivity type (P type) semiconductor substrate and connected to transfer charge between the photodiode region and the signal detection region; A plurality of interlayer insulating layers formed on the first conductive type (P-type) semiconductor substrate including the photodiode region, the transfer gate, and the signal detection region; A compound semiconductor epi layer comprising P-type and N-type impurity implants in the interspaces of the interlayer insulating layers formed by etching the interlayer insulating layers; Characterized in that configured to include.

바람직한 구현예로서, 상기 층간절연층은 피라미드 모양이 되도록 사선으로 식각되고, 각 층간절연층의 사이공간은 상기 화합물 반도체 에피층이 성장되도록 역피라미드 모양의 공간으로 남게 된 것을 특징으로 한다.In an exemplary embodiment, the interlayer insulating layer is etched diagonally to form a pyramid shape, and the interspace of each interlayer insulating layer is left as an inverse pyramid-shaped space so that the compound semiconductor epitaxial layer is grown.

상기한 목적을 달성하기 위한 본 발명의 3차원 구조의 화합물 반도체 적층형 이미지센서용 포토다이오드 제조 방법은:Method of manufacturing a photodiode for a compound semiconductor stacked image sensor of the three-dimensional structure of the present invention for achieving the above object:

제1도전형(P형) 반도체기판 위에 포토다이오드 영역이 되는 제2도전형(N형)의 불순물층과, 복수의 메탈라인이 전기적으로 연결되어 신호검출영역이 되는 제2도전형(N형) 불순물층을 형성하는 단계와; 상기 포토다이오드 영역과 신호검출영역간에 전하를 전송하기 위한 게이트로 사용되는 전달게이트를 형성하는 단계와; 상기 포토다이오드 영역 및 전달게이트, 신호검출영역를 포함하는 상기 제1도전형(P형) 반도체기판 위쪽으로 복수의 층간절연층이 증착되는 단계와; 상기 층간절연층을 넓은 면적으로 빛(L)이 수광될 수 있는 형상으로 식각(etching) 하는 단계와; 상기 식각 공정에 의하여 형성된 각 층간절연층의 사이공간에 하부층에는 N형 불순물이 주입되고 상층부에는 P형 불순물층이 형성된 구조의 화합물 반도체 에피층을 형성하는 단계; 를 포함하여 이루어진 것을 특징으로 한다.The second conductive type (N type) impurity layer of the second conductive type (N type), which becomes a photodiode region on the first conductive type (P type) semiconductor substrate, and the plurality of metal lines are electrically connected to form a signal detection region. ) Forming an impurity layer; Forming a transfer gate used as a gate for transferring charge between the photodiode region and the signal detection region; Depositing a plurality of interlayer dielectric layers over the first conductive (P-type) semiconductor substrate including the photodiode region, the transfer gate, and the signal detection region; Etching the interlayer insulating layer into a shape in which light (L) can be received with a large area; Forming a compound semiconductor epitaxial layer having a structure in which an N-type impurity is injected into a lower layer and a P-type impurity layer is formed in an upper portion of the interlayer insulating layer formed by the etching process; Characterized in that comprises a.

바람직한 구현예로서, 상기 층간절연층을 피라미드 모양이 되도록 사선으로 식각하여, 각 층간절연층의 사이공간이 역피라미드 모양의 공간으로 남도록 하는 것을 특징으로 한다.In a preferred embodiment, the interlayer insulating layer is etched diagonally so as to have a pyramid shape, so that the interspace of each interlayer insulating layer remains as an inverted pyramid shaped space.

이하, 본 발명의 바람직한 일 실시예를 첨부도면을 참조로 상세하게 설명하기로 한다.Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

첨부한 도 2는 본 발명에 따른 3차원 구조의 화합물 반도체 적층형 이미지센서용 포토다이오드 및 그 제조 방법에 대한 일 실시예를 설명하는 단면도이다.2 is a cross-sectional view illustrating an embodiment of a photodiode for a compound semiconductor stacked image sensor having a three-dimensional structure and a method of manufacturing the same according to the present invention.

먼저, 제1도전형(P형) 반도체기판(204) 위에 포토다이오드 영역(206)이 되는 제2도전형(N형)의 불순물층과 이 불순물층에 인접되게 전달게이트(202)를 형성하고, 바로 옆쪽에는 신호검출영역(208)이 되는 제2도전형(N형) 불순물층을 형성한다.First, an impurity layer of the second conductivity type (N type) that becomes the photodiode region 206 and a transfer gate 202 adjacent to the impurity layer are formed on the first conductivity type (P type) semiconductor substrate 204. Next to the side, a second conductive (N-type) impurity layer serving as the signal detection region 208 is formed.

보다 상세하게는, 상기 제1도전형(P형) 반도체기판(204) 위에 제2도전형(N형)의 불순물층인 포토다이오드 영역(206) 및 신호검출영역(208)을 이격 형성하고, 포토다이오드 영역(206)에서 신호검출영역(208)으로 전하를 전송하기 위한 게이트로 사용되는 트랜스퍼 트랜지스터의 게이트 전극을 말하는 전달게이트(202)를 형성한다.More specifically, the photodiode region 206 and the signal detection region 208 which are impurity layers of the second conductive type (N type) are spaced apart from each other on the first conductive type (P type) semiconductor substrate 204, A transfer gate 202 is formed that refers to the gate electrode of the transfer transistor used as a gate for transferring charge from the photodiode region 206 to the signal detection region 208.

이때, 상기 제2도전형(N형) 불순물층은 마스크 및 이온주입공정을 통해 N형 불순물 이온주입을 실시하여 형성된다.In this case, the second conductivity type (N-type) impurity layer is formed by performing N-type impurity ion implantation through a mask and an ion implantation process.

다음으로, 상기와 같은 전압감지부 즉, 포토다이오드 영역(206) 및 전달게이트(202), 그리고 신호검출영역(208)를 포함하는 상기 제1도전형(P형) 반도체기판(204) 위쪽으로 복수의 층간절연층(210)이 증착된다.Next, above the first conductive type (P-type) semiconductor substrate 204 including the voltage sensing unit, that is, the photodiode region 206, the transfer gate 202, and the signal detection region 208. A plurality of interlayer insulating layers 210 are deposited.

이때, 상기 신호검출영역(208) 위에는 복수의 메탈라인(203)이 전기적으로 연결되며, 이 메탈라인(203)은 신호검출회로부(미도시됨)쪽으로 전기적으로 연결되며, 녹는점(용융점)이 높은 금속전극을 사용하여 회로를 형성하게 된다.In this case, a plurality of metal lines 203 are electrically connected to the signal detection region 208, and the metal lines 203 are electrically connected to the signal detection circuit unit (not shown), and a melting point (melting point) is The circuit is formed using a high metal electrode.

다음으로, 상기 층간절연층(210)을 식각(etching)하는 공정이 진행되는데, 층간절연층(210)을 피라미드 모양이 되도록 사선으로 식각하여, 층간절연층(210) 사이 공간이 역피라미드 모양의 공간으로 남도록 한다.Next, a process of etching the interlayer insulating layer 210 is performed. The interlayer insulating layer 210 is etched diagonally so as to form a pyramid shape, and the space between the interlayer insulating layer 210 is inverted pyramid shape. Leave it as space.

이어서, 식각 공정에 의하여 형성된 각 층간절연층(210)의 사이공간에 화합물 반도체 에피층(201)이 형성되는데, 이 에피층(201)의 형성 중에 에피층(201)내부에 불순물 가스를 in stew로 주입한 후, 어닐링을 통하여 활성화시킴으로써 화합물 반도체의 PN 접합을 구현해 낸다.Subsequently, a compound semiconductor epitaxial layer 201 is formed in the interspace of each interlayer insulating layer 210 formed by an etching process, and during the formation of the epitaxial layer 201, impurity gas is introduced into the epitaxial layer 201 in stew. PN junction of the compound semiconductor is implemented by injecting into and then activating through annealing.

즉, 사선으로 식각된 층간절연층(210) 사이에 하부층에는 2도전형(N형) 화합물반도체 에피층(201)이 형성되며, 이 화합물반도체 에피층(201)의 상층부에는 불순물 주입으로 제1도전형(P형) 불순물층이 형성된다.That is, a two-conducting (N-type) compound semiconductor epitaxial layer 201 is formed in the lower layer between the interlayer insulating layers 210 etched diagonally, and the first layer of the compound semiconductor epitaxial layer 201 is implanted with impurities. A conductive (P type) impurity layer is formed.

삭제delete

삭제delete

따라서, 상기 층간절연층(210)을 피라미드 형상으로 형성하여 포토다이오드 영역(206)으로 흡수되는 빛의 수광 면적이 넓어지게 되어, 결국 본 발명의 포토다이오드는 넓은 면적으로 빛(L)을 흡수할 수 있게 되고, 포토다이오드의 감광 면적을 극대화함으로써, 기존의 포토다이오드에서 제한되었던 광감응 효율을 크게 개선시킬 수 있게 된다.Therefore, the interlayer insulating layer 210 is formed in a pyramid shape, so that the light receiving area of light absorbed by the photodiode region 206 is widened. Therefore, the photodiode of the present invention absorbs light L in a large area. In addition, by maximizing the photosensitive area of the photodiode, it is possible to greatly improve the photosensitive efficiency that has been limited in the conventional photodiode.

이상에서 본 바와 같이, 본 발명에 따른 3차원 구조의 화합물 반도체 적층형 이미지센서용 포토다이오드 및 그 제조방법에 의하면, 이미지센서용 포토다이오드의 감광면적을 극대화하여 입사하는 빛의 양을 극대화시켜줌으로써, 칩이 소형화됨에 따라 나타나는 광감응 효율의 저하 및 전하 용량의 저하를 개선시켜줄 수 있어 극소형 픽셀의 구현을 가능하게 해준다.As described above, according to the three-dimensional compound semiconductor stacked image sensor photodiode and the manufacturing method of the three-dimensional structure according to the present invention, by maximizing the photosensitive area of the image sensor photodiode to maximize the amount of incident light, As the chip becomes smaller, the degradation of the photosensitive efficiency and the reduction of the charge capacity can be improved, thereby enabling the implementation of the smallest pixel.

또한, 포토다이오드에 입사하는 빛의 투과도를 높임으로써, 특히 투과도가 낮은 단파장 빛에 대한 광감응 효율을 높여줄 수 있다.In addition, by increasing the transmittance of light incident on the photodiode, it is possible to increase the light-sensing efficiency, especially for short wavelength light having low transmittance.

삭제delete

삭제delete

Claims (4)

제1도전형(P형) 반도체기판(204)와;A first conductive (P type) semiconductor substrate 204; 상기 제1도전형(P형) 반도체기판(204) 위에 형성되며, 제2도전형(N형)의 불순물층으로 이루어진 포토다이오드 영역(206)과;A photodiode region 206 formed on the first conductive type (P type) semiconductor substrate 204 and formed of an impurity layer of a second conductive type (N type); 상기 포토다이오드 영역(206)과 이격 형성되며, 제2도전형(N형) 불순물층으로 이루어진 신호검출영역(208)과;A signal detection region 208 spaced apart from the photodiode region 206 and formed of a second conductivity type (N-type) impurity layer; 상기 신호검출영역(208)에 전기적으로 연결되는 복수의 메탈라인(203)과;A plurality of metal lines 203 electrically connected to the signal detection area 208; 상기 제1도전형(P형) 반도체기판(204) 위에 형성되며, 상기 포토다이오드 영역(206))과 신호검출영역(208))간에 전하를 전송하기 위하여 연결된 전달게이트(202)와;A transfer gate 202 formed on the first conductivity type (P-type) semiconductor substrate 204 and connected to transfer charge between the photodiode region 206 and the signal detection region 208; 상기 포토다이오드 영역(206) 및 전달게이트(202), 신호검출영역(208)를 포함하는 상기 제1도전형(P형) 반도체기판(204) 위에 형성된 복수의 층간절연층(210)과;A plurality of interlayer insulating layers 210 formed on the first conductive type (P-type) semiconductor substrate 204 including the photodiode region 206, the transfer gate 202, and the signal detection region 208; 상기 층간절연층(210)이 식각되어 형성된 각 층간절연층(210)의 사이공간에 P형 및 N형 불순물 주입으로 이루어진 화합물 반도체 에피층(201);A compound semiconductor epitaxial layer 201 formed of P-type and N-type impurity implants in a space between the interlayer insulating layers 210 formed by etching the interlayer insulating layer 210; 을 포함하여 구성된 것을 특징으로 하는 3차원 구조의 화합물 반도체 적층형 이미지센서용 포토다이오드.Photodiode for compound semiconductor stacked image sensor having a three-dimensional structure comprising a. 청구항 1에 있어서,The method according to claim 1, 상기 층간절연층(210)은 피라미드 모양이 되도록 사선으로 식각되고, 각 층간절연층의 사이공간은 상기 화합물 반도체 에피층(201)이 성장되도록 역피라미드 모양의 공간으로 남게 된 것을 특징으로 하는 3차원 구조의 화합물 반도체 적층형 이미지센서용 포토다이오드.The interlayer dielectric layer 210 is etched diagonally to form a pyramid shape, and the interspace of each interlayer dielectric layer is left as an inverse pyramid-shaped space so that the compound semiconductor epitaxial layer 201 is grown. Photodiode for compound semiconductor stacked image sensor with structure. 제1도전형(P형) 반도체기판(204) 위에 포토다이오드 영역(206)이 되는 제2도전형(N형)의 불순물층과, 복수의 메탈라인(203)이 전기적으로 연결되어 신호검출영역(208)이 되는 제2도전형(N형) 불순물층을 형성하는 단계와;The second conductive type (N-type) impurity layer, which becomes the photodiode region 206, and the plurality of metal lines 203 are electrically connected to the first conductive type (P-type) semiconductor substrate 204 to form a signal detection region. Forming a second conductive (N-type) impurity layer to be (208); 상기 포토다이오드 영역(206)과 신호검출영역(208)간에 전하를 전송하기 위한 게이트로 사용되는 전달게이트(202)를 형성하는 단계와;Forming a transfer gate (202) used as a gate for transferring charge between the photodiode region (206) and the signal detection region (208); 상기 포토다이오드 영역(206) 및 전달게이트(202), 신호검출영역(208)를 포함하는 상기 제1도전형(P형) 반도체기판(204) 위쪽으로 복수의 층간절연층(210)이 증착되는 단계와;A plurality of interlayer insulating layers 210 are deposited on the first conductive P-type semiconductor substrate 204 including the photodiode region 206, the transfer gate 202, and the signal detection region 208. Steps; 상기 층간절연층(210)을 넓은 면적으로 빛(L)이 수광될 수 있는 형상으로 식각(etching)하는 단계와;Etching the interlayer dielectric layer 210 into a shape such that light L can be received in a large area; 상기 식각 공정에 의하여 형성된 각 층간절연층(210)의 사이공간에 하층부에N형 불순물과 상층부에 P형 불순물이 주입된 화합물 반도체 에피층(201)을 형성하는 단계;Forming a compound semiconductor epitaxial layer (201) in which an N-type impurity is formed in a lower layer and a P-type impurity is injected in an upper layer in a space between the interlayer insulating layers 210 formed by the etching process; 를 포함하여 이루어진 것을 특징으로 하는 3차원 구조의 화합물 반도체 적층형 이미지센서용 포토다이오드 제조 방법.The photodiode manufacturing method for a compound semiconductor stacked image sensor having a three-dimensional structure comprising a. 청구항 3에 있어서,The method according to claim 3, 상기 층간절연층(210)을 피라미드 모양이 되도록 사선으로 식각하여, 각 층간절연층(210)의 사이공간이 역피라미드 모양의 공간으로 남도록 하는 것을 특징으로 하는 3차원 구조의 화합물 반도체 적층형 이미지센서용 포토다이오드 제조 방법.The interlayer dielectric layer 210 is etched diagonally to form a pyramid shape, so that the space between the interlayer dielectric layers 210 is left as an inverted pyramid-shaped space for a compound semiconductor stacked image sensor having a three-dimensional structure. Photodiode manufacturing method.
KR1020070013620A 2007-02-09 2007-02-09 3d structure laminated compound semiconductor solid-state image sensor and a method for manufacturing the same KR100819744B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070013620A KR100819744B1 (en) 2007-02-09 2007-02-09 3d structure laminated compound semiconductor solid-state image sensor and a method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070013620A KR100819744B1 (en) 2007-02-09 2007-02-09 3d structure laminated compound semiconductor solid-state image sensor and a method for manufacturing the same

Publications (1)

Publication Number Publication Date
KR100819744B1 true KR100819744B1 (en) 2008-04-08

Family

ID=39533874

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070013620A KR100819744B1 (en) 2007-02-09 2007-02-09 3d structure laminated compound semiconductor solid-state image sensor and a method for manufacturing the same

Country Status (1)

Country Link
KR (1) KR100819744B1 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050097156A (en) * 2004-03-31 2005-10-07 매그나칩 반도체 유한회사 Image sensor and method of manufacturing the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050097156A (en) * 2004-03-31 2005-10-07 매그나칩 반도체 유한회사 Image sensor and method of manufacturing the same

Similar Documents

Publication Publication Date Title
US7855407B2 (en) CMOS image sensor and method for manufacturing the same
KR102083402B1 (en) Image sensor and method of forming the same
US20160218138A1 (en) Solid-state image pickup device and method for manufacturing a solid-state image pickup device
KR20190062241A (en) Multiple deep trench isolation (mdti) structure for cmos image sensor
KR20140020713A (en) System and method for fabricating a 3d image sensor structure
TW201110338A (en) Imager with biased material and backside well
CN109411490B (en) Bump electrode for reducing dark current
US9466636B2 (en) Image sensors including well regions of different concentrations and methods of fabricating the same
JP2009071310A (en) Image sensor, and manufacturing method thereof
US20220216262A1 (en) High density image sensor
US20090173940A1 (en) Image Sensor and Method for Manufacturing the Same
US9741758B2 (en) Methods of forming image sensors including deposited negative fixed charge layers on photoelectric conversion regions
KR100806772B1 (en) Image Senor Pixel and Method of Forming the same
TWI556423B (en) Image sensor device and semiconductor structure
US20230197762A1 (en) Complementary metal-oxide-semiconductor image sensor and method of making
TWI679755B (en) Cmos image sensor for global shutter
KR20100078111A (en) Image sensor and method for manufacturing thereof
KR100819744B1 (en) 3d structure laminated compound semiconductor solid-state image sensor and a method for manufacturing the same
KR100819743B1 (en) 3d structure poly-crystal compound semiconductor solid-state image sensor and a method for manufacturing the same
KR20100078145A (en) Image sensor and method for manufacturing thereof
CN100499149C (en) CMOS image sensor and method for manufacturing the same
KR20110070075A (en) Image sensor and method for manufacturing thereof
KR20100025873A (en) Cmos image sensor having crosstalk preventive impurity isolation layer and method for manufacturing the same
KR20070000817A (en) Cmos image sensor, and method for fabricating the same
KR100880287B1 (en) Image sensor and method for manufacturing thereof

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee