KR100819046B1 - Apparatus and Method for Restoring multiple linked clock/data by compensating for non-linear characteristics - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and method for clock / data recovery for multiple links using a phase interpolator through a nonlinear compensation circuit. A phase detector for converting the phase comparison result into a phase synthesis control code, and converts the control code into a current value that is a result of a transfer function that is an inverse function for nonlinearity to compensate for the nonlinear characteristics of the phase interpolator. A nonlinear compensator and a phase interpolator for receiving a multi-phase clock, selecting two appropriate clocks, and outputting a reconstructed clock as a clock signal having a linear phase with respect to a control code. The present invention adds a nonlinear compensation circuit having a non-linear inverse form transfer function to improve linearity in the phase relationship of a clock signal that is an output of a phase combining circuit to a control code, thereby maintaining a uniform resolution of the reconstructed clock and providing jitter performance. Reduces the degradation.

Nonlinear Compensation Circuit, Phase Interpolator, Data / Clock Recovery

Description

Apparatus and Method for Restoring multiple linked clock / data by compensating for non-linear characteristics}

1 is a diagram of a clock / data recovery circuit using a phase interpolator of a conventional digital control method.

2 is a diagram of a clock / data recovery apparatus using a phase interpolator that compensates for nonlinear characteristics according to the present invention.

3 is a diagram of a clock / data recovery apparatus for multiple links using a phase interpolator including a nonlinear compensation circuit according to an embodiment of the present invention.

4 is a flowchart illustrating a clock / data recovery method using a phase interpolator that compensates for nonlinear characteristics according to the present invention.

5 is a flowchart illustrating a method of recovering clock / data for multiple links using a phase interpolator including a nonlinear compensation circuit according to a preferred embodiment of the present invention.

FIG. 6 is a diagram illustrating a phase relationship between control codes B and C which are outputs of the phase combining control circuit shown in FIG. 3 and a reconstructed clock of a phase interpolator. FIG.

FIG. 7 is a diagram showing the phase relationship between the phase selector control code B, which is the output of the phase selector control circuit shown in FIG. 3, and the reference clocks I and Q of the phase selector.

FIG. 8 is a diagram illustrating a phase relationship between a phase interpolator control code C, which is an output of the phase interpolator control circuit shown in FIG. 3, and a recovery clock RCLK of a phase interpolator.

FIG. 9 is a diagram illustrating a relationship between a relative incremental value of a current source weight W that is an output of the nonlinear compensation circuit of FIG. 3 and a current source of a phase interpolator.

The present invention relates to a multi-link clock / data recovery circuit using a phase interpolator, and more particularly, to a multi-link clock / data recovery circuit for improving linearity of a phase interpolator through a nonlinear compensation circuit.

Each input data signal input to the multi-link receiver has a frequency offset or a different phase due to a difference in length and characteristics of a transmission line, a difference in characteristics between transmitters, and the like. Due to this frequency offset and phase error problem, each clock / data recovery circuit mounted in a multi-link receiver must have an independent phase alignment function.

Conventional multi-link clock / data recovery circuits have multiple clock / data recovery circuits sharing one reference phase lock loop to provide independent phase alignment, and each clock / data recovery circuit has a reference phase lock loop. A multi-phase reference clock is input from the circuit and a phase interpolator is used to synthesize a clock signal synchronized with the input data.

The control method for synthesizing the clock signal can be largely divided into an analog control method and a digital control method. Analog control schemes generally have better jitter generation performance and do not account for jitter degradation due to switching noise, as the phase interpolators can synthesize the phases continuously over the entire range. There is no need for high speed operation (TH Lee, et al., IEEE Journal of Solid-State Circuits, Vol. 29, No. 12, 1994, pp. 1491-1496). On the other hand, the digital control method implements all control circuits through digital logic circuits, which makes librarying easier and the control signal is hardly affected by power supply noise. There are advantages (M. Fukaishi, et al., IEEE Journal of Solid-State Circuits, Vol. 35, No. 11, 2000, pp. 1611-1618).

A clock / data recovery circuit using a phase interpolator of a conventional digital control method will be described below.

1 is a diagram illustrating a clock / data recovery circuit using a phase interpolator of a conventional digital control method.

Referring to FIG. 1, it can be seen that the circuit is composed of three parts, a band-bang phase detector 101, a code controller 102, and a phase interpolator 103. The binary phase detector 101 compares the phase of the input data with the clock synthesized by the phase interpolator 103 and transmits a phase increase / decrease result to the code controller 102 in the form of a binary value.

The code control unit 102 is configured as an increase / decrease counter to increase the phase control code when the output of the binary phase detector is to increase the phase, and to decrease the phase control code to decrease the phase. The phase interpolator 103 synthesizes a recovery clock having a new phase proportional to the phase control code among the multi-phase clocks. Therefore, the phase of the reconstructed clock, which is the output of the phase interpolator 103, is synchronized with the input data phase after a predetermined tracking time.

However, the conventional digitally controlled clock / data recovery circuit using such a phase interpolator has the following problems.

If the two multi-phase reference clocks applied to the phase interpolator 103 have a phase difference of 90 degrees from each other, this can be represented by a sin function and a cos function, respectively, and the phase of the synthesized signal is given by Equation (1). Determined by the relationship.

<Equation 1>

At this time, the generated phase θ has the same relationship as α and β, and the inverse function is represented by Equation 3 below.

<Equation 2>

<Equation 3>

For linear phase control, suppose that the relationship between θ and β is equal to Equation 4, and then substitute Equation 4 into Equation 3 to obtain the same result as Equation 5.

 <Equation 4>

<Equation 5>

If the tangent function of Equation 5 is approximated as a fraction of β, the same result as Equation 6 can be obtained. The final relationship between α and β for linear phase control is shown in Equation 7.

 <Equation 6>

<Equation 7>

However, since the above result is an approximation process, when a control code α and β having a relationship as shown in Equation 7 are used, a clock signal having a linear phase cannot be obtained from a phase interpolator. Due to the nonlinearity of the phase interpolator, the phase resolution of the clock synthesized by the phase interpolator is large and small compared to the average value, resulting in nonuniformity. Therefore, there is a problem that jitter performance is relatively lowered in a section in which the resolution of the phase is smaller than the average value.

In order to solve the above-mentioned problems, the present invention provides a digital control for controlling the phase transfer characteristics of a nonlinear phase interpolator generated in a linear control so as to have an inverse function for its nonlinearity according to the use of a nonlinear compensation circuit. To provide a multi-link clock / data recovery apparatus and method having a linearity by compensating in a manner.

In an embodiment of the present invention, a data / clock restoration apparatus for a multi-link data / clock restoration apparatus using a phase interpolator that compensates for nonlinear characteristics may be configured to adjust the phase of the input data and the phase of the restoration clock. A phase detection unit for comparing the phase difference control unit to generate a phase synthesis control code mapped to the reconstruction clock and the phase difference, and a compensation function that is an inverse function of a nonlinear function that takes the phase synthesis control code as an argument A non-linear compensator for generating a current source weight value and two reference clocks among the multi-phase reference clocks according to the current source weight value, and synthesizing the selected two reference clocks to generate a new recovery clock having a linear phase; It comprises a phase interpolation part which outputs to a phase detection part.

In yet another embodiment of the present invention, a data / clock restoration apparatus for a multi-link data / clock restoration apparatus using a phase interpolator for compensating for nonlinear characteristics may include a phase and restoration of binary input data. A phase detector for calculating a phase difference by comparing phases of clocks, a phase selection signal synchronized to the reconstruction clock, and a phase difference based on the phase difference for selecting two or more reference clocks having a phase difference of 90 degrees among multiple reference phase clocks; A phase interpolator control circuit for generating a first control code determined through a counter, and a phase selector for generating a second control code according to a correlation with the phase selection signal specifying two reference clocks from the two or more reference clocks A control circuit, a nonlinear compensation function in the form of an inverse of the nonlinear function taking the first control code as an argument. A non-linear compensation circuit for generating a current source weight value using a second selector, a phase selector for directly selecting the two reference clocks having a phase difference of 90 degrees in the multiple reference phase clocks by the second control code, and synthesizing the selected two reference clocks And a phase interpolator for generating a new recovery clock having a linear phase reflecting the current source weight value and outputting it to the phase detector.

According to an embodiment of the present invention, a data / clock restoration method using a phase interpolator for compensating for nonlinear characteristics may be performed by adjusting a phase of an input data and a phase of a recovery clock. Calculating a phase difference by comparing, generating a phase synthesis control code mapped according to the reconstruction clock and the phase difference, and using a compensation function that is an inverse function of a nonlinear function that takes the phase synthesis control code as an argument. Generating a new reconstructed clock having a linear phase by selecting two reference clocks among the multi-phase reference clocks according to the current source weight value and synthesizing the selected two reference clocks.

In another embodiment of the present invention, a data / clock restoration method using a phase interpolator through compensation of a nonlinear characteristic may include a phase of binary input data. Calculating a phase difference by comparing phases of a recovery clock, and adding or subtracting the phase difference signal based on a phase selection signal synchronized to the recovery clock according to the phase difference of selecting two or more reference clocks having a phase difference of 90 degrees among multiple reference phase clocks; Generating a first control code determined through a counter, generating a second control code in accordance with an association with the phase selection signal specifying two reference clocks from the two or more reference clocks, the first Generate current source weight value using nonlinear compensation function, which is the inverse of nonlinear function with control code as argument Directly selecting the two reference clocks having a phase difference of 90 degrees by the second control code, and synthesizing the selected two reference clocks to obtain a linear phase reflecting the current source weight value. The branch is configured to include generating a new recovery clock.

Hereinafter, with reference to the accompanying drawings will be described in detail with respect to a preferred embodiment according to the present invention.

2 is a diagram illustrating a clock / data recovery apparatus using a phase interpolator that compensates for nonlinear characteristics according to the present invention.

Referring to FIG. 2, the binary input data and the clock signal are input to compare the phase of the data and the clock signal to output the phase comparison result signals UP and DN and the re-timed reconstruction data RDATA to the input clock signal. A phase synthesis controller 202 for receiving a phase comparison result signal UP and DOWN and a clock signal output from the phase detector 201 and the phase detector 201, and outputting a phase synthesis control code PIC; Nonlinear compensator 203 which receives the phase synthesis control code PIC, which is the output of synthesis control means 202, and has an inverse function transfer function for nonlinearity and outputs a result value W to compensate for nonlinear characteristics And receiving a result value W, which is an output of the multi-phase clock and the nonlinear compensator 203, selecting two appropriate clocks among the multi-phase clocks, and linearly between the two clocks according to the input result value W. With phase And a group phase detector 201, phase interpolator 204, which outputs a clock signal with a recovered clock (RCLK) input to a component.

FIG. 3 is a diagram illustrating a clock / data recovery apparatus for multiple links using a phase interpolator including a nonlinear compensation circuit according to a preferred embodiment of the present invention.

Referring to FIG. 3, the phase detector 301 is an Alexander's Phase Detector, which is a type of a general binary phase detector that receives input data and a clock signal and outputs a phase difference between the two signals as a binary value. The phase synthesis control circuit 310 receives a phase comparison result signal UP and DN, which are outputs of the phase detector, and selects a phase synchronized with a recovery clock RCLK for selecting two adjacent clocks among the multi-phase clocks. A phase interpolator control circuit 312 which outputs the signals M_UP and M_DN and a C code (first control code) which is a part of the phase synthesis control code, and phase selection signals M_UP and M_DN which are outputs of the phase interpolator control circuit. And a phase selector control circuit 311 that outputs a B code (second control code) that is a part of the phase combining control code. The nonlinear compensation circuit 330 receives a C code, which is an output of the phase interpolator control circuit, and outputs a current value W having the inverse function form of the nonlinear function as a transfer function.

The phase synthesis circuit 320 receives a multi-phase clock and B code, which is an output of the phase selector control circuit 311, and selects two clock signals I and Q having a phase closest to the phase of the input data. A phase selector 321, two clock signals I and Q which are outputs of the phase selector, and a current value W which is an output of the nonlinear compensation circuit are input, and two clock signals I and Q according to the current values. And a phase interpolator 322 that outputs a reconstruction clock RCLK of a new phase having a linear phase relationship by giving a weight in the phase difference.

Hereinafter, the present invention will be described in detail through an embodiment of the case where the number N of the multi-phase clock is 4 and the number (resolution) M of the maximum interpolation phase of the phase interpolator is 16. FIG.

The phase detector 300 compares the phase of the recovery clock RCLK and the input binary data and outputs a phase comparison result to two outputs, UP and DN. If the phase of the clock signal is behind the phase of the input data, UP is outputted as '1'. If the phase of the clock signal is advanced compared to the phase of the input data, DN is outputted as '1'. If the same bit value is continuously applied to data and there is no data transition, both outputs are output as '0'.

The phase synthesis control circuit 320 includes a phase interpolator control circuit 322 and a phase selector control circuit 321. The phase synthesis control circuit receives two outputs UP and DN applied from a phase detector, and adds 1 to the output code C when the UP output of the phase detector is '1', and outputs the output code when the DN output is '1'. It is a kind of up / down counter that subtracts 1 from (C). The phase synthesis control circuit is composed of a phase selector control circuit and a phase interpolator control circuit as described above.

The nonlinear compensation circuit 330 receives the phase interpolator control code C, which is the output of the phase interpolator control circuit, and outputs a current source weight W such that the phase of the output clock of the phase interpolator is linearly proportional to the control code. do.

The current source weight W that is the output of the nonlinear compensation circuit 330 is determined as follows. Equation (5) below assumes phase control through the compensation functions f (α) and f (β) to compensate for nonlinearity while maintaining a complementary relationship between α and β as in Equation 7 above. It can be expressed as Equation (8).

<Equation 8>

For convenience, assuming that f (α) and f (β) are also complementary, Equation 8 is transformed as shown in Equation 9, so f (α) and f (β) are as shown in Equations 10 and 11, respectively. It can be seen.

<Equation 9>

<Equation 10>

<Equation 11>

Therefore, each current source that determines the coefficients of the two input signals in the phase interpolator 330 should receive linear control codes α and β to supply currents of the same type as the characteristics of f (α) and f (β). . Thus, assuming that the current sources of the control codes α and β and the phase interpolator are controlled by the N-bit temperature coefficient code, the current sources of the phase interpolator at each bit are proportional to (α) and (11) in order to be proportional to α or β. It has a size that corresponds to the increment that can be obtained by differentiating. The nonlinear compensation circuit outputs the magnitude of the above-described increment as the current source weight (W).

4 is a flowchart illustrating a clock / data recovery method using a phase interpolator that compensates for nonlinear characteristics according to the present invention.

Referring to FIG. 4, when a phase difference between input data and a recovery clock is calculated (401) and output, a phase synthesis control code is generated according to the phase difference by receiving the recovery clock and the phase difference (402). Then, a current source weight value for linearity is generated by using a compensation function, which is an inverse function of a nonlinear function, using the phase synthesis control code as an argument (403). Based on this value, two reference clocks are selected from a multi-phase reference clock and synthesized. A recovery clock of linear phase is generated (404).

5 is a flowchart illustrating a method of recovering clock / data for multiple links using a phase interpolator including a nonlinear compensation circuit according to a preferred embodiment of the present invention.

Referring to FIG. 5, first, a phase difference between binary input data and an input recovery clock is calculated (501). Then, a phase selection signal synchronized with the reconstruction clock to be used when selecting two or more reference clocks from the multi-phase reference clock as a value mapped according to the phase difference, and together with the first control code C according to the phase difference value Code 502). The second control code (B code) is generated based on the correlation between the phase selection signal (503) and the two reference clocks are subsequently selected (504). On the other hand, the first control code is used as an argument to the compensation function, which is the inverse of the nonlinear function, to generate a current source weight value for ensuring linearity of a newly generated recovery clock (505). The two selected last reference clocks are synthesized based on the weight value to generate a new recovery clock having a linear phase (506).

FIG. 6 is a diagram illustrating a phase relationship between control codes B and C, which are outputs of the phase combining control circuit shown in FIG. 3, and a reconstruction clock of a phase interpolator.

According to the relationship between the code of the control codes (B, C), which are outputs of the phase synthesis control circuit, and the phase of the clock signal, which is the output of the phase interpolator, the phase interpolator control code (C) is a phase selector control code (B). In the case of 00 'or' 11 ', the B code is increased from 0 to 14 by the UP signal, which is the output of the phase detector, and decreased by the DN signal. On the other hand, when the control code B of the phase selector control circuit is '01' or '10', the code is reduced from 15 to 1 by the UP signal and increased by the DN signal.

FIG. 7 is a diagram showing the phase relationship between the phase selector control code B, which is the output of the phase selector control circuit shown in FIG. 3, and the reference clocks I and Q of the phase selector.

According to the phase relationship between the phase selector control code (B), which is the output of the phase selector control circuit, and the output clocks (I, Q) of the phase selector, two clocks having adjacent phases are selected from the multiple phase clocks input to the phase selector. The number of cases that can be generated and generated is all four, and the number of these four cases is selected by the control code B, which is the output of the phase selector control circuit, and the two selected clocks are referred to as clock I and clock Q, respectively. .

FIG. 8 is a diagram illustrating a phase relationship between a phase interpolator control code C, which is an output of the phase interpolator control circuit shown in FIG. 3, and a recovery clock RCLK of a phase interpolator.

만큼 떨어진 위상을 갖는 클럭을 출력한다.According to the phase relationship between the phase interpolator control code C, which is the output of the phase interpolator control circuit, and the output clock RCLK of the phase interpolator, the output selected by the phase selector as the phase interpolator control code C increases. A clock RCLK having a new phase having a phase value between the phase of in clock I and the phase of clock Q is output. For example, if the value of control code (C) is 1, the phase of the output clock of the phase interpolator is from clock I in phase between clock I and clock Q.

Output a clock with phases separated by

FIG. 9 is a diagram illustrating a relationship between a relative incremental value of a current source weight W that is an output of the nonlinear compensation circuit of FIG. 3 and a current source of a phase interpolator.

According to the relationship between the relative incremental value of the current source weight W which is the output of the nonlinear compensation circuit and the current source of the phase interpolator, the incremental value of the current source weight of the nonlinear compensation circuit is compensated linearly. For example, when the control code C is 4, the phase interpolator current source 3 operates, and compared to the case where the control code C is 3, the value of the phase interpolator current source is relatively 1.00 which is the current source weight W. It will have a normalized value.

The control code corresponding to the phase of the clock aligned with the input data is determined in the phase synthesis control circuit by the configuration of the circuits as described above, and the current source weights W corresponding to the control codes B and C are nonlinear compensation. As a result of the change by the circuit, a new recovery clock with a synchronized linear phase is generated, allowing for recovery of the input data and clock with improved jitter performance.

Claims (12)

A phase detector for comparing a phase of the input data with a phase of the recovery clock to calculate a phase difference; A phase synthesis controller configured to generate a phase synthesis control code mapped according to the reconstruction clock and the phase difference; A nonlinear compensator configured to generate a current source weight value using a compensation function that is an inverse function of the nonlinear function having the phase synthesis control code as an argument; And A phase interpolation unit for selecting two reference clocks among the multi-phase reference clocks according to the current source weight value, synthesizing the selected two reference clocks, generating a new reconstructed clock having a linear phase, and outputting them to the phase detector; Clock and data recovery apparatus for a multi-link using a phase interpolator to compensate for the non-linear characteristics comprising a. The phase of the new reconstruction clock of the phase interpolator is And a phase interpolator for compensating for the nonlinear characteristics, wherein the current value is linearly proportional to the phase synthesis control code. The method of claim 1, The current source weight value of the nonlinear compensator is Compensation for nonlinear characteristics, characterized in that by substituting a nonlinear function having the phase synthesis control code as a factor in the linear relational expression existing between the phase synthesis control codes to obtain the nonlinear function values, each value is differentiated. Clock and data recovery device for multiple links using interpolators. A phase detector for comparing the phase of the binary input data with the phase of the recovery clock to calculate a phase difference; A phase for generating a first control code determined through a phase selection signal synchronized with the reconstruction clock and the first and second counters based on the phase difference according to the phase difference, for selecting two or more reference clocks having a phase difference of 90 degrees among multiple reference phase clocks; Interpolator control circuit; A phase selector control circuit for generating a second control code in accordance with an association with the phase selection signal, which specifies two reference clocks from among the two or more reference clocks; A nonlinear compensation circuit for generating a current source weight value using a nonlinear compensation function that is an inverse function of the nonlinear function taking the first control code as an argument; A phase selector for directly selecting the two reference clocks whose phase difference in the multiple reference phase clock is 90 degrees by the second control code; And Compensating the non-linear characteristics, characterized in that it comprises a phase interpolator for synthesizing the selected two reference clocks to generate a new recovery clock having a linear phase reflecting the current source weight value, and outputs to the phase detector Clock and data recovery device for multiple links using phase interpolator. The method of claim 4, wherein The phase of the new reconstruction clock of the phase interpolator is And a phase interpolator for compensating for the nonlinear characteristics, wherein the current control is linearly proportional to the first control code by the current weight value. 5. The method of claim 4, wherein the current source weight value of the nonlinear compensation circuit is Compensating for the nonlinear characteristics by substituting a compensation function having the first control code as an argument into a linear relation existing between the first control codes to obtain the respective compensation functions, and then setting each of them as a derivative. Clock and data recovery device for multiple links using phase interpolator. Calculating a phase difference by comparing the phase of the input data with the phase of the recovery clock; Generating a phase synthesis control code mapped according to the reconstruction clock and a phase difference; Generating a current source weight value using a compensation function that is an inverse function of a nonlinear function taking the phase synthesis control code as an argument; And Selecting two reference clocks among the multi-phase reference clocks according to the current source weight value and synthesizing the selected two reference clocks to generate a new reconstruction clock having a linear phase; Clock and data recovery method for multilink using compensated phase interpolator. 8. The method of claim 7, wherein the current source weight value is Compensation for nonlinear characteristics, characterized in that by substituting a nonlinear function having the phase synthesis control code as a factor in the linear relational expression existing between the phase synthesis control codes to obtain the nonlinear function values, each value is differentiated. Clock and data recovery method for multilink using interpolator. Calculating a phase difference by comparing the phase of the binary input data with the phase of the recovery clock; Generating a first control code determined by selecting an at least two reference clocks having a phase difference of 90 degrees from among multiple reference phase clocks, a phase selection signal synchronized to the reconstruction clock, and a first control code based on the phase difference based on the phase difference; ; Generating a second control code in accordance with an association with the phase selection signal specifying two reference clocks from among the two or more reference clocks; Generating a current source weight value using a nonlinear compensation function that is an inverse function of the nonlinear function taking the first control code as an argument; Directly selecting, by the second control code, the two reference clocks whose phase difference in the multiple reference phase clock is 90 degrees; And Synthesizing the two selected reference clocks to generate a new reconstructed clock having a linear phase reflecting the current source weight value; multi-clock clock and data using a phase interpolator for compensating for nonlinear characteristics Restore method. 10. The method of claim 9, wherein the current source weight value is Compensating the nonlinear characteristic by substituting a compensation function having the first control code as an argument into a linear relational expression existing between the first control codes to obtain the respective compensation functions, and then setting each of them as derivative values. A method for clock and data recovery for multiple links using a phase interpolator. 10. The method of claim 9, wherein the new recovery clock is A clock and data recovery method for a multi-link using a phase interpolator for compensating for nonlinear characteristics, characterized in that the clock is synthesized by adding the two selected clocks having a 90 degree phase difference by adding the current source weight value to each coefficient. 12. A computer-readable recording medium recorded with a program for executing a multi-clock clock and data recovery method using a phase interpolator that compensates for the nonlinear characteristics according to any one of claims 7 to 11.

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