KR100815343B1 - Manufacture method of Diffractive thin-film piezoelectric micro-mirror and Manufacturing method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diffractive micromirror and a method of manufacturing the same. Particularly, a diffractive micromirror and a method of manufacturing the diffractive micromirror can be precisely formed to a desired degree in depth and width of a recess of the diffractive micromirror by a piezoelectric driving method. It is about.

Thin film, piezoelectric, optical modulator, diffractive optical modulator, micro mirror, depression

Description

Diffractive thin-film piezoelectric micro-mirror and manufacturing method thereof

1 illustrates a prior art electrostatic grating light modulator.

2 is a diagram illustrating reflecting incident light in a state where the electrostatic grating light modulator of the prior art is not deformed.

3 shows a diffraction of incident light in a state in which a prior art grating light modulator is deformed by electrostatic force.

4A to 4J are process drawings of the recessed thin film piezoelectric micromirror according to the prior art.

5A to 5C are perspective views of a diffractive thin film piezoelectric micromirror according to an embodiment of the present invention.

6A-6F are side cross-sectional views of a process of manufacturing a diffractive thin film piezoelectric micromirror having depressions according to a first embodiment of the present invention;

7A to 7G are side cross-sectional views of a manufacturing process of a diffractive thin film piezoelectric micromirror having depressions according to a second embodiment of the present invention;                 

8A to 8H are side cross-sectional views of a manufacturing process of a diffractive thin film piezoelectric micromirror having depressions according to a third embodiment of the present invention;

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diffractive micromirror and a method of manufacturing the same. Particularly, a diffractive micromirror and a method of manufacturing the diffractive micromirror can be precisely formed to a desired degree in depth and width of a recess of the diffractive micromirror by a piezoelectric driving method. It is about.

In general, optical signal processing has advantages of high speed, parallel processing capability, and large-capacity information processing, unlike conventional digital information processing, which cannot process a large amount of data and real-time processing, and design a binary phase filter using spatial light modulation theory. Research on fabrication, optical logic gates, optical amplifiers, image processing techniques, optical devices, optical modulators, etc.

The dual spatial optical modulator is used in the fields of optical memory, optical display, printer, optical interconnection, hologram, and the like, and research on the development of a display device using the same is underway.

Such a spatial light modulator is, for example, a reflective deformable grating light modulator 10 as shown in FIG. 1. Such a modulator 10 is disclosed in US Pat. No. 5,311,360 to Bloom et al. The modulator 10 includes a plurality of regularly spaced deformable reflective ribbons 18 having reflective surface portions and suspended above the substrate 16. An insulating layer 11 is deposited on the silicon substrate 16. Next, deposition of the silicon dioxide film 12 and the low stress silicon nitride film 14 is followed.

The silicon nitride film 14 is patterned from the ribbon 18 and a portion of the silicon dioxide film 12 is etched so that the ribbon 18 is retained on the silicon dioxide film 12 by the nitride frame 20.

In order to modulate light having a single wavelength λ _0, the modulator is designed thick with a thickness of the silicon dioxide film 12 of the ribbon 18 so that the λ _0/4.

The lattice amplitude of this modulator 10 defined by the vertical distance d between the top reflective surface 22 on the ribbon 18 and the reflective surface of the substrate 16 is the ribbon 16 (the ribbon 16 serving as the first electrode). Is controlled by applying a voltage between the reflective surface 22 of the < RTI ID = 0.0 >) and the substrate 16 (the conductive film 24 < / RTI >

In the undeformed condition, that is, while no voltage is not applied, the grating amplitude is λ ₀ / equal to 2, the car full path between reflected from the ribbons and the substrate the light like a λ _0, the reinforcing phase such reflected light Let's do it.

Thus, in the undeformed state, the modulator 10 reflects light as a planar mirror. The undeformed state is indicated as 20 in FIG. 2 showing incident light and reflected light.                         

When a proper voltage is applied between the ribbon 18 and the substrate 16, electrostatic forces deform the ribbon 18 in the down position toward the surface of the substrate 16. In the down position, the grating amplitude is changed like the λ _0/4. The total path difference is half of the wavelength, and the light reflected from the modified ribbon 18 and the light reflected from the substrate 16 have a destructive interference.

As a result of this interference, the modulator diffracts incident light 26. The modified state is represented by 28 and 30 in FIG. 3, showing light diffracted in the +/- diffraction modes (D + 1, D-1).

However, BLUM's optical modulator uses an electrostatic method to control the position of the micromirror, in which case the operating voltage is relatively high (usually around 30V) and the relationship between applied voltage and displacement is not linear. There is a disadvantage that the reliability is not high in controlling the light.

In order to solve this problem, Korean Patent Application No. P2003-077389 discloses a "thin film piezoelectric optical modulator and its manufacturing method."

The recessed thin film piezoelectric optical modulator according to the disclosed prior art includes a silicon substrate and a diffraction member.

Here, the diffraction member has a constant width and a plurality of constant alignment to form a recessed thin film piezoelectric optical modulator. In addition, these diffractive members have different widths and alternately arranged to form a recessed thin film piezoelectric optical modulator. In addition, the diffractive members may be spaced apart from each other at a predetermined interval (almost the same distance as the width of the diffractive member), and in this case, the micromirror layer formed on the entire upper surface of the silicon substrate reflects and diffracts incident light.

The silicon substrate has depressions to provide a space for the diffraction member, an insulating layer is deposited on the upper surface, and end portions of the diffraction members are attached to both sides of the depression.

The diffraction member has a rod shape, and the lower surfaces of both ends are attached to both side regions outside the depression of the silicon substrate so that the center portion is spaced apart from the depression of the silicon substrate, and the portions located at the depression of the silicon substrate are upper and lower sides. It includes a lower support movable to.

In addition, the diffraction member is stacked on the left end of the lower support, a lower electrode layer for providing a piezoelectric voltage, and a piezoelectric material layer laminated on the lower electrode layer and contracting and expanding when voltage is applied to both sides to generate a vertical driving force; It is laminated on the piezoelectric material layer and includes an upper electrode layer for providing a piezoelectric voltage to the piezoelectric material layer.

In addition, the diffraction member is stacked on the right end of the lower support, the lower electrode layer for providing a piezoelectric voltage, and the piezoelectric material layer laminated on the lower electrode layer and contracted and expanded when voltage is applied to both sides to generate a vertical driving force; And an upper electrode layer laminated on the piezoelectric material layer and providing a piezoelectric voltage to the piezoelectric material layer.

In addition, Korean Patent Application No. P2003-077389 describes the protruding type in addition to the depression type described above, and describes a manufacturing method.

4A to 4J are process diagrams of the recessed thin film piezoelectric micromirror according to the prior art.

Referring to FIG. 4A, in order to etch the silicon wafer 401, a mask layer 402 is formed to a thickness of 0.1 to 1.0 μm by a method of thermal oxidation, and patterned to prepare silicon etching.

Referring to FIG. 4B, the mask layer 402 is removed after etching silicon to an appropriate thickness using a solution capable of etching silicon such as TMAH or KOH.

Referring to FIG. 4C, the insulating and etch stop layer 403 is formed on the etched silicon by thermal oxidation. That is, an insulating and etching prevention layer 403 such as SiO ₂ is formed on the surface of the silicon wafer.

In addition, referring to FIG. 4D, poly-Si or amorphous is formed on the etched portion of the silicon wafer 401 by low pressure chemical vapor deposition (LPCVD) or plasma chemical vapor deposition (PECVD) to form a space. Silicon (amorphous-Si) or the like is deposited to form the sacrificial layer 404 and then polished flat. In this case, when using a SOI (Sillicon On Insulator) it can proceed without deposition and polishing of polysilicon.

Afterwards, a silicon nitride series such as Si ₃ N ₄ is deposited by LPCVD or PECVD, for example, preferably in the range of 0.1 to 5.0 μm thick, and then SiO ₂ is in the range of 0.1 to 5 μm by thermal oxidation or PECVD. It may be omitted as necessary to deposit.

Next, referring to FIG. 4E, a lower support 405 for supporting the piezoelectric material is deposited on the silicon wafer 401, and silicon oxide (for example, SiO _2, etc.) may be used as a material for forming the lower support 405. , Silicon nitride series (eg, Si ₃ N _4, etc.), ceramic substrates (Si, ZrO ₂ , Al ₂ O _3, etc.), silicon carbide, and the like. The lower support 405 can be omitted if necessary.

Referring to FIG. 4F, a lower electrode 406 is formed on the lower support 405, and as the electrode material of the lower electrode 406, Pt, Ta / Pt, Ni, Au, Al, RuO _2, or the like may be used. It is formed in a method such as sputtering or evaporation in the range of 0.01 ~ 3㎛.

Referring to FIG. 4G, the piezoelectric material 407 is wetted on the lower electrode 406 by wet (screen printing, sol-gel coating, etc.) and dry methods (sputtering, evaporation, vapor deposition, etc.). It is formed in the range of ˜20.0 μm. In addition, the piezoelectric material 407 to be used can use both upper and lower piezoelectric materials and left and right piezoelectric materials, and can use piezoelectric materials such as PzT, PNN-PT, ZnO, and other elements such as Pb, Zr, Zn, or titanium. It may further comprise a piezoelectric electrolytic material.

Referring to FIG. 4H, the upper electrode 408 is formed on the piezoelectric material 407. Pt, Ta / Pt, Ni, Au, Al, RuO _2, etc. may be used as the electrode material, and 0.01 to 3 may be used. It is formed by a method such as sputtering or evaporation in the micrometer range.

Referring to FIG. 4I, a micromirror 409 is attached to the upper electrode 408, and the material includes light reflection materials such as Ti, Cr, Cu, Ni, Al, Au, Ag, Pt, Au / Cr, and the like. Used.

In this case, the upper electrode layer 408 may be used as a micro mirror or a separate micro mirror may be deposited on the upper electrode layer 408.

Referring to FIG. 4J, in order to form the diffractive thin film piezoelectric micromirror array from the matrix of the diffractive thin film piezoelectric micromirror array formed as described above, the micromirror 409 after patterning using a mask layer such as a photo resist. The upper electrode 408, the piezoelectric material 407, the lower electrode 406, and the lower support 405 are etched to form a diffractive thin film piezoelectric micromirror array. Thereafter, the sacrificial layer 404 is etched using XeF ₂ gas.

Here, the process of removing the sacrificial layer 404 after forming the diffractive thin film piezoelectric micromirror array from the mother of the diffractive thin film piezoelectric micromirror array has been described, but the micromirror array is removed after the sacrificial layer 404 is removed. It may be formed.

That is, first, holes are formed in a region where the lower supporter 405 is not formed in the matrix of the diffractive thin film piezoelectric micromirror array, and the sacrificial layer 404 is etched using XeF ₂ gas, and then the diffractive thin film piezoelectric micromirror After patterning using a mask layer such as a photo resist in the matrix of the array, the micromirror 409, the upper electrode 408, the piezoelectric material 407, the lower electrode 406, and the lower support 405 are etched to form a micro Form a mirror array.

On the other hand, the diffractive thin film piezoelectric optical modulator according to the prior art has a problem that it is difficult to control the thickness when polishing the polysilicon. That is, there is a problem that the spread of the setting time is large for each ribbon in the chip.

In addition, the diffractive thin film piezoelectric optical modulator according to the prior art has a problem that the depth of the separation space is ± 0.5 μm, and thus the separation space depth cannot be 0.5 μm or less.

Accordingly, the present invention has been made to solve the above problems, forming a protective layer that can define the width and depth of the separation space, the diffraction type micro to allow processing the width and depth of the separation space to the desired degree A mirror and a method of manufacturing the same.

The present invention for achieving the above object, the silicon substrate is formed in the central portion in the groove in the longitudinal direction of the both side walls perpendicular to the bottom surface; A lower protective layer which prevents etching of the lower layer during the manufacturing process with an oxide layer formed at a predetermined depth on the bottom surface of the groove of the silicon substrate; A pair of sidewall protection layers formed of a high concentration ion implantation layer formed at a predetermined depth on the sidewalls of the grooves of the silicon substrate to prevent external etching during the manufacturing process; And a ribbon shape, and lower surfaces of both ends are attached to both side regions away from the grooves of the silicon substrate so that the center portion is spaced apart from the grooves of the silicon substrate, and spaced apart from the grooves when a voltage is applied. It is driven up and down, and characterized in that it comprises a piezoelectric mirror layer for diffracting the incident beam.

In addition, the present invention is a silicon substrate in which grooves in which both side walls are perpendicular to the bottom surface are formed in the central portion in the longitudinal direction; A lower protective layer which prevents etching of the lower layer during the manufacturing process with an oxide layer formed at a predetermined depth on the bottom surface of the groove of the silicon substrate; A pair of sidewall protection layers formed of a high concentration ion implantation layer formed at a predetermined depth on the sidewalls of the grooves of the silicon substrate to prevent external etching during the manufacturing process; The bottom surface of each end is attached to both side regions outside the groove of the silicon substrate so that the center portion is spaced apart from the groove of the silicon substrate, and the center portion is spaced apart from the groove of the silicon substrate. A movable lower support; And a piezoelectric mirror layer formed on the lower support such that both ends thereof are positioned on the groove of the silicon substrate, and when a voltage is applied, a portion spaced apart from the groove is driven up and down and diffracts an incident beam. It features.

In addition, the present invention is a silicon substrate in which grooves in which both side walls are perpendicular to the bottom surface are formed in the central portion in the longitudinal direction; A lower protective layer which prevents etching of the lower layer during the manufacturing process with an oxide layer formed at a predetermined depth on the bottom surface of the groove of the silicon substrate; A pair of sidewall protection layers formed of a high concentration ion implantation layer formed at a predetermined depth on the sidewalls of the grooves of the silicon substrate to prevent external etching during the manufacturing process; A lower supporter having a ribbon shape, and having lower surfaces at both ends thereof attached to both sides of the silicon substrate so as to be spaced apart from the groove of the silicon substrate; One end is located at the left end of the lower support, the other end is located a predetermined distance spaced to the left from the central portion of the lower support, the first piezoelectric to provide a vertical driving force by contraction and expansion when voltage is applied layer; One end is located at the right end of the lower support, the other end is located a predetermined distance spaced to the right from the center of the lower support, the second piezoelectric layer that provides a vertical driving force by contraction and expansion when voltage is applied ; And positioned in the center portion of the lower support, characterized in that it comprises a micro mirror layer for diffracting the incident beam.

In addition, the present invention, the first step of forming a lower protective layer by forming an oxide layer from a predetermined depth to a predetermined depth inside the silicon substrate; Stacking a mask on the silicon substrate and forming a pair of sidewall protective layers spaced apart from each other in a predetermined width from the surface to the lower protective layer by high concentration ion implantation; Forming a piezoelectric layer on the silicon substrate and patterning the piezoelectric layer to fabricate a diffraction thin film piezoelectric micromirror array; And removing a silicon substrate region surrounded by the lower protective layer and the sidewall protective layer to form a diffractive thin film piezoelectric micromirror array.

In addition, the present invention, the first step of forming a lower protective layer by forming an oxide layer from a predetermined depth to a predetermined depth inside the silicon substrate; A second step of forming a pair of sidewall protective layers spaced apart from each other in a predetermined width from the surface to the lower protective layer by implanting high concentration ions after laminating a mask on the silicon substrate; Forming a piezoelectric layer on the silicon substrate, and removing the sacrificial layer on the lower protective layer; And a fourth step of manufacturing the diffractive thin film piezoelectric micromirror array by patterning the piezoelectric layer.

Now, a preferred embodiment of the present invention will be described in detail with reference to the drawings of FIG. 5A.

5A is a perspective view of a diffractive micromirror according to an embodiment of the present invention. The diffractive micromirror according to an embodiment of the present invention may include a silicon substrate 601, a lower protective layer 602, and a pair of sidewall protections. The layer 604, the lower support 605a, and the piezoelectric layer 610a.

The lower passivation layer 602 is an insulating layer formed at a depth desired to form a space spaced from the surface by ion implantation or the like during manufacturing, so that the silicon substrate 601 disposed below is not etched during manufacturing.

The pair of sidewall protection layers 604 are formed to be perpendicular to the lower protection layer 602, and doped with B, Al, Ga, etc., at a high concentration of 10 ¹⁸ to 10 ²¹ pieces / cm ³ from the surface during manufacture. It is formed to prevent the silicon substrate 601 located on each outer side to be etched during the manufacturing process.

Meanwhile, the area surrounded by the lower protective layer 602 and the pair of sidewall protective layers 604 is removed by etching in the manufacturing process to form the space 620, and the piezoelectric layer stacked on the silicon substrate 601. A moving space of 610a is provided.

The lower support 605a is formed to float in the space 620 on the surface of the silicon substrate 601, and serves to support the piezoelectric layer 610a to be stacked.

The piezoelectric layer 610a is stacked on the lower support 605a and includes a lower electrode layer 611a, a piezoelectric material layer 612a, an upper electrode layer 613a, and a mirror 614a.

When the piezoelectric material layer 612a is provided with a piezoelectric voltage to the lower electrode layer 611a and the upper electrode layer 613a, the piezoelectric material layer 612a contracts or expands from side to side to generate a vertical driving force, and thus the mirror 614a moves up and down. .

As a result, the mirror 614a generates diffracted light by forming a step of a multiple of λ / 4 when the wavelength of the incident light and the mirror in the adjacent piezoelectric layer 610b is λ. That is, mirrors in the plurality of piezoelectric layers 610a to 610n gather to form a diffraction type optical modulator.

5B is a perspective view of a diffractive micromirror according to a second embodiment of the present invention, wherein the diffractive micromirror according to the second embodiment of the present invention includes a silicon substrate 701, a lower protective layer 702, and a pair of The side wall protection layer 704, the lower support 705a, and the piezoelectric layer 710a are comprised. The diffractive micromirror according to the second embodiment of the present invention differs from the first embodiment in that both ends of the piezoelectric layer 710a are positioned on the separation space 720.

5C is a perspective view of a diffractive micromirror according to a third embodiment of the present invention, wherein the diffractive micromirror according to the third embodiment of the present invention includes a silicon substrate 801, a lower protective layer 802, and a pair of It is comprised by the side wall protection layer 804, the lower support part 805a, a pair of piezoelectric layers 810a and 810a ', and the mirror 830a. The third embodiment of the present invention differs from the first and second embodiments in that the piezoelectric layers 810a and 810a 'are located at both sides of the lower support 805a, and in the center of the lower support 805a. The mirror 830a is located.

The lower protective layer 802 is an insulating layer formed at a depth desired to form the space 820 from the surface by ion implantation or the like during manufacturing, so that the silicon substrate 801 located below is not etched during manufacturing. .

The pair of sidewall protection layers 804 are formed to be perpendicular to the lower protection layer 802, and doped with B, Al, Ga, etc., at a high concentration of 10 ¹⁸ to 10 ²¹ pieces / cm ³ from the surface during manufacture. The silicon substrate 801, which is formed and located outside of each other, is prevented from being etched in the manufacturing process.

Meanwhile, the area surrounded by the lower protective layer 802 and the pair of sidewall protective layers 804 is removed by etching during the manufacturing process to form the space 820, and the lower support layer stacked on the silicon substrate 801. Provide a moving space in the center portion of 805a.

The lower support 805a is formed to float in the spaced space 820 of the silicon substrate 801, and serves to support a pair of stacked piezoelectric layers 810a and 810a ', and has a mirror 830a at the center portion. ) Is formed.

A pair of piezoelectric layers 810a and 810a 'are stacked on the lower support 805a, one end of which is positioned on the separation space 820, and the other end of which is located on the silicon substrate 801, and the lower electrode layers 811a and 811a, respectively. '), Piezoelectric material layers 812a and 812a', and upper electrode layers 813a and 813a '.

Here, the piezoelectric material layers 812a and 812a 'are contracted or expanded left and right when the piezoelectric voltages are provided to the lower electrode layers 811a and 811a' and the upper electrode layers 813a and 813a 'to generate vertical driving force. The mirror 830a moves up and down.

As a result, the mirror 830a generates diffracted light by forming a step of a multiple of λ / 4 when the wavelength of the incident light with the mirror in the center of the adjacent lower support is λ. That is, the mirrors in the plurality of lower supports gather to form a diffractive optical modulator.

6A to 6F are side cross-sectional views of a manufacturing process of a diffractive thin film piezoelectric micromirror having a depression according to a first embodiment of the present invention.

Referring to FIG. 6A, a silicon wafer 601 is prepared and a lower protective layer 602 is formed at a predetermined depth from a depth desired to form a space spaced from the surface by ion implantation or the like.

Next, referring to FIG. 6B, an ion exposure mask 603 having both boundary portions exposed is formed to form a sidewall protective layer 604 that defines both boundaries of the width of the separation space on the silicon wafer 601. Laminated.

When the ion exposure mask 603 is implanted with ions such as B, Al, and Ga, ions such as B, Al, and Ga are implanted only in the exposed portions, thereby forming a boundary of a desired space. A sidewall protective layer 604 formed via the via is shown in FIG. 6B.

Ion implantation is a technique of ionizing a material to be doped and then accelerating it to have a greatly increased kinetic energy and forcing it into the surface of the silicon wafer 601. As a result, doping in the horizontal direction is significantly reduced as compared to heat diffusion. Bring it directly brings benefits.

In general, ion implantation can be achieved by 1) precise control of implanted ion concentration, 2) miniaturization of devices with reduced horizontal distribution, 3) high-purity impurity implantation using mass spectrometers, and 4) diverse concentration distribution through overlapping ion implantation. 5) doping concentration uniformity, 6) low temperature process, photoresist film can be used as a mask, 7) impurities are reduced.

The ion implantation apparatus generally comprises an ion source, an accelerator, a mass spectrometer, a focusing lens, an x-y deflector, a wafer top chamber, and the like. The ion source is a source for obtaining the ions to be implanted, and the generated ions are accelerated by the electric field and after the mass spectrometer, only the ions to be implanted are separated and proceed. In order to scan the silicon wafer 601 uniformly, a deflecting device is required for scanning while deflecting ions, and there is a focusing lens that adjusts the width of the beam. There is a need for a silicon wafer mounting chamber, which is a target to be ion implanted, and a current measuring device capable of knowing the implanted ion dose by measuring the overall ion current.

The ion implantation apparatus is operated under vacuum in the range of 10 ⁻⁵ to 10 ⁻⁷ Torr. The ion implantation system is divided into a boost current ion implanter, a high current ion implanter, a line implantation ion implanter, and a high energy ion implanter according to the ion current and energy magnitude.

In this case, the ion concentration implanted to form the sidewall protective layer 604 is 10 ¹⁸ to 10 ²¹ atoms / cm ³ , and the doping of group III elements such as B, Al, and Ga, as shown above, increases the P-type ion concentration. When the layer is formed and the Group 5 element is used, an n-type high concentration ion implantation layer is formed.

Referring to FIG. 6C, when the ion implantation by the ion implantation apparatus is completed to form the desired sidewall protection layer 604 on the silicon wafer 601, the ion exposure mask 603 is removed.

6D, a lower support 605 for supporting the piezoelectric material is deposited on the silicon wafer 601. In this case, a material constituting the lower support 605 is silicon oxide (for example, SiO _2, etc.). ), Silicon nitride series (eg, Si ₃ N _4, etc.), ceramic substrates (Si, ZrO ₂ , Al ₂ O _3, etc.), silicon carbide, and the like. The lower support 605 can be omitted as necessary.

In addition, referring to FIG. 6D, the piezoelectric layer 610 is deposited on the lower support 605. First, a lower electrode 611 constituting the piezoelectric layer 610 is formed, and at this time, an electrode of the lower electrode 611 is formed. The material may be Pt, Ta / Pt, Ni, Au, Al, RuO ₂ and the like, and is formed by a method such as sputtering or evaporation in the range of 0.01-3 μm.

6D, the piezoelectric material 612 is wetted on the lower electrode 611 (screen printing, sol-gel coating, etc.) and a dry method (sputtering, evaporation, vapor deposition, etc.). It forms in 0.01-20.0 micrometers. In addition, the piezoelectric material 612 to be used may use both upper and lower piezoelectric materials and left and right piezoelectric materials, and may use piezoelectric materials such as PzT, PNN-PT, and ZnO, and may include Pb, Zr, Zn, or titanium. Piezoelectric electrolytic material.

6D, the upper electrode 613 is formed on the piezoelectric material 612. Pt, Ta / Pt, Ni, Au, Al, RuO _2, etc. may be used as the electrode material, and 0.01 may be used. It is formed by a method such as sputtering or evaporation in the range of ˜3 μm.

Next, referring to FIG. 6D, the micromirror 614 is attached on the upper electrode 613, and the materials include Ti, Cr, Cu, Ni, Al, Au, Ag, Pt, Au / Cr, and the like. Reflective materials are used.

In this case, the upper electrode layer 613 may be used as a micro mirror or a separate micro mirror 614 may be deposited on the upper electrode layer 613.

Referring to FIG. 6E, in order to form the diffractive thin film piezoelectric micromirror array from the matrix of the diffractive thin film piezoelectric micromirror array formed as described above, the micromirror 614 is patterned using a mask layer such as a photo resist. The upper electrode 613, the piezoelectric material 612, the lower electrode 611, and the lower support 605 are etched to form a diffractive thin film piezoelectric micromirror array.

Referring to FIG. 6F, the sacrificial layer 620 is subsequently etched, and as a result, a space is formed in a portion where the sacrificial layer 620 is etched to enable vertical driving of the diffractive thin film piezoelectric micromirror.

Here, the process of removing the sacrificial layer 620 after forming the diffractive thin film piezoelectric micromirror array from the mother of the diffractive thin film piezoelectric micromirror array has been described, but the micromirror array is removed after the sacrificial layer 620 is removed. It may be formed.

That is, first, after the sacrificial layer 620 is etched in the matrix of the diffractive thin film piezoelectric micromirror array, the micromirror 614 is patterned using a mask layer such as a photo resist in the matrix of the diffractive thin film piezoelectric micromirror array. The upper electrode 613, the piezoelectric material 612, the lower electrode 611, and the lower support 605 are etched to form a micro mirror array.

7A to 7G are side cross-sectional views of a manufacturing process of a diffractive thin film piezoelectric micromirror having a depression according to a second embodiment of the present invention. The method of manufacturing the diffractive thin film piezoelectric micromirror having the recessed portion according to the second embodiment of the present invention of FIGS. 7A to 7G differs from the manufacturing method of FIGS. 6A to 6F. Is located above the space. Therefore, in order to fabricate the diffractive thin film piezoelectric micromirror having such a structure, it is necessary to etch and remove the piezoelectric layer 710 located at a portion away from the space before removing the sacrificial layer 720.

Referring to FIG. 7A, a silicon wafer 701 is prepared, and a lower protective layer 702 is formed at a predetermined depth from a depth desired to form a space spaced from a surface by ion implantation.

Next, referring to FIG. 7B, an ion exposure mask 703 in which both boundary portions are exposed is stacked on the silicon wafer 701 in order to form sidewall protection layers defining both sides of the width of the separation space.

When the ion exposure mask 703 is implanted with ions such as B, Al, and Ga, ions may be implanted only in the exposed portions to form a boundary of a desired space, and the sidewall protective layer formed through the process ( 704 is shown in FIG. 7B. Here, to form the sidewall protective layer 704, Group 3 elements such as B, Al, and Ga are exemplified, but Group 5 elements are also possible. In the case of Group 3 elements, a p-type high concentration ion implantation layer is formed and is a Group 5 element. In this case, an n-type high concentration ion implantation layer is formed.

Referring to FIG. 7C, when the ion implantation by the ion implantation apparatus is completed to form the desired sidewall protection layer 704 on the silicon wafer 701, the ion exposure mask 703 is removed.

Referring to FIG. 7D, a lower support 705 for supporting the piezoelectric material is deposited on the silicon wafer 701, and a piezoelectric layer 710 is deposited on the lower support 705. A lower electrode 711 constituting the 710 is formed, a piezoelectric material 712 is formed on the lower electrode 711, an upper electrode 713 is formed on the piezoelectric material 712, and a microstructure is formed on the upper electrode 713. Attach the mirror 714.

Referring to FIG. 7E, in order to form the diffractive thin film piezoelectric micromirror array from the matrix of the diffractive thin film piezoelectric micromirror array formed as described above, after the patterning is performed using a mask layer such as a photo resist, the micromirror ( 714, the upper electrode 713, the piezoelectric material 712, the lower electrode 711, and the lower support 705 are etched to form a diffractive thin film piezoelectric micromirror array.

Referring to FIG. 7F, after that, except for the piezoelectric layer 710 existing on the spaced apart space, the piezoelectric layer 710 located at a portion away from the spaced space is removed so that the piezoelectric layer 710 is located only on the spaced space. do.

Referring to FIG. 7G, the sacrificial layer 720 is etched. As a result, a space is formed in a portion where the sacrificial layer 720 is etched to enable vertical driving of the diffractive thin film piezoelectric micromirror.

Here, the process of removing the sacrificial layer 720 after forming the diffractive thin film piezoelectric micromirror array from the mother of the diffractive thin film piezoelectric micromirror array has been described, but the micromirror array is removed after the sacrificial layer 720 is removed. It may be formed.

That is, first, the sacrificial layer 720 is etched in the matrix of the diffractive thin film piezoelectric micromirror array, and then patterned using a mask layer such as a photo resist in the matrix of the diffractive thin film piezoelectric micromirror array, followed by the micromirror 714. The upper electrode 713, the piezoelectric material 712, the lower electrode 711, and the lower support 705 are etched to form a micro mirror array.

8A to 8H are side cross-sectional views of a manufacturing process of a diffractive thin film piezoelectric micromirror having depressions according to a third embodiment of the present invention. The method of manufacturing the diffractive thin film piezoelectric micromirror having the recessed portion according to the third embodiment of the present invention of FIGS. 8A to 8H is different from that of the manufacturing method of FIGS. 6A to 6F. It is located left and right from the space. Therefore, in order to fabricate the diffractive thin film piezoelectric micromirror having such a structure, it is necessary to etch and remove the piezoelectric layer 810 located in the spaced portion before removing the sacrificial layer 820.

Referring to FIG. 8A, a silicon wafer 801 is prepared, and a lower protective layer 802 is formed at a predetermined depth from a depth desired to form a space spaced from a surface by ion implantation.

Next, referring to FIG. 8B, an ion exposure mask 803 having both boundary portions exposed is formed on the silicon wafer 801 to form sidewall protection layers 804 that define both boundaries of the width of the separation space. Laminated.

When the ion exposure mask 803 is implanted with ions such as B, Al, and Ga, ions may be implanted only in the exposed portions to form a boundary of a desired separation space, and the sidewall protective layer formed through this process ( 804 is shown in FIG. 8B.

Referring to FIG. 8C, when the ion implantation by the ion implantation apparatus is completed to form the desired sidewall protection layer 804 on the silicon wafer 801, the ion exposure mask 803 is removed.

8D, a lower support 805 for supporting the piezoelectric material is deposited on the silicon wafer 801, and a piezoelectric layer 810 is deposited on the lower support 805. A lower electrode 811 constituting 810 is formed, a piezoelectric material 812 is formed on the lower electrode 811, and an upper electrode 813 is formed on the piezoelectric material 812. In this case, it is not necessary to attach the micro mirror, because the piezoelectric layer 810 existing on the separation space is removed and the micro mirror 830 is formed on the lower support 805.

8E, in order to form the diffractive thin film piezoelectric micromirror array from the matrix of the diffractive thin film piezoelectric micromirror array formed as described above, the upper electrode after patterning using a mask layer such as a photo resist. 813, the piezoelectric material 812, the lower electrode 811, and the lower support 805 are etched to form a diffractive thin film piezoelectric micromirror array.

Referring to FIG. 8F, afterwards, the piezoelectric layer 810 existing on the separation space is removed so that the piezoelectric layer 810 is located on the left and right sides from the separation space.

Referring to FIG. 8G, the micro mirror 830 is stacked on the lower support 805 from which the piezoelectric layer 810 is removed, and the incident light is reflected. In this case, the micromirrors 830 are stacked only on the separation space, but may be stacked on the entire piezoelectric layer 810.

Referring to FIG. 8H, the sacrificial layer 820 is subsequently etched, and as a result, a space is formed in a portion where the sacrificial layer 820 is etched to enable vertical driving of the diffractive thin film piezoelectric micromirror.

Here, the process of removing the sacrificial layer 820 after forming the diffractive thin film piezoelectric micromirror array from the mother of the diffractive thin film piezoelectric micromirror array has been described, but after removing the sacrificial layer 820, the micromirror array is removed. It may be formed.

That is, first, the sacrificial layer 820 is etched in the matrix of the diffractive thin film piezoelectric micromirror array, and then the upper electrode 813 is patterned using a mask layer such as a photo resist in the matrix of the diffractive thin film piezoelectric micromirror array. The piezoelectric material 812, the lower electrode 811, and the lower support 805 are etched to form a micro mirror array.

According to the present invention as described above, it is effective to define the width of the separation space to a desired degree by forming the separation space using the ion implantation.

What has been described above is just one embodiment for carrying out the diffraction type thin film piezoelectric micromirror according to the present invention and a method for manufacturing the same, and the present invention is not limited to the above-described embodiment, and is claimed in the following claims. As will be apparent to those skilled in the art to which the present invention pertains without departing from the gist of the present invention, the technical spirit of the present invention may be changed to the extent that various modifications can be made.

Claims (20)

A silicon substrate having grooves vertically formed with respect to the bottom surface on both side walls of the central portion in the longitudinal direction; A lower protective layer which prevents etching of the lower layer during the manufacturing process with an oxide layer formed at a predetermined depth on the bottom surface of the groove of the silicon substrate; A pair of sidewall protection layers formed of a high concentration ion implantation layer formed at a predetermined depth on the sidewalls of the grooves of the silicon substrate to prevent external etching during the manufacturing process; And The bottom surface of each end is attached to both side regions away from the groove of the silicon substrate so that the center portion is spaced apart from the groove of the silicon substrate, and the portion spaced from the groove is applied when a voltage is applied. A diffractive thin film piezoelectric micromirror which is driven up and down and comprises a piezoelectric mirror layer for diffracting an incident beam. The method of claim 1, It has a ribbon shape, and the lower surfaces of both ends are attached to both side regions away from the grooves of the silicon substrate so that the center portion is spaced apart from the grooves of the silicon substrate, and the piezoelectric mirror layer is stacked on the top. The thin film piezoelectric micromirror further comprises a lower support for moving the up and down portion of the silicon substrate. The method of claim 1, And said sidewall protective layer is a p-type high concentration ion implantation layer formed by ion implantation of a group 3 element. The method of claim 1, And said sidewall protective layer is an n-type high concentration ion implantation layer formed by ion implantation of a Group 5 element. A silicon substrate having grooves vertically formed with respect to the bottom surface on both side walls of the central portion in the longitudinal direction; A lower protective layer which prevents etching of the lower layer during the manufacturing process with an oxide layer formed at a predetermined depth on the bottom surface of the groove of the silicon substrate; A pair of sidewall protection layers formed of a high concentration ion implantation layer formed at a predetermined depth on the sidewalls of the grooves of the silicon substrate to prevent external etching during the manufacturing process; The bottom surface of each end is attached to both side regions outside the groove of the silicon substrate so that the center portion is spaced apart from the groove of the silicon substrate, and the center portion is spaced apart from the groove of the silicon substrate. A movable lower support; And Both ends are stacked on the lower support so that they are positioned on the groove of the silicon substrate, and when a voltage is applied, a portion spaced apart from the groove is driven up and down, and includes a piezoelectric mirror layer for diffracting the incident beam. Thin film piezoelectric micro mirror. The method of claim 5, wherein And said sidewall protective layer is a p-type high concentration ion implantation layer formed by ion implantation of a group 3 element. The method of claim 5, wherein And said sidewall protective layer is an n-type high concentration ion implantation layer formed by ion implantation of a Group 5 element. A silicon substrate having grooves perpendicular to the bottom surface of both side walls formed along a longitudinal direction in a central portion thereof; A lower protective layer which prevents etching of the lower layer during the manufacturing process with an oxide layer formed at a predetermined depth on the bottom surface of the groove of the silicon substrate; A pair of sidewall protection layers formed of a high concentration ion implantation layer formed at a predetermined depth on the sidewalls of the grooves of the silicon substrate to prevent external etching during the manufacturing process; A lower supporter having a ribbon shape, and having lower surfaces at both ends thereof attached to both sides of the silicon substrate so as to be spaced apart from the groove of the silicon substrate; One end is located at the left end of the lower support, the other end is located a predetermined distance spaced to the left from the center of the lower support, the first piezoelectric layer that provides a vertical driving force by contraction and expansion when voltage is applied ; One end is located at the right end of the lower support, the other end is located a predetermined distance spaced to the right from the center of the lower support, the second piezoelectric layer that provides a vertical driving force by contraction and expansion when voltage is applied ; And Located in the central portion of the lower support, the diffractive thin film piezoelectric micromirror comprising a micromirror layer for diffracting the incident beam. The method of claim 8, And the sidewall protective layer is a p-type high concentration ion implantation layer formed by ion implantation of a group 3 element. The method of claim 8, And said sidewall protective layer is an n-type high concentration ion implantation layer formed by ion implantation of a Group 5 element.  Forming a lower protective layer by forming an oxide layer from a predetermined depth to a predetermined depth inside the silicon substrate; Stacking a mask on the silicon substrate and forming a pair of sidewall protective layers spaced apart from each other in a predetermined width from the surface to the lower protective layer by high concentration ion implantation; Forming a piezoelectric layer on the silicon substrate and patterning the piezoelectric layer to fabricate a diffraction thin film piezoelectric micromirror array; And And removing a silicon substrate region surrounded by the lower protective layer and the sidewall protective layer to form a diffractive thin film piezoelectric micromirror array. The method of claim 11, The second step, Stacking a mask on the silicon substrate; And A second step of forming a sidewall protective layer of a pair of p-type high concentration ion implantation layers spaced apart from each other in a predetermined width from the surface to the lower protective layer by implanting group 3 high concentration ions into the silicon substrate; Method for producing a diffractive thin film piezoelectric micromirror comprising. The method of claim 11, The second step, Stacking a mask on the silicon substrate; And Injecting high concentration ions of Group 5 into the substrate to form a sidewall protective layer of a pair of n-type high concentration ion implantation layers spaced apart from each other and parallel to each other at a predetermined width from a surface to the lower protective layer; A method for producing a diffractive thin film piezoelectric micromirror made. The method of claim 11, And a fifth step of forming a lower support on the substrate supporting the piezoelectric layer after the second step. The method of claim 11, The third step, Forming a lower electrode layer on the substrate; Forming a piezoelectric material layer on the lower electrode layer formed in step 3-1; Forming a top electrode layer having a micro mirror function on the piezoelectric material layer formed in step 3-2; And And forming a diffractive thin film piezoelectric micromirror array by patterning the piezoelectric layer formed of the lower electrode layer, the piezoelectric material layer, and the upper electrode layer to form a diffractive thin film piezoelectric micromirror array. The method of claim 15, After the above steps 3-4, And a third step of removing the piezoelectric layer outside the portion where the sacrificial layer is located. The method of claim 11, The third step, Forming a lower electrode layer on the substrate; Forming a piezoelectric material layer on the lower electrode layer formed in step 3-1; Removing the piezoelectric layer having a predetermined width from a center portion of the portion where the sacrificial layer is located; Forming a micromirror layer on the lower support on which the piezoelectric layer is removed; And And forming a diffractive thin film piezoelectric micromirror array by patterning a piezoelectric layer including the lower support, the lower electrode layer, the piezoelectric material layer, and the upper electrode layer to form a diffractive thin film piezoelectric micromirror array.  Forming a lower protective layer by forming an oxide layer from a predetermined depth to a predetermined depth inside the silicon substrate; Stacking a mask on the silicon substrate and implanting high concentration ions to form a pair of side wall protective layers spaced apart and parallel to each other at a predetermined width from a surface to the lower protective layer; Forming a piezoelectric layer on the silicon substrate and removing the sacrificial layer on the lower protective layer; And And manufacturing a diffractive thin film piezoelectric micromirror array by patterning the piezoelectric layer. The method of claim 18, The second step, Stacking a mask on the substrate; And And forming a sidewall protective layer of the p-type high concentration ion implantation layer by implanting high concentration ions of Group 3 into the substrate. The method of claim 18, The second step, Stacking a mask on the substrate; And And forming a sidewall protective layer of the n-type high concentration ion implantation layer by implanting high concentration ions of Group 5 into the substrate.

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