KR100812062B1 - Inverter and display device having the same - Google Patents

Abstract

The present invention relates to an inverter and a display device having the same, and more particularly, to an inverter composed of only a PMOS and a display device having the same. An inverter according to the present invention is connected to a first power line and is connected to a first transistor supplied with an input signal to a gate, and is connected to the first power line and an output terminal, and a gate to receive the same input signal as the first transistor. A second transistor, a third transistor connected between the second transistor and a second power line, and a first electrode connected to the first transistor, and a second electrode connected to a gate of the third transistor; The first to third transistors all have a PMOS structure.

Inverter, PMOS, Transistor, Display, Diode

Description

Inverter and display device having the same {Inverter and display device having the same}

1 is a circuit diagram showing the structure of a conventional inverter.

2 is a graph showing a simulation result of a conventional inverter.

3 is a circuit diagram showing the structure of an inverter according to a first embodiment of the present invention.

4 is a graph showing a simulation result according to the first embodiment of the present invention.

5 is a circuit diagram showing the structure of an inverter according to a second embodiment of the present invention.

6 is a graph showing a simulation result according to the second embodiment of the present invention.

7 is a circuit diagram showing the structure of an inverter according to a third embodiment of the present invention.

8 is a graph showing simulation results according to a third embodiment of the present invention.

9 is a circuit diagram showing the structure of an inverter according to a fourth embodiment of the present invention.

10 is a plan conceptual view illustrating a display device to which an inverter structure according to the present invention is applied.

*** Explanation of the main symbols in the drawing **

A1 to D1: first transistor A3 to D3: third transistor

A2 to D2: second transistor B4 to D4: fourth transistor

AC, CC, DC: Capacitor

The present invention relates to an inverter and a display device having the same, and more particularly, to an inverter composed of only a PMOS and a display device having the same.

Recently, the degree of integration of large-scale semiconductor integrated circuits (LSI) has been improved. A display device composed of an integrated circuit is composed of a combination of logic gates, called a NAND circuit or a NOR circuit, and the basis of such a logic gate is an inverter.

1 is a circuit diagram showing the structure of a conventional inverter, Figure 2 is a graph showing a simulation result of the conventional inverter.

Referring to FIG. 1, a conventional inverter includes a first transistor M1, a second transistor M2, a third transistor M3, and a capacitor C. FIG.

The first transistor M1 is connected to the first power supply VDD line and the output Vout terminal, and receives an input signal Vin to the gate.

The second transistor M2 is connected to the output Vout terminal and the second power supply VSS line, and has a gate connected to the first node a.

The third transistor M3 is diode-connected between the first node a and the second transistor M2.

The capacitor C has a first terminal connected to the first node a and a second terminal connected to the output Vout terminal.

Looking at the operation of the conventional inverter having the above-described structure as follows. First, when a low is applied as the input signal Vin, the threshold voltage Vth of the second power source VSS-third transistor is connected to the first node a through the diode-connected third transistor M3. However, the value of Vth <0) is applied. In this case, as the first transistor M1 is turned on, the output voltage Vout gradually approaches the value of the first power source VDD, and thus the second transistor M2 is also turned on. do. As a result, some problems described below will occur.

First, a static current path is formed through the first transistor M1 and the second transistor M2, thereby increasing power consumption. Second, the output voltage Vout is determined according to the on resistance ratio of the first transistor M1 and the second transistor M2, so that the output voltage Vout is set to the first power supply VDD which is the full high level. I can't reach it. Finally, in order for the output voltage Vout to be close to the first power supply VDD, the width W / length L of the second transistor M2 is equal to the width W / length of the first transistor M1 ( It should be very small compared to L). For this reason, when the input voltage Vin is at a high level, the discharge current through the second transistor M2 is small, which causes a problem in that the operating speed becomes slow when pulled down.

SUMMARY OF THE INVENTION An object of the present invention for solving the above-described problems is to simplify the process and improve driving characteristics by applying an inverter composed of only PMOS transistors to a display device.

As a technical means for achieving the above object, the first aspect of the present invention is connected to a first power supply line, a first transistor receiving an input signal to a gate, the first power supply line and an output terminal, and a first gate to the gate. A second transistor receiving the same input signal as the transistor, a third transistor connected between the second transistor and a second power line, and a first electrode connected to the first transistor, and a second electrode of the third transistor; It includes a capacitor connected to the gate, the first transistor to the third transistor to provide an inverter having a PMOS structure.

A second aspect of the present invention is connected to a first power line, the first transistor is supplied with an input signal to the gate, the first power line and the output terminal is connected, the gate receives the same input signal as the first transistor A second transistor, a third transistor connected between the output terminal and a second power supply line, and a fourth transistor diode-connected between the gate of the third transistor and the second power supply line, wherein the first to fourth transistors All of them are to provide inverters with PMOS structure.

According to a third aspect of the present invention, there is provided a display device including a plurality of inverters, wherein the inverter is connected to a first power line and is connected to a first transistor receiving an input signal at a gate, the first power line and an output terminal. A second transistor receiving the same input signal as the first transistor, a third transistor connected between the second transistor and a second power line, and a first electrode connected to the first transistor; The display device includes a capacitor connected to a gate of the third transistor, and the first to third transistors all have a PMOS structure.

In a display device including a plurality of inverters, the inverter is connected to a first power line, a first transistor receiving an input signal to a gate, the first power line and an output terminal, the gate is the first transistor A second transistor configured to receive the same input signal, a third transistor connected between the output terminal and a second power line, and a fourth transistor diode-connected between the gate and the second power line of the third transistor, The first to fourth transistors all provide a display device having a PMOS structure.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a circuit diagram illustrating a structure of an inverter according to a first embodiment of the present invention, and FIG. 4 is a graph showing a simulation result according to the first embodiment of the present invention.

Referring to FIGS. 3 and 4, an inverter according to the present invention includes a first transistor A1, a second transistor A2, a third transistor A3, and a capacitor AC.

The first transistor A1 is connected to the first power line AL1 and the capacitor AC, and receives an input signal Vin to the gate.

The second transistor A2 is connected to the first power line AL1 and the output Vout terminal and receives the same input signal Vin as the first transistor A1.

The third transistor A3 is connected to the output Vout terminal and the second power supply line AL2, and a gate thereof is connected to the second electrode of the capacitor AC.

The capacitor AC has a first electrode connected with the first transistor A1, and a second terminal connected with the third transistor A3.

On the other hand, all of the first transistor A1 to the third transistor A3 are PMOS transistors.

The operation of the inverter having the above-described structure will be described below. First, when a low signal is applied as the input signal Vin, the first transistor A1 and the second transistor A2 are turned on. As the first transistor A1 is turned on, a first power supply VDD 'is applied to the first electrode of the capacitor AC, and the second electrode is in a floating state. At this time, since the voltage is not applied to the third transistor A3 and turned off, the output path of the second power source VSS is blocked. As the second transistor A2 is turned on, the first power VDD is output as the output signal Vout.

Then, when a high signal is applied as the input signal Vin, the first transistor A1 and the second transistor A2 are turned off. Therefore, the voltage of the output signal Vout is gradually lowered so that the third transistor A3 is turned on by the capacitance Cgs between the gate and the source of the third transistor A3. Accordingly, the output signal Vout is lowered to the second power supply VSS. In addition, in the simulation result of the inverter according to the first embodiment of the present invention (FIG. 3), it can be confirmed that the rising time and the falling time are secured as the input signal Vin is inverted.

FIG. 5 is a circuit diagram showing the structure of an inverter according to a second embodiment of the present invention, and FIG. 5 is a graph showing a simulation result according to the second embodiment of the present invention.

Referring to FIGS. 5 and 6, an inverter according to the present invention includes a first transistor B1, a second transistor B2, a third transistor B3, and a fourth transistor B4.

The first transistor B1 is connected to the first power source VDD line and the fourth transistor B4 and receives an input signal Vin to the gate.

The second transistor B2 is connected to the first power supply VDD line and the output Vout terminal, and receives the same input signal Vin as the first transistor B1 to the gate.

The third transistor B3 is connected between the output Vout terminal and the second power supply VSS line.

The fourth transistor B4 is diode-connected between the gate of the third transistor B3 and the second power source VSS line.

On the other hand, all of the first to fourth transistors B1 to B4 are PMOS transistors.

The operation of the inverter having the above-described structure will be described below. First, when a low signal is supplied as the input signal Vin, the first transistor B1 and the second transistor B2 are turned on. As the first transistor B1 is turned on, a voltage close to the first power source VDD is applied to the first node A. FIG. At this time, the width W / length L of the first transistor B1 is formed to be larger than the width W / length L of the fourth transistor B4. That is, since the resistance R of the fourth transistor B4 is larger than the resistance R of the first transistor B1, the path of the second power source VSS through the fourth transistor B4 is blocked. Thus, a voltage close to the first power source VDD is applied to the first node A. FIG. Accordingly, the third transistor B3 is turned off, and as the second transistor B2 is turned on, the first power source VDD having a high level as the output signal Vout is drawn out. do. Accordingly, the static current path through the second transistor B2 and the third transistor B3 is also eliminated.

Thereafter, when a high signal is supplied as the input signal Vin, the first transistor B1 and the second transistor B2 are turned off. In addition, a voltage equal to the sum of the threshold voltage Vth of the second power source VSS and the fourth transistor is applied to the first node A by the diode-connected fourth transistor B4. At this time, a boost is generated by the parasitic capacitance between the gate and the source of the third transistor B3, and the threshold voltage Vth and Vth <of the second low power supply VSS + the third transistor are generated at the first node a. The voltage becomes less than 0), causing the third transistor B3 to be turned on completely. Accordingly, the output voltage Vout is lowered to the lowest level VSS, and since the width W / length L of the third transistor B3 may be a large value in operation, the discharge voltage Vout is discharged through the second transistor M2. Speed up the operation.

In addition, it can be seen from the simulation result of the inverter according to the second embodiment of the present invention (FIG. 5) that the rising time and the falling time are secured while the input signal Vin is inverted. In addition, according to the present embodiment, even when a high level voltage is supplied as the input signal Vin, the operation speed does not decrease as the output signal Vout is discharged through the third transistor B3.

7 is a circuit diagram showing the structure of an inverter according to a third embodiment of the present invention, and FIG. 8 is a graph showing a simulation result according to the third embodiment of the present invention.

Referring to FIGS. 7 and 8, an inverter according to the present invention may include a first transistor C1, a second transistor C2, a third transistor C3, a fourth transistor C4, and a capacitor CC. Include.

The first transistor C1 is connected to the first power line CL1 and the first electrode of the capacitor CC1 and receives an input signal Vin at the gate.

The second transistor C2 is connected to the first power line CL1 and the third transistor C3 and receives the same input signal Vin as the first transistor C1 at the gate.

The third transistor C3 is connected to the second transistor C2 and the second power line CL2, and a gate thereof is connected to the second electrode of the capacitor CC.

The fourth transistor C4 is connected to the second electrode and the second power line VSS of the capacitor CC and manufactured in a diode structure.

In the capacitor CC, a first electrode is connected to the first transistor C1 and a second electrode is connected to the fourth transistor C4.

On the other hand, all of the first to fourth transistors C1 to C4 are PMOS transistors.

In the first embodiment of the present invention described with reference to FIGS. 3 and 4, an unexpected situation may occur in an actual process because the gate voltage of the third transistor A3 is not initialized. For example, if a large amount of electric charges are collected in the gate line of the third transistor A3, the ON of the third transistor A3 cannot be controlled only by the capacitance of the capacitor AC, and thus the inverter operates normally. This can be difficult. In order to solve this problem, in the second and third embodiments of the present invention, a diode-connected fourth transistor C4 may be added to initialize the gate voltage of the third transistor C3.

Referring to the operation of the inverter as described above are as follows. First, when a low signal is supplied as the input signal Vin, the first transistor C1 and the second transistor C2 are turned on. As the first transistor C1 is turned on, a first power source VDD is applied to the first electrode of the capacitor CC, and the diode CC is connected to the first transistor C4. A voltage equal to the sum of the threshold voltage Vth of the second power source VSS and the fourth transistor C4 is applied to the second electrode. Therefore, the capacitor CC is charged with the voltage of VDD- (VSS + | Vth |). In addition, as the second transistor C2 is turned on, the first power source VDD is output as the output signal Vout.

On the other hand, when a high signal is supplied as the input signal Vin, the first transistor C1 and the second transistor C2 are turned off. Accordingly, the output voltage Vout is gradually lowered. At this time, a predetermined voltage held in the capacitor CC is applied to the gate of the third transistor C3, and the output voltage Vout is lowered to the second power supply VSS. In addition, in the simulation result of the inverter according to the third embodiment of the present invention (FIG. 7), it can be confirmed that a rising time and a falling time are secured while the input signal Vin is inverted.

9 is a circuit diagram showing the structure of an inverter according to a fourth embodiment of the present invention.

Referring to FIG. 9, an inverter according to the present invention includes a first transistor D1, a second transistor D2, a third transistor D3, a fourth transistor D4, and a capacitor DC.

The first transistor D1 is connected to the first power line DL1 and the first electrode of the capacitor DC and receives an input signal from the gate.

The second transistor D2 is connected to the first power line DL1 and the output Vout terminal and receives the same input signal as the first transistor D1.

The third transistor D3 is connected between the output Vout terminal and the second power line VL2.

The fourth transistor D4 is diode-connected between the gate of the third transistor D3 and the second power line VL2.

The capacitor DC has a first electrode connected with the first transistor D1 and a second electrode connected with the fourth transistor D4. Meanwhile, all of the first to fourth transistors D1 to D4 have a PMOS structure.

The operation of the inverter having the above-described structure is the same as in the second embodiment described with reference to FIGS. 4 and 5. In this embodiment, the capacitor DC is further added to the second embodiment to compensate for the boost operation when the input signal Vin is at a high level.

 10 is a plan conceptual view illustrating a display device to which an inverter structure according to the present invention is applied.

Referring to FIG. 10, the display device according to the present invention includes a pixel unit 100, a scan driver 200, a data driver 300, and a controller 400.

The pixel portion 100 includes a plurality of scan lines S1, S2, ... Sn, a plurality of data lines D1, D2, ... Dm, a plurality of scan lines S1, S2 ... Sn, and a plurality of scan lines S1, S2, ... Sn. A plurality of pixels 110 formed in a region defined by data lines D1, D2, ... Dm are included.

The scan driver 200 applies a scan signal to the plurality of scan lines S1, S2, ... Sn. On the other hand, the scan driver 200 includes a shift register 210, a level shifter 220 and a buffer 230. First, the shift register 210 sequentially supplies a signal to be supplied to the scan line to the level shifter 220. The level shifter 220 converts the signal received from the shift registerer 210 to a voltage level that can be supplied to the buffer 230 and the plurality of scan lines S1, S2, ... Sn. In addition, the buffer 230 prevents the operation speed from decreasing due to the load of the pixel unit 100.

The data driver 300 applies a data signal to the plurality of data lines D1, D2, ..., Dm.

Meanwhile, the scan driver 200 and the data driver 300 are directly mounted on a substrate (not shown). Such a structure is referred to as a chip on glass (COG) method.

The controller 400 supplies a control signal for driving the scan driver 200 and the data driver 300.

In the display device as described above, for example, the buffer 230 of the scan driver 200 includes a plurality of inverters (not shown). In the present invention, all the transistors employed in the inverter may be manufactured in a PMOS structure to simplify the process and improve driving characteristics. Since the structure of the preferred inverter is the same as described with reference to Figures 2 and 9 will be omitted on the page. In addition, in the present embodiment, only an example in which an inverter having a PMOS structure is applied to the scan driver has been described.

According to the inverter and the display device having the same according to the present invention, since the circuit is composed only of PMOS, the process can be simplified and the driving characteristics of the device can be improved. In addition, since the N type transistor having low mobility and high threshold voltage is not used compared to the P type, a high response speed is obtained.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various modifications are possible within the scope of the technical idea of the present invention.

Claims (8)

A first transistor connected to the first power line and the first electrode of the capacitor and receiving an input signal to the gate; A second transistor connected to the first power line and an output terminal and receiving a same input signal as a gate of the first transistor; It is connected between the output terminal and the second power line, the gate includes a third transistor connected to the second electrode of the capacitor, The capacitor is connected to the drain of the first transistor and the gate of the third transistor, The first to third transistors all have a PMOS structure. A first transistor connected to the gates of the first power line and the third transistor and receiving an input signal to the gate; A second transistor connected to the first power line and an output terminal and receiving the same input signal as a gate of the first transistor; A third transistor connected between the output terminal and a second power line; And A fourth transistor diode-connected between the gate of the third transistor and the second power line, The first to fourth transistors all have a PMOS structure. The method of claim 2, And a first electrode connected to the drain of the first transistor and a second electrode connected to the source of the fourth transistor. The method of claim 2, And a first electrode connected to the drain of the first transistor and a second electrode connected to the output terminal. In a display device including a plurality of inverters, The inverter A first transistor connected to the first power line and the first electrode of the capacitor and receiving an input signal to the gate; A second transistor connected to the first power line and an output terminal and receiving a same input signal as a gate of the first transistor; It is connected between the output terminal and the second power line, the gate includes a third transistor connected to the second electrode of the capacitor, The capacitor is connected to the drain of the first transistor and the gate of the third transistor, The first to third transistors all have a PMOS structure. In a display device including a plurality of inverters, The inverter A first transistor connected to the gates of the first power line and the third transistor and receiving an input signal to the gate; A second transistor connected to the first power line and an output terminal and receiving the same input signal as a gate of the first transistor; A third transistor connected between the output terminal and a second power line; And A fourth transistor diode-connected between the gate of the third transistor and the second power line, The first to fourth transistors all have a PMOS structure. The method of claim 6, The inverter And a first electrode connected to the drain of the first transistor and a second electrode connected to the source of the fourth transistor. The method of claim 6, The inverter And a first electrode connected to the drain of the first transistor and a second electrode connected to the output terminal.

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