KR100803254B1 - Computer readable recording medium for storing computer program - Google Patents

Abstract

An object of the present invention is to provide an asynchronous circuit design tool for a person skilled in the hardware description language of synchronous circuit design that is widely used in the industry to perform asynchronous circuit design relatively easily.

The asynchronous circuit design tool has conversion means for converting code described by an asynchronous circuit design language with a primitive that enables asynchronous interprocess communication to a hardware description language for synchronous circuit design into a hardware description language for synchronous circuit design. It includes one translator. By converting the code described by the asynchronous circuit design language into the hardware description language for the synchronous circuit design language, it becomes possible to perform functional verification of the circuit design by the commercial simulator for the synchronous circuit.

Asynchronous Circuits, Description Languages, Circuit Design, Primitives, Tools

Description

Computer-readable recording medium recording a computer program {COMPUTER READABLE RECORDING MEDIUM FOR STORING COMPUTER PROGRAM}

1 is a typical circuit design flow using industry standard Verilog HDL.

2 illustrates interprocess communication in an asynchronous circuit.

FIG. 3 shows a two phase handshake between processes. FIG.

4 shows a four phase handshake between processes.

5 illustrates a combination of port attributes.

6 is an explanatory diagram of port attributes and channel signals;

7 is an explanatory diagram of two-line encoding.

8 is an explanatory diagram of two-line encoding.

9 is an explanatory diagram of a handshake circuit.

10 is an asynchronous design description of process A.

11 is an asynchronous design technique of Process B.

12 illustrates an asynchronous design of process C.

13 is an explanatory diagram of a translator.

14 is an explanatory diagram of a dedicated simulator;

15 shows an example of Verilog code conversion of process A. FIG.

16 illustrates an asynchronous design of the handshake circuit.

Fig. 17 shows Verilog code conversion example of the handshake circuit.

18 shows a conversion scheme of two-wire encoding.

FIG. 19 is an explanatory diagram of a two-wire encoder / decoder. FIG.

20 is an explanatory diagram of a logic synthesis tool.

21 is a netlist of process A;

22 is a circuit diagram of Process A.

Fig. 23 is a reg-simple connection diagram.

24 is a bit-to-dual connection diagram.

25 is a Q_elem connection diagram.

Fig. 26 is a sequence of input / output signals of Q_elem.

27 is a Muller-C element connection diagram.

28 is asynchronous circuit design code using a probe command.

29 is a coding example of Verilog code.

30 is an explanatory diagram of asynchronous interprocess communication.

31 is an explanatory diagram of an interprocess handshake;

32 is an asynchronous circuit design code using a probe command.

33 is a coding example of Verilog code.

34 is an explanatory diagram of asynchronous interprocess communication.

35 is an explanatory diagram of an interprocess handshake;

36 is an asynchronous circuit design code using a sync command.

37 is a coding example of Verilog code.

38 is an explanatory diagram of asynchronous interprocess communication.

39 is an explanatory diagram of an interprocess handshake;

40 is an asynchronous circuit design code using a sync command.

Fig. 41 is a coding example of Verilog code.

* Description of the symbols for the main parts of the drawings

10: translator

11: conversion means

20: dedicated simulator

21: Verification means

30: logic synthesis tool

31: logical synthesis means

32: cell library

40: Asynchronous Circuit Design Language

50: Verilog Code

60: netlist

The present invention relates to asynchronous circuit design tools and computer programs for verifying or logically synthesizing code described by an asynchronous circuit design language.

Due to the rapid increase in circuit scale due to the rapid development of IC technology, text-based circuit design and verification by HDL (Hardware Description Language) is becoming common in digital circuit design. The remarkable increase in circuit scale has made the synchronous design technique of driving the entire circuit by the global clock quite a short time as a standard technique. Almost all CAE / CAD tools, SSI and MSI components, and cell libraries that make up the current commercial design environment are ready for synchronous design. However, as the semiconductor technology, the VLSI chip, and the clock frequency increase in recent years, problems of clock skew have occurred. Due to the miniaturization of the process, the delay of the switching element is small, while the wiring delay is relatively large. As a result, the delay of the clock system across the chip varies greatly depending on the place in the chip, and the phase consistency of the input / output signal of the device driven by the significantly different global clock signal is not already guaranteed. In addition to the problem of clock skew, increasing power consumption is also a major problem. The exponential increase of the power consumption of the VLSI due to the high speed of the device due to miniaturization and the exponential increase of the circuit scale has become a big problem. In addition, radiation noise synchronized with the clock of the synchronization circuit is also a problem. Asynchronous design has attracted attention as a technique for solving such problems of clock skew, power consumption and radiated noise.

In the case of designing an asynchronous circuit, there are a method of proceeding designing structurally and hierarchically starting from a schematic input and a method of designing and verifying using a design language on a text base. The former technique is intuitive and suitable for the design of small circuits, but not for the design of large circuits. In particular, considering the recent circuit size, it is necessary to verify whether the designed circuit performs the desired function, formal verification according to the design change, joint verification with software, and inter-block joint verification. It's a pretty unreal technique. In the latter design method, there are OCCAM, CSP, Tangram, and the like as the design language in the text base. OCCAM was also used as a parallel programming language for the transmitter, but was used in the design of asynchronous circuits by Brunvand, an assistant professor at Utha University. CSP was used as a VLSI programming language by the Alain Martin assistant professor group at the California Institute of Technology. Tangram is a CSP-based proprietary language developed by Kees van Berkel of the Philips lab, asynchronous circuit description language. Logical synthesis is performed by Syntax-directed Translation in the same way as CSP. Since these design languages and synthesis tools are not commercially available, engineers who can use them to design asynchronous circuits are limited to research institutes and universities. In addition, various tools for making the final LSI described using these design languages are owned by the respective institutions in the current state, and there is a problem that an industry standard has not yet been provided.

Accordingly, an object of the present invention is to provide an asynchronous circuit design tool and a computer program for a person skilled in the hardware description language of synchronous circuit design that is widely used in the industry for relatively asynchronous circuit design.

In order to solve the above problems, the asynchronous circuit design tool of the present invention synchronizes codes described by an asynchronous circuit design language with a primitive that enables asynchronous interprocess communication to a hardware description language for synchronous circuit design. A translator having conversion means for converting to a hardware description language for circuit design. By converting the code described by the asynchronous circuit design language into the hardware description language for the synchronous circuit design language, it becomes possible to perform the functional verification of the circuit design by a commercial simulator for the synchronous circuit.

The asynchronous circuit design tool of the present invention includes verification means for functionally verifying an asynchronous circuit design described by an asynchronous circuit design language with a primitive that enables asynchronous interprocess communication to a hardware description language for synchronous circuit design. Includes a dedicated simulator. By using a dedicated simulator for functionally verifying the asynchronous circuit design described by the asynchronous circuit design language, functional verification can be performed without converting the asynchronous circuit design language into the hardware description language for the synchronous circuit design language.

In the dedicated simulator constituting the asynchronous circuit design tool of the present invention, the verification means may perform functional verification after converting the asynchronous circuit design language into an intermediate language by a compile method, or in an interpreter method. The function verification can be performed by sequentially interpreting the asynchronous circuit design language. Compilation works well in large circuit designs, and interpreter works well in small circuit designs.

The asynchronous circuit design tool of the present invention is a logic synthesizing means for generating a netlist by logically synthesizing a code described by an asynchronous circuit design language with a primitive that enables asynchronous interprocess communication to a hardware description language for synchronous circuit design. It includes a logic synthesis tool having a. By generating a netlist by logically synthesizing the code described by the asynchronous circuit design language, it is possible to obtain circuit connection information that can be mounted on an actual circuit.

A logic synthesis tool constituting the asynchronous circuit design tool of the present invention, further comprising a cell library comprising a cell for synchronous circuit design and a cell for asynchronous circuit design, wherein the logic synthesis means generates a netlist by referring to the cell library It is preferable to set it as. By adding a cell for asynchronous circuit design in addition to a cell for synchronous circuit design, a cell library necessary for netlist generation can be constructed.

In the asynchronous circuit design language of the present invention, it is preferable to include cport and channel as data types for interprocess communication. The cport preferably has active / passive and input / output as attributes. For example, statements

cport active input [7: 0] A;

Declares that cport A is the active port and 8-bit input port.

Also, statements

channel [7: 0] T;

Declares that channel T is an 8-bit wide channel connecting the subport cport.

In the asynchronous circuit design language of the present invention, it is preferable to include send, receive, sync and probe as commands for interprocess communication. Specify a cport and a variable to communicate with in the statement.

Statement

send (A, x); receive (B, y);

Means that the data of the variable x is transmitted to the partner process through cport A, and the data received through the cport B is stored in the variable y.

Also, statements

sync (Z);

Means synchronizing using cport Z, but data transmission and reception are not performed. The send, receive, and sync commands activate 2-phase to 4-phase handshaking in the actual circuit.

In addition, a command probe is a function that returns a value, for example, a statement.

probe (B);

Returns immediate values on the channel connected to cport B via cport B. By using the probe command, any processing can be performed, for example, as preparation before initiating an interprocess handshake.

The computer program of the present invention is a converting means for converting a code described by an asynchronous circuit design language with a primitive that enables asynchronous interprocess communication to a hardware description language for synchronous circuit design into a hardware description language for synchronous circuit design. A computer program for operating a computer system. By executing a computer program for converting the code described by the asynchronous circuit design language into the hardware description language for the synchronous circuit design language, the function of the circuit design can be verified by the commercial simulator for the synchronous circuit.

The computer program of the present invention is a verification means for functionally verifying an asynchronous circuit design described by an asynchronous circuit design language with a primitive that enables asynchronous interprocess communication to a hardware description language for a synchronous circuit design. Computer program for functioning. By executing a computer program for functional verification of the asynchronous circuit design described by the asynchronous circuit design language, functional verification can be performed without converting the asynchronous circuit design language into the hardware description language for the synchronous circuit design language.

The computer program of the present invention functions after converting an asynchronous circuit design described by an asynchronous circuit design language with a primitive that enables asynchronous interprocess communication to a hardware description language for synchronous circuit design into an intermediate language by a compilation method. It is a computer program for operating a computer system as verification means for performing verification. In large circuit designs, the compilation method is appropriate.

The computer program of the present invention sequentially analyzes an asynchronous circuit design language by an interpreter method, which is described by an asynchronous circuit design language with a primitive that enables asynchronous interprocess communication to a hardware description language for synchronous circuit design. It is a computer program for making a computer system function as a verification means which performs a function verification while performing. In small circuit designs, the interpreter method is suitable.

The computer program of the present invention is a logic synthesis means for generating a netlist by logically synthesizing a code described by an asynchronous circuit design language with a primitive that enables asynchronous interprocess communication to a hardware description language for synchronous circuit design. A computer program for operating a computer system. By executing a computer program that generates a netlist by logically synthesizing the code described by the asynchronous circuit design language, circuit connection information that can be mounted on an actual circuit can be obtained.

In the computer program of the present invention, the primitive includes, for example, a probe command for executing an arbitrary process after reception of a request signal and before transmission of an acknowledgment signal in asynchronous interprocess communication. It is preferable. By using the probe command, arbitrary processing can be performed before initiating an interprocess handshake.

In the computer program of the present invention, the primitive preferably includes a sync command for synchronizing between ports, for example. By using the sync command, you can control asynchronous interprocess communication.

The computer program of the present invention can be recorded on a recording medium. As a recording medium, for example, a semiconductor memory element (ROM, RAM, EEPROM, etc.), a magnetic recording medium (a recording medium capable of magnetically reading data such as a flexible disk, a magnetic card), an optical recording medium (CD-RAM) , A recording medium capable of optically reading data such as a CD-ROM, DVD-RAM, DVD-ROM, DVD-R, PD disk, MD disk, MO disk). The information recording format on these recording media is not particularly limited.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

Figure 1 shows a typical circuit design flow using industry standard Verilog HDL. In Fig. 1, a disconnected frame means input / output data of a design technique or a design process, and a double line frame means a process of design. A design specification is a specification description for that design. Predetermined specifications are described in detail using intuitive and natural techniques such as natural language, tables, and drawings. This is the basis for the detailed specification of the product. Behavioral Description is a detailed description of the level of operation with respect to the design. It is also possible to describe the operation level using Verilog HDL. In that case, the Verilog HDL-specific simulator can be used to verify consistency with the design specification.

The RTL description is described using Verilog HDL, while the RTL description is architecture dependent, while the operating technology is architecture independent. The operation technique is not an object of logic synthesis, but the RTL technique is a technique capable of logic synthesis. Operational techniques are used in simulations to verify whether design specifications are accurately described, and at the same time, in the creation of test vectors for functional verification and testing using RTL techniques. The gate-level netlist, which is the output of logic synthesis, is used for logic verification by functional verification and testing with the cell library. After the logic verification, the physical verification after the Floor Planning Automatic Place & Route is performed to obtain a physical layout. As a result of the layout verification, if necessary, the layout is corrected, followed by implementation (Implementation), and chip production.

2 illustrates interprocess communication (handshake communication) in an asynchronous circuit. An asynchronous circuit means a circuit designed for the purpose of performing distributed control with each process (minimum functional circuit) autonomous or autonomous with local coordination without using a global clock. In the synchronous design, each operation such as instruction fetch, decode, execution, read / write, etc. is executed in synchronization with the global clock, so that the circuit operation is performed at high speed. In order to achieve this, problems such as clock delay, clock skew, clock jitter, and the like occur, but in an asynchronous design, since the processes operate autonomously or autonomously through handshake with each other, this problem does not occur. Each process is connected to another process via a communication channel and performs event driving autonomously or autonomously under local cooperation. The communication channel is connected to the port at both ends thereof. In the example shown in FIG. 2, process A has port a and process B has port b. Process A and Process B are connected through a communication channel at port a and port b. The communication channel consists of a request signal, an acknowledgment signal, and a data signal. Each process can run in parallel, independent of other processes, and does not have to wait for other processes to complete processing. The process may proceed at a stage where it is ready to execute the desired process.

3 shows two phase handshaking (Non Return to Zero) between processes, and transmits and receives a request / response signal at the rising or falling edge of the signal. For example, in the above example, in order to transmit a request signal from port a to port b, the request signal is raised from L level to H level, or lowered from H level to L level. Port b detects that a request signal has been sent from port a toward port b by detecting the rising or falling edge of the request signal. In order for the port b to return the response signal to the port a, it is sufficient to raise the level of the response signal from the L level to the H level or to decrease the level from the H level to the L level. This completes the handshake.

4 shows four-phase handshaking (Return to Zero) between processes, sending and receiving request / response signals at the signal level. For example, in the above-described example, in order to transmit the request signal from the port a to the port b, the request signal may be raised from the L level to the H level. When port b detects that the request signal has transitioned to the H level, it detects that the request signal has been transmitted. In order for the port b to return the response signal to the port a, the level of the response signal may be increased from the L level to the H level. After confirming that the level of the response signal has transitioned to the H level, the port a lowers the level of the request signal from the H level to the L level. After confirming that the level of the request signal has transitioned from the H level to the L level, the port b lowers the response signal level from the H level to the L level, and the handshake is completed. In the following description, for convenience of explanation, the inter-process communication is explained by employing four-phase handshaking.

5 illustrates a combination of port attributes. Because the process runs autonomously or autonomously, every port is given a property of 'Active' or 'Passive'. In addition, considering the attribute 2 of 'input' or 'output', it can be classified into four kinds of attributes. The opposite port attribute is uniquely determined according to the port attribute of the communication partner. For example, as shown in FIG. 6, when the port attribute of the process A which autonomously requests data transfer is "active input", the port attribute of the process B which performs data transfer autonomously is "passive output". The transmission and reception of the request signal and the response signal in the communication channel are performed by the two-phase handshaking or the four-phase handshaking described above. In this case, when two-line encoding is used, the response signal line can be reduced as shown in FIG. As shown in Fig. 8, when the port of the process A is "active output", since the direction of the request signal line and the data signal line are the same, the request signal line can be reduced. In the asynchronous design, the use of two-wire encoding in the design of the control unit and the datapath part eliminates the need for explicit delay element insertion and makes the circuit system Delay Insensitive. The present invention may correspond to both the bundle data method shown in FIG. 6 and the two-line encoding method shown in FIG. 7 or 8.

9 shows a handshake circuit between a plurality of processes. Each process has a plurality of ports and is configured to communicate with the plurality of processes. In the handshake circuit shown in FIG. 9, Process A also communicates with Process C while communicating with Process B. FIG. Process A is active for processes B and C (indicated by black circles), but process B is passive for process A and C (indicated by white circles). Process C is passive for Process A and active for Process B. Note that in the process A, since the attribute of the port Pa1 is an active input, as shown in Fig. 6, the handshake is initiated by transmitting a request signal by itself to receive data from the process B. On the other hand, since the attribute of the port Pa2 is the active output, as shown in Fig. 8, the handshake is initiated by sending a request signal by itself to transmit data to the process C.

In the present invention, by adding a new primitive that enables asynchronous interprocess communication to a hardware description language such as Verilog HDL, circuit design is performed using an asynchronous circuit design language that realizes interprocess communication exchanged in the above-described handshake circuit. . FIG. 10 shows a coding example in which Process A shown in FIG. 9 is coded using the asynchronous circuit design language of the present invention. Referring to the coding example shown in FIG. 10 in accordance with the grammar, first, the module declaration unit declares the module name "A" and the input / output signal names "RESET, Pa1, Pa2". In the input / output signal (port) declaration unit, an input signal "RESET" of one bit and a variable "regA" of two bits are declared. In addition, the declaration cport newly introduced by the asynchronous circuit design language of the present invention declares the port names "Pa1, Pa2" and their attributes for performing asynchronous interprocess communication. The property of port Pa1 is the active input, and the property of port Pa2 is the active output. Receipt from process B is executed by the receive command, and transmission to process C is executed by the send command. The receive command and the send command are commands newly introduced by the asynchronous circuit design language of the present invention. Referring to the always statement, waiting for the initialization signal RESET to be released, data from Process B received via port Pa1 is received in variable regA and coded to be sent to Process C via port Pa2. The processes B and C shown in Fig. 9 are coded in an asynchronous circuit design language, as shown in Figs. 11 and 12, respectively.

13 is a functional block diagram of the asynchronous circuit design tool 100. The asynchronous circuit design tool 100 includes a translator 10. The translator 10 is a hardware description language for synchronous circuit design (e.g., a subset or fullset of Verilog HDL or VHDL) to an asynchronous circuit design language with primitives that enable asynchronous interprocess communication. The conversion means 11 which converts the code 40 described by the hardware description language (for example, Verilog HDL or VHDL) 50 for a synchronous circuit design is provided. By converting the code 40 into the hardware description language 50 for synchronous circuit design, the circuit design described by the asynchronous circuit design language can be verified by a commercial simulator for synchronous circuits. The translator 10 is realized by executing a computer program on the computer system that functions the computer system as the converting means 11.

Fig. 15 shows an example of the code conversion. The Verilog code of FIG. 15 corresponds to FIG. 7, but is not a two-wire encoding, but a circuit for determining whether a signal line including a data bus is high impedance. The actual circuit is implemented by two wire encoding. In other words, this Verilog code is used for simulation verification and is not intended for logic synthesis. In the module declaration section, the module name "A" and the input / output signal names "RESET, Pa1_req, Pa1_data, Pa2_data, Pa2_ack" are declared. In the input / output signal declaration section, the 1-bit input signal "RESET", the 2-bit variable "regA", the 1-bit output signal "Pa1_req", the 2-bit input data line "Pa1_data", and the 2-bit output data. The line "Pa2_data" and the 1-bit input signal line "Pa2_ack" are declared. As described above, since the four-phase handshaking is employed in this embodiment, the Verilog code of FIG. 15 will be described with reference to FIGS. 4 and 7.

The first begin-end block of the Verilog code follows the procedure described in Fig. 4, but the determination of whether data is output to the signal line is performed by determining whether the high impedance is in a single-wire state instead of the scheme of two-wire encoding. . In other words, the output signal Pa1_req corresponds to the request signal in FIG. 7, and the input signal Pa1_data corresponds to the response signal or data signal. First, Pa1_req is set to High by a force command, and a request is sent out and waits until data is output to the input data line Pa1_data, that is, until it is not high impedance. When data is output to the input data line Pa1_data, it is accommodated in the internal register regA. The second begin-end block follows the procedure described in Fig. 8, where the output data line Pa2_data corresponds to the request signal or data signal, and the input signal line Pa2_ack corresponds to the response signal. First, the contents of regA are outputted to the output data line Pa2_data by the force command, and wait until Pa2_ack is not high impedance. After receiving Pa2_ack, the output data line Pa2_data is opened with high impedance, waiting for Pa2_ack to become high impedance, and handshaking is completed.

FIG. 16 shows a coding example in which the handshake circuit of FIG. 9 constituted by the processes A, B, and C described in FIGS. 10 to 12 is coded by an asynchronous circuit design language. With the declaration channel newly introduced by the asynchronous circuit design language of the present invention, three 2-bit channels connecting processes A, B and C are declared as CH1, CH2 and CH3. An instance of each process is connected by these channels. When this coding example is converted into a Verilog code by the translator 10 described above, a Verilog code as shown in Fig. 17 is obtained. As shown in the Verilog code of FIG. 17, the channel CH (n = 1, 2, 3) of FIG. 16 has two kinds of wires CHn_ctrl (n = 1, 2, 3) and CHn_data (n = 1, 2). , 3). The port Pa1_req of the process A is connected to the wiring CH1_ctrl, and the port Pa1_data is connected to the wiring CH1_data. Similarly, the port Pc3_ack of the process C is connected to the wiring CH3_ctr, and the port Pc3_data is connected to the wiring CH3_data.

Incidentally, in the above description, the case where the code described by the asynchronous circuit design language is converted into the synchronous circuit design language and then functionally verified by a commercial simulator for the synchronous circuit is illustrated. However, as shown in FIG. 14, the dedicated simulator 20 The functional verification can also be performed by the asynchronous circuit design tool 100 provided with). The dedicated simulator 20 is a verification means for functionally verifying the asynchronous circuit design of the code 40 described by the asynchronous circuit design language with a primitive added to enable the asynchronous interprocess communication to the hardware description language for the synchronous circuit design ( 21). As the verification means 21, function verification may be performed after converting an asynchronous circuit design language into an intermediate language by a compilation method, or function verification may be performed while sequentially interpreting the asynchronous circuit design language by an interpreter method. . The dedicated simulator 20 is realized by executing a computer program on the computer system that functions the computer system as the verification means 21.

The code of the asynchronous circuit design language is converted into a netlist (circuit connection information) that can be implemented by the logic synthesis tool of the present invention. As described above, it is difficult to implement in the output list of the translator 10 of the process A. This is because detecting the arrival of data by detecting the high impedance of the data signal line is not practical in an actual circuit. The logic synthesis tool of the present invention will be described on the assumption that it is implemented by a dual-rail encoding method. 18 is an example of a coding scheme of two-wire encoding. 19 is a circuit diagram when a two-wire encoding scheme is used for 4-bit data transmission. For convenience of explanation, explanation will be made with attention to the d0 bit. First, since no meaningful data is output at first, the Send signal is Low and all data line pairs are {0, 0}. When the data to be transmitted to d0, for example, 1 is output and the transmission signal is set to High, {d0.0, d0.1} = {0, 1}. The decoder (four decoders in the case of 4 bits) provided in each data line pair on the receiving side also detects the arrival of data and obtains the data according to the scheme of FIG. Use the Muller-C element to wait for all the arrival signals from the decoder corresponding to each bit to be aligned. When the inputs to the Muller-C elements are all high, the receive signal goes high, resulting in the arrival of 4-bit data.

As described above, the asynchronous circuit design language described above is converted into a Verilog nestable that can be mounted by the asynchronous circuit design tool 100 having the logic synthesis tool 30. The logic synthesis tool 30 generates a netlist 60 by logically synthesizing the code 40 described by an asynchronous circuit design language with a primitive that enables asynchronous interprocess communication to a hardware description language for synchronous circuit design. Logical synthesis means 31 is provided. The logic synthesis tool 30 further includes a cell library 32 consisting of a cell for synchronous circuit design and a cell for asynchronous circuit design. The logical synthesizing means 31 generates the netlist 60 with reference to the cell library 32. The logic synthesizing tool 30 is realized by executing a computer program on the computer system that functions the computer system as the logical synthesizing means 31.

FIG. 21 is a netlist obtained by converting the coding example of process A shown in FIG. 10 by the logic synthesis tool 30. Referring to the declaration of this netlist, the two-bit port described in the list of FIG. 10 may be configured as input [3: 0] Pa1_d; It can be seen that it is expanded to output [3: 0] Pa2_d; and converted to 4-bit port. 22 is a circuit diagram corresponding to the list of FIG. Before explaining the circuit shown in FIG. 22, the description is added about each cell used for this circuit. These cells belong to the cell library 32 of the logic synthesis tool 30.

23 shows a reg-simple connection diagram. This cell is a decoder in the 2-wire encoding scheme of 1-bit data. d0 and d1 are two lines of one-bit input data. The decoded data is set in an internal register according to the scheme of FIG. 18 and output to the output lines Q and Q_. At this time, the put signal indicating the arrival of data becomes High. 24 shows a bit-to-dual connection diagram. When the transmission signal becomes high, the input signal D is 2-wire encoded and output to the output signals d0 and d1. 25 shows a Q_element connection diagram. This cell executes the sequence shown in FIG. 27 shows a Muller-C element connection diagram. When both A and B are high, Z is high. When both A and B are low, Z is low. Otherwise, the Z output does not change.

Here, the circuit diagram of the process A shown in FIG. 22 is demonstrated. The part enclosed by the dotted lines is a connection diagram generated by the logic synthesis tool 30, and is described in the list shown in FIG. 20 using the cells required from the cell library 32 that is added to the logic synthesis tool 30. Configure the circuit. The circle on the dotted line indicates that the corresponding signal line is the input / output port specified in the declaration cport. Next, the operation procedure of this circuit is demonstrated. Although not explicitly used in the list of FIG. 10, the initialization signal RESET is inserted into the list of FIG. 21, which is an output of logical synthesis. Since the RESET signal is initially high, the lc input X8_c of the Q_element is Low and is the initial state of the sequence shown in FIG. When the reset goes low, since Pa2_c is low, X8_c goes high (t1). Since this means that the input lc becomes High in FIG. 26, the sequence shown in FIG. 26 is started. As shown in Fig. 26, the input lc is transitioned to High, and the output rc is transitioned to High (t2). This means that Pa1_c transitions to High in FIG. Pa1_c is a request signal to process B (see Fig. 9).

Process B receives this request signal and sends two-wire encoded data to Pa1_d [n] (n = 0, 1, 2, 3). This data is decoded and latched as regA [0] and regA [1] inside reg-simple (regA [0] _ and regA [1] _ are inverted outputs). At the same time, X1_d and X2_d, which acknowledge the reception of data at this timing, go high and are input to the Muller-C element. Since there may be a deviation in the timing at which data arrives due to a deviation in the data line length of X1_d and X2_d, the timing at which both X1_d and X2_d become High cannot be assumed to be simultaneous. The output X0_d of the Muller-C element goes high when both X1_d and X2_d go high (t3). X0_d in FIG. 22 corresponds to rd in FIG. 26, and when it is shifted to High, Q_elem sets rc, that is, Pa1_c in FIG. 22 to Low (t4). The process B receives Pa1_c transitioned to Low, detects that the data sent from the process B to the process A has been received, and outputs Null on the data line to stop the sending of the data. Since reg-simple sets X1_d and X2_d to Low when the Null is output on the data line, the Muller-C element makes X0_d Low when both X1_d and X2_d become Low (t5). This completes handshaking with Process B.

Since X0_d in FIG. 22 goes low, rd transitions to Low in FIG. 26, Q_elem makes ld, that is, X8_dd in FIG. 22 high (t6). X8_dd is a bit-to-dual send signal. The bit-to-dual encodes the data regA [0] and regA [1] held in reg-simple and transmits them to Pa2_d [n] (n = 0, 1, 2, 3). Since this data transmission is a request from the process A in the process C (see FIG. 9), the process C sets the response signal Pa2_c to High after receiving this request. When Pa2_c goes high, X8_c (the input signal lc of Q_elem) that is the output of the NOR goes low (t7). Q_elem receives the input lc transitioned to Low, and transitions X8_dd as the output signal ld (bit-to-dual transmission signal) to Low (t8). The bit-to-dual receives the transition of the transmission signal to Low, stops the transmission of the 2-wire encoded data, and outputs Null to the data lines Pa2_d [n] (n = 0, 1, 2, 3). . Process C detects that a response has been received by process A by receiving Null, and transitions the response signal Pa2_c to High. As a result, the sequence with the process C is completed, but as shown in the list of FIG. 10, since it is always wait (! RESET), the process with the process B and the process C unless the RESET signal is set to High. Asynchronous communication is repeated.

Using the probe and sync of the present invention, it is possible to construct a more efficient circuit more simply. First, before describing the preferred embodiment, the communication primitives added to the subset of Verilog HDL are summarized below.

1. channel: Newly added data type, connected to the following cport.

2. cport: newly added data type, there are 6 types as below.

active input: active input port

active output: active output port

passive input: passive input port

passive output: passive output port

active sync: active sync port

passive sync: passive sync port

3. send / receive / sync / probe: New command for communication.

send: A command to send data read from a variable.

receive: A command to receive data and write to a variable.

sync: A command that synchronizes ports without involving data transmission and reception.

4. probe: Newly added Function.

probe: A Function that returns the immediate value on the channel connecting to the specified cport.

First, an embodiment using a probe function will be described. In handshaking of send or receive via a passive port, a sequence of transmission or reception is initiated by the arrival of a request signal from an opposite port. However, in actual circuits, handshaking may not be started immediately by the arrival of the request signal, but for example, waiting for the request signal, first performing other processing, and then performing handshaking of transmission or reception. According to the newly defined command, it is possible to wait for a request signal from an opposing port, perform other processing first, and then perform handshaking of transmission or reception.

28 is a coding example in which usage example 1 of the probe is described using an asynchronous circuit design language. In the coding example shown in FIG. 28, "..." Indicates an arbitrary statement. In the module declaration section, the module name "M" and the input / output signal name "P" are declared. In the input / output signal (port) declaration section, port P is declared to be an 8-bit cport passive output. In the if statement, it is described to execute the next statement ("..." between the if statement and send (P, a)) when the value returned by the probe (P) command is 1 bit. send (P, a) is a command for sending the value read from the variable a through the port P to the opposite port.

Fig. 29 is a code conversion example in which the example 1 of the probe is converted into a Verilog code. In the module declaration section, the module name "M" and the input / output signal names "P_ctrl, P_data" are declared. In the input / output signal declaration section, an input signal P_ctrl of 1 bit and an output signal P_data of 8 bits are declared. This state is as shown in FIG. Processes M and N are connected via respective ports P and Q. Port P is passive output and port Q is active input. When the port P receives the request signal from the port Q through P_ctrl, the port P transmits data (response signal) through the P_data. Returning to the description of FIG. 29, the if statement is coded to execute the next statement ("..." between the if statement and begin) when the value of P_ctrl is 1 bit. The begin-end statement is a statement that converts send (P, a) into Verilog code. The begin to end statements will be described with reference to FIG. First, wait until P_ctrl is not high impedance, execute the probe command, and output the value of variable a to P_data. Then wait for P_ctrl to become high impedance and open P_data (4-phase handshaking). Here, P_ctrl corresponds to the request signal, and P_data corresponds to the response signal. In this way, by using the probe command, after receiving the request signal from the opposing port and before responding to the opposing port with the response signal, the arbitrary message " Can be executed.

32 is a coding example in which usage example 2 of the probe is described using an asynchronous circuit design language. In the module declaration section, the module name "M" and the input / output signal name "P" are declared. In the input / output signal declaration section, port P is declared to be an 8-bit cport passive input. In the wait statement, when the value returned by the probe (P) command is a predetermined value of 8 bits (not high impedance), the statement of the case statement determined according to the value returned by the probe (P) command is returned. To execute. receive (P, a) is a command for assigning a value received through port P to variable a.

Fig. 33 is a code conversion example of converting use example 2 of the probe to Verilog code. In the module declaration section, the module name "M" and the input / output signal names "P_ctrl, P_data" are declared. In the input / output signal declaration section, an 8-bit input signal P_data and a 1-bit output signal P_ctrl are declared. This state is as shown in FIG. Processes M and N are connected via respective ports P and Q. Port P is passive input and port Q is active output. When the port P receives data (a request signal) from the port Q through P_data, the port P responds with a response signal through P_ctrl. Returning to the description of FIG. 33, the wait statement is a statement of the case statement determined according to the value of P_data when the value of P_data is an 8-bit predetermined value (not high impedance). To execute. The begin ~ end statement is the conversion of receive (P, a) into Verilog code. The begin to end statements will be described with reference to FIG. First, it waits until P_data is not high impedance, executes a probe command, and assigns the value output to P_data to variable a. Subsequently, 1 bit of 1 is output to P_ctrl, and P_ctrl is opened by waiting for P_data to become high impedance (four-phase handshaking). Here, P_data corresponds to the request signal, and P_ctrl corresponds to the response signal. In this way, by using the probe command, after receiving the request signal from the opposing port and before responding to the opposing port with the response signal, any statement specified in the case statement is... Can be executed.

Fig. 36 is a coding example for describing the use example 1 of sync using an asynchronous circuit design language. In the module declaration section, the module name "M" and the input / output signal name "P" are declared. In the input / output signal declaration section, the port P is declared to be cport passive sync. sync (P) is a command for synchronizing between ports via the port P.

Fig. 37 is a code conversion example of converting sync example 1 to Verilog code. In the module declaration section, the module name "M" and the input / output signal names "P_ctrl, P_data" are declared. In the input / output signal declaration section, the input signal P_ctrl and the output signal P_data are declared. This state is as shown in FIG. Processes M and X are connected via ports P and Q. Port P is passive sync and port Q is active sync. In addition, processes M and N are connected via ports R and S. FIG. Port R is the active input and port S is the passive output. The ports P and Q perform synchronization between ports without performing data transmission / reception. Ports R and S perform data transmission and reception through handshaking. Returning to the description of FIG. 37, the begin to end statements convert sync (P) into Verilog codes. In this begin to end statement, first, the terminal waits until P_ctrl is not high impedance, and outputs 1 bit of 1 to P_data. Subsequently, P_ctrl waits for high impedance to open P_data. This makes it possible to synchronize ports P and Q.

An example of the use of the sync command will be described with reference to FIGS. 38 and 39. Here, the process which the process X controls the communication between the processes M and N through the ports P and Q is illustrated. When the process M detects the arrival of the request signal from the port Q because P_ctrl is not high impedance, the process M outputs a request signal for requesting data transfer to the process N to R_ctrl. Then, data is output from process N to R_data. This data is a response signal to the request signal. Process M receives the data output in R_data and negates R_ctrl. When the process M completes the reception of data from R_data, it outputs a response signal to P_data. Then P_ctrl is canceled. In this way, it is also possible to control communication between processes by using the sync command.

40 is a coding example in which sync example 2 of sync is described using an asynchronous circuit design language. In the module declaration section, the module name "M" and the input / output signal name "P" are declared. In the input / output signal declaration section, the port P is declared to be cport active sync. The if statement is a statement between the if statement and sync (P) when the value returned by probe (P) is 1 bit 1. To execute. This example shows the use of the probe command, but the if statement is not required but can be omitted.

Fig. 41 is a code conversion example of converting use example 2 of sync to Verilog code. In the module declaration section, the module name "M" and the input / output signal names "P_ctrl, P_data" are declared. In the input / output signal declaration section, the input signal P_data and the output signal P_ctrl are declared. The if statement is coded to execute the next statement ("..." between the if statement and begin) when the value of P_ctrl is 1 bit 1. The begin ~ end statement is a conversion of sync (P) into Verilog code. In this begin to end statement, first, one bit 1 is output to P_ctrl, and waits for P_data not to be high impedance. If P_data is not high impedance, open P_ctrl and wait for P_data to be canceled.

According to the present embodiment, it is possible to provide an environment in which a technician skilled in the industry standard HDL (Verilog HDL and VHDL) can design an asynchronous circuit relatively easily. As a result, as semiconductor processes progress in miniaturization, the reliability of the synchronous circuit design (current power problem, clock skew problem, etc.) has been exceeded. And it becomes possible to draw out by verifiability. In addition, since the portability of the asynchronous circuit is high, it is possible to repeatedly use the asynchronous circuit design technology developed by the present invention as IP, so that it becomes easy to cope with a shortage of engineers and short-term development. In addition, the present embodiment can provide an environment in which asynchronous circuits with very low electromagnetic radiation are developed for various products. The asynchronous circuit design technology of the present invention is an ultra-low power consumption VLSI, a semi-finished or finished product (PDA, smart card, e-book, etc.) integrally composed thereof, LSI using a TFT technology, a semi-finished product using the same or Applicable to the finished product. Specifically, the present invention can be applied to wearable devices, toys, home crime prevention sensor-related devices, electronic devices that do not contain batteries such as RFID, automobile-mounted devices, medical devices, military products, and the like.

According to the present invention, it is possible to provide an asynchronous circuit design tool and a computer program for performing asynchronous circuit design relatively easily to those skilled in the hardware description language of the synchronous circuit design that are widely used in the industry.

Claims (12)

delete delete delete delete delete delete delete Functioning a computer system as a converting means for converting code described by an asynchronous circuit design language with a primitive that enables asynchronous interprocess communication to a hardware description language for synchronous circuit design into the hardware description language for synchronous circuit design. A computer readable recording medium having recorded thereon a computer program. A verification means for functionally verifying an asynchronous circuit design described by an asynchronous circuit design language with a primitive that enables asynchronous interprocess communication to a hardware description language for synchronous circuit design, which records a computer program for functioning a computer system. Computer-readable recording medium. As verification means for performing functional verification after converting an asynchronous circuit design described by an asynchronous circuit design language with a primitive that enables asynchronous interprocess communication to a hardware description language for synchronous circuit design into an intermediate language by a compile method, A computer readable recording medium having recorded thereon a computer program for operating a computer system. Verification that performs functional verification while interpreting the asynchronous circuit design language in turn by an interpreter method, which is described by an asynchronous circuit design language with primitives that enable asynchronous interprocess communication to a hardware description language for synchronous circuit design. A computer-readable recording medium having recorded thereon a computer program for operating a computer system as a means. A logical synthesis means for generating a netlist by logically synthesizing code described by an asynchronous circuit design language with primitives that enable asynchronous interprocess communication to a hardware description language for synchronous circuit design. Computer-readable recording medium that records a program.

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