KR100803129B1 - Error correction method in digital broadcasting receiving system - Google Patents

Abstract

The present invention relates to an error correction method in a digital broadcasting reception system, wherein an erasing RS decoder used to correct an error in a process of playing received digital broadcasting data includes a key equation for obtaining an error position polynomial and an error magnitude polynomial. key equation). However, key equation operations take the largest part of the total computation time and have the largest hardware complexity. The present invention is to solve the above problems, in a digital broadcast receiving system that can reduce the hardware complexity compared to the conventional erasing RS decoder by using a 2-memory recursive operation method in the key equation operation To provide an error correction method.

RS, error, decoder, recursive, memory

Description

Error correction method in digital broadcasting reception system {ERROR CORRECTION METHOD IN DIGITAL BROADCASTING RECEIVING SYSTEM}

1 is a flowchart illustrating an erase RS decoding process using a Berekamp Massey algorithm.

2 illustrates arithmetic blocks of a modified syndrome polynomial.

3 is a block diagram illustrating a two-memory recursive calculation method in a digital broadcasting reception system according to an embodiment of the present invention.

4 is a time divisional representation of a two-memory recursive operation.

5 is a block diagram illustrating a protocol stack in an OSI 3 layer.

6 is a diagram showing the structure of an MPE-FEC frame.

<Explanation of symbols for the main parts of the drawings>

301, 302: memory

The present invention relates to an error correction method of a digital broadcast reception system, and more particularly, to a method of simplifying a hardware structure of an erasure RS decoder used for error correction in a DVB-H reception system.

The general RS code decoding process can be divided into five steps: calculation of syndrome polynomial, error locator polynomial and error magnitude polynomial, error location and error value calculation, and error correction. .

Among them, the key equation operation for calculating the error position polynomial and the error magnitude polynomial occupies the largest part of the total computation time and has the largest hardware complexity. Thus, the key equation operation structure is an important part of determining the performance of the RS decoder. Algorithms for computing key equations include the Berlekamp-Massey algorithm, the Euclidean algorithm, and the modified Euclidean algorithm.

1 is a flowchart illustrating an erase RS decoding process using a Berekamp Massey algorithm.

As shown in FIG. 1, when RS encoded data is received, an operation of a syndrome polynomial S (x) capable of determining whether an error is present in a codeword is first performed. If an error is found in the operation of the syndrome polynomial, it means that there is an error in the codeword. polynomial) calculate Γ (x). Then, the modified syndrome polynomial S (x) and the erase locator polynomial Γ (x) are multiplied to calculate a modified syndrome polynomial Ξ (x) (S110).

Next, an error locator polynomial Λ (x) is generated using the modified syndrome polynomial Ξ (x) using the Berekkamp algorithm (S111).

Next, the resulting error locator polynomial Λ (x), the new error / erase locator polynomial Ψ (x), and the error magnitude polynomial Ω (x) are obtained. error value) e _ik and an erase value f _ik are calculated to perform error correction (S112).

However, in the hardware structure implemented by the general polynomial operation method described above, a low complexity pipeline structure is known, but in the case of multiplication between two polynomials such as a modified syndrome polynomial Ξ (x), the hardware The structure is very complicated.

In addition, the erase / error locator polynomial Ψ (x) and error magnitude polynomial Ω (x) are similarly required to operate in a similar manner to the modified syndrome polynomial Ξ (x). The hardware complexity of the cancellation RS decoder has been greatly increased.

2 is a diagram illustrating a calculation block of a modified syndrome polynomial Ξ (x).

As shown in FIG. 2, when using this modified syndrome polynomial Ξ (x) operation, a component required for the operation of the erase locator polynomial Ξ (x) of RS (255,191, t = 32) has a maximum of 8 bits. We need 4096 flip-flops and 2016 8-bit XOR circuits. This is more than 50% of the overall complexity for a typical RS decoder that does not use an erase operator in a single operation block.

As described above, the general cancellation RS decoder used to improve the reception performance of the DVB-H reception system has a problem in that the hardware complexity is greatly increased compared to the general RS decoder, making it difficult to implement the digital broadcast reception system in a small size.

The present invention has been made to solve the above problems, and an object of the present invention is to reduce the hardware complexity of the digital broadcast reception system by improving the hardware complexity of the erasing RS decoder.

In the method for correcting the error of the data by performing erasure RS decoding in the digital broadcast receiving system according to the present invention for achieving the above object,
(a) calculating a syndrome polynomial and an erase locator polynomial;
(b) calculating a modified syndrome polynomial obtained by multiplying the syndrome polynomial and the erase locator polynomial by two-memory recursive calculation; And,
(c) performing the error correction of the data by performing a Berelekamp-Massey algorithm with the value calculated in step (b).

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Here, step (b) sequentially stores the coefficient values of each order term of the modified syndrome calculated by multiplying the syndrome polynomial and the erase locator polynomial and in the first memory. XOR (Exclusive OR) operation of two bytes sequentially from the highest order term of the stored modified syndrome, and storing the calculated intermediate value in the second memory and the intermediate value stored in the second memory. XOR arithmetic operations are sequentially performed by two bytes from the highest order term of the value to the next order term, and the calculated intermediate value is stored in the first memory.

At this time, the step of storing the intermediate value XOR operation is preferably performed by repeating 63 times in one direction.

The present invention provides a complexity of the entire DVB-H reception system by using a 2-memory method without using flip-flops in the XOR operation of an erased RS decoder which is used to improve the reception performance of the DVB-H reception system. It is characterized by reducing.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, with reference to the accompanying drawings illustrating the configuration and operation of the embodiment of the present invention, the configuration and operation of the present invention shown in the drawings and described by it will be described as at least one embodiment, By the technical spirit of the present invention described above and its core configuration and operation is not limited.

3 is a block diagram illustrating a two-memory recursive calculation method in a digital broadcasting reception system according to an embodiment of the present invention.

As shown in FIG. 3, the two memories 301 and 302 each have a single port RAM structure having a 64 byte depth of 8 bits of data-width. The fastest way to read a total of 64 bytes of e-data over 64 clocks is the fastest process, so a total of two XOR arithmetic circuits are needed, one for each memory. When the XOR operation is performed by reading the syndrome value stored in the first memory 301 by 2 bytes and the process of storing the intermediate value of the operation performed in the second memory 302 is repeated 63 times, the first step is performed. ) The one-way operation ends. When performing the next step operation, the first memory 301 performs the one-way operation as described above from the second memory 302 to the first memory 301. The operation is repeated 63 times.

4 is a time-divided diagram of a 2-memory recursive operation in one direction.

As shown in the figure, the operation result of the first step is stored in the second memory unit (Second MEM) for 66 clocks in the first memory unit (First MEM), and then again stored in the second memory unit (Second MEM). The result is stored in the first memory unit (First MEM) through the XOR operation of the first step during the clock. Since the recursive operation can be performed repeatedly up to 32 times, a hardware structure diagram for the modified syndrome polynomial Ξ (x) operation requires 128 8-bit memories and two XOR circuits.

Specifically, the XOR operation spans two clocks at a time. In T = 0, the coefficient of the order term (x ⁿ ) of the syndrome value stored in the first memory is extracted. In T = 1, the coefficient of the order term (x ^n-1 ) of the syndrome value stored in the first memory is extracted. Extract In T = 2, the coefficient of the order term (x ⁿ ) of the syndrome value extracted from the first memory and the coefficient of the order term (x ^n-1 ) are XORed to perform an OROR of the intermediate value ( x ^{n '} ) coefficients are extracted and at the same time the coefficients of the order term (x ^n-2 ) of the syndrome value stored in the first memory. In T = 3, the coefficient of the order term x ^{n '} of the XOR-operated intermediate value is stored in a second memory, the coefficient of the order term x ^n-1 of the syndrome value extracted from the first memory, and The coefficient of the order term (x ^n-2 ) of the syndrome value is XORed to extract the coefficient of the order term (x ^n'-1 ) of the intermediate value, and at the same time the order term (x) of the syndrome value stored in the first memory. extract the coefficient of ^n-3 ). In T = 4, the coefficients of the order term (x ^n'-1 ) of the XOR ^-operated intermediate value are stored in a second memory, and the coefficients and the order term (x ^n-2 ) of the extracted syndrome value are stored. x ^n-3) by performing an XOR operation of the coefficient extracting a coefficient of an intermediate value of a difference suhang (x ^n'-2) and, at the same time the coefficient of difference suhang (x ^n-4) of the syndrome value stored in the first memory Extract In T = 5, the coefficients of the extracted order term (x ^n'-2 ) of the intermediate value are stored in a second memory, and the coefficients of the order term (x ^n-3 ) and the order term (x ⁿ ) of the extracted syndrome value are stored. ^-4 ) extracts the coefficients of the intermediate order term (x ^n'-3 ) by XOR operation of the coefficients of the intermediate value, and simultaneously extracts the coefficients of the order term (x ^n-5 ) of the syndrome value stored in the first memory. do.

As described above, as an example of the one-way operation of the two-memory regression operation, a total of 64 errors can be corrected in the erase RS decoding scheme. Therefore, the recursive operation of T = 0 to 63 is repeated as described above to perform the operation up to 32 times.

Table 1 shows the number of hardware configurations of a general erasing RS decoder and an erasing RS decoder according to a preferred embodiment of the present invention.

Although the number of memories is increased to 384 by the preferred embodiment of the present invention, compared to the polynomial operation used in the conventional erasing RS decoder, the hardware complexity and the space-consuming flip-flop circuit are not used. In addition, since the number of XOR circuits can be implemented as six, the size of the hardware can be greatly reduced with the complexity of the hardware compared to the conventional method.

Hereinafter, the DVB-H protocol stack and MPE (Multi-Protocol Encapsulation) -FEC (FEC) forward error correction (FEC) frame structure will be briefly described to facilitate understanding of the present invention. Explain.

FIG. 5 is a block diagram illustrating a protocol stack as an OSI 3 layer, and is divided into a network layer, a data link layer, and a physical layer.

As shown, MPE, MPE-FEC, and PSIP information of the datagram section structure are separated from the stream in the form of TS packets, and extracted as IP data from which the header and the CRC are removed from the section datagram. Extracting the IP data from the TS packet is all performed at the data link layer. The IP data in the data link layer is stored in a memory located inside or outside the data link layer through the RS decoder and the error interval is corrected, and the stored IP data is read from the host and played.

FIG. 6 shows the structure of an MPE-FEC frame. The MPE-FEC frame structure consists of 255 bytes and consists of 191 bytes of an application data table and 64 bytes of an RS data table.

RS decoding requires one row of MPE data and MPE-FEC data. However, since MPE and MPE-FEC Section data payloads are recorded continuously in vertical units, that is, column units, the addresses are jumped by number of row units to read them in order of row units. You should read as you go.

No_of_row is defined as four of 256, 512, 768, and 1024 in the DVB-H specification. The MAU is designed to automatically jump addresses in units of no_of_row. When the data is entered in the section unit, it includes the information of Start Address, End Address, Start, End of MPE and MPE-FEC. When parsing the section structure and telling the MAU the address, it starts with the Start Address and jumps to the no_of_row unit to read and write data. A typical RS decoder corrects for 32 bytes of symbol error, but due to the nature of the DVB-H data link layer, which can be determined by CRC check on a section-by-section basis, a clear RS decoding is used. Up to 64 bytes of error per row can be corrected.

Above, preferred embodiments of the present invention described above are disclosed for the above purposes, and such changes and implementations fall within the scope of the present invention.

As described above, the error correction method in the digital broadcasting reception system according to the present invention has the following effects.

First, it can greatly help to improve the hardware complexity of all broadcasting communication systems using erasure decoder. Especially, in the case of DVB-H reception system that needs to support various transmission modes, it has a great effect on hardware complexity improvement. have.

Second, there is an effect that can be widely applied to the data link layer of a similar broadcast receiving system introduced for IPDC (IP Data Casting).

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (3)

A method of correcting an error in data by performing erasing RS decoding in a digital broadcasting reception system, (a) calculating a syndrome polynomial and an erase locator polynomial; (b) calculating a modified syndrome polynomial obtained by multiplying the syndrome polynomial and the erase locator polynomial by two-memory recursive calculation; And, (c) performing a error correction of the data by performing a Berelekamp-Massey algorithm using the value calculated in step (b). . The method of claim 1, Step (b) is Sequentially storing coefficient values of each order term of the modified syndrome calculated by multiplying the syndrome polynomial and the erase locator polynomial by a first memory; An XOR (Exclusive OR) operation of two bytes sequentially from the highest order term of the modified syndrome stored in the first memory, and storing the calculated intermediate value in the second memory; In the digital broadcast receiving system, the step of XOR operation by two bytes sequentially from the highest order term of the intermediate value stored in the second memory to the next order term, and storing the calculated intermediate value in the first memory Error correction method. The method of claim 2, And storing the intermediate value calculated by the XOR is repeated 63 times in a unidirectional direction.

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