KR100802072B1 - Voltage discharging appratus and internal voltage generator having the same - Google Patents

Abstract

The present invention is to provide an internal power supply for providing a stable internal voltage, according to an aspect of the present invention, to output a feedback voltage having a constant voltage ratio with respect to the voltage applied to the supply terminal of the internal voltage Voltage feedback means for; Pull-down control means for detecting a level difference between a reference voltage and the feedback voltage in response to a drive signal and outputting a pull-down control signal; Level adjusting means for selectively connecting a pull-up resistor and a pull-down resistor to an output terminal of the pull-down control signal to adjust a width and a speed of a level change of the pull-down control signal; And a pull-down driver for pull-down driving the supply terminal of the internal voltage in response to the pull-down control signal.

Normal Voltage, Overdriving, Discharging, Switch, Offset Voltage

Description

VOLTAGE DISCHARGING APPRATUS AND INTERNAL VOLTAGE GENERATOR HAVING THE SAME}

1 is a conceptual diagram of a general bit line sense amplifier.

2 is a general circuit diagram of an internal power supply having an overdriving structure.

3A and 3B are internal circuit diagrams of the normal voltage generator shown in FIG.

FIG. 4 is a view showing an operation waveform diagram of the internal power supply device shown in FIGS. 2 to 3B and a level change of a normal voltage accordingly.

5 is an internal circuit diagram of a normal voltage discharging unit according to the related art.

6A and 6B illustrate changes in level of normal voltage according to driving of the normal voltage discharging unit illustrated in FIG. 5.

7 is a circuit diagram of a normal voltage discharging unit according to a first embodiment of the present invention.

8A and 8B are operational waveform diagrams of the normal voltage discharging unit of the present invention shown in FIG.

9 is a circuit diagram of a normal voltage discharging unit according to a second exemplary embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

100: driving part

200: control unit

300: level control

500: offset adjustment unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly, to an apparatus for discharging an internal power supply.

As low driving voltages are used to reduce the power of memory devices, there have been various technical supplements for assisting the operation of the sensing amplifier in memory devices including DRAM, and one of them is the overdriving structure of the sensing amplifier.

1 is a conceptual diagram of a general bit line sense amplifier 10.

As shown in FIG. 1, the bit line detection amplifier 10 receives data stored in a unit memory cell through positive or negative bit lines BL and BLB, and provides levels of positive and negative bit lines BL and BLB. Detect the difference and amplify it.

At this time, the data loaded on the positive and negative bit lines BL and BLB are amplified to the levels of the first and second driving voltages RTO and SB applied to drive the bit line sense amplifier 10.

However, since a plurality of unit memory cells are generally connected to one activated word line, the plurality of bit line sense amplifiers as described above are simultaneously driven. In addition, since the capacity of the capacitor in the unit memory cell for storing data is small, the data applied to the positive or negative bit line has a fine voltage level. Therefore, how fast it is possible to sense and amplify the data of the microvoltage level applied to the positive / negative bit line is determined by whether sufficient current can be supplied to the plurality of bit line sense amplifiers that are simultaneously driven.

Therefore, for more accurate and faster driving of the bit line sense amplifier, overdriving which temporarily applies a high level of voltage during the initial driving of detecting the level difference between the positive and negative bit lines is performed.

For reference, a core voltage VCORE used as a normal power source in the semiconductor memory device is applied to the first driving power source RTO. The external voltage VDD, which is higher than the core voltage VCORE, is temporarily applied for overdriving. In addition, the ground voltage VSS is applied to the second driving power source SB.

On the other hand, the following will be described with respect to a power supply having a structure for overdriving.

2 is a general circuit diagram of a power supply having an overdriving structure.

Referring to FIG. 2, the power supply device includes an external voltage driver PM1 for supplying an external voltage VDD to a supply terminal of the first driving power source RTO in response to an external power-supply signal VDD_ON, and an external device. The normal voltage generator 20 for generating the normal voltage VCORE having a level corresponding to the reference voltage VREFC by receiving the voltage VDD and the first driving power in response to the normal power-supply signal VCORE_ON. And a normal voltage driver PM2 for supplying the output voltage VCORE of the normal voltage generator 20 to the supply terminal of the RTO.

Next, a circuit implementation of the normal voltage generator 20 will be described with reference to the drawings. In particular, the normal voltage generator 20 has a different circuit implementation depending on whether the applied reference voltage VREFC has the same level as the normal voltage VCORE or has a voltage level 1/2 times. Let's take a look at all of them.

FIG. 3A is an internal circuit diagram of the normal voltage generator 20A shown in FIG. 2.

Referring to FIG. 3A, the normal voltage generator 20A detects a level difference between the reference voltage VREFC1 and the normal voltage VCORE and generates a control signal in response to a level of the control signal. And a driver PM3 for supplying the external voltage VDD to the supply terminal of the normal power supply VCORE.

The controller AMP1 is a differential amplifier having a reference voltage VREFC1 and a normal voltage VCORE as differential inputs, and has a negative feedback characteristic.

In addition, the driver PM3 is implemented as a PMOS transistor having a control signal as a gate input and having a source-drain path between a supply terminal of the external voltage VDD and a supply terminal of the normal voltage VCORE.

Let's look briefly at the operation. Here, it is assumed that the reference voltage VREFC1 has 1.5V.

First, when the level of the normal voltage VCORE drops, the controller AMP1 decreases the level of the control signal. Subsequently, the driver PM3 becomes more active and supplies more current as the level of the control signal decreases, so that the level of the normal voltage VCORE increases.

As such, the normal voltage VCORE generated through the process maintains 1.5V as the reference voltage VREFC1.

3B is another circuit diagram of the normal voltage generator 20B shown in FIG. 2.

Referring to FIG. 3B, the normal voltage generation unit 20B divides the normal voltage VCORE and outputs the feedback unit 21 for outputting the feedback-normal voltage FD_VCORE, and the feedback-normal voltage FD_VCORE and the reference. The controller AMP2 for generating a control signal by detecting a level difference between the voltages VREFC and the driver PM4 for supplying the external voltage VDD to a supply terminal of the normal voltage VCORE in response to the level of the control signal. ).

Here, the feedback unit 21 includes first and second resistor diodes connected in series between the supply terminal of the normal voltage VCORE and the supply terminal of the ground voltage VSS, and is connected to the connection node of the first and second resistance diodes. The voltage is output as the feedback-normal voltage FD_VCORE. At this time, the level of the feedback-normal voltage FD_VCORE has a ratio of 1/2 to the normal voltage VCORE.

In addition, the controller AMP2 is a differential amplifier having a reference voltage VREFC and a feedback-normal voltage FD_VCORE as differential inputs, and has a negative feedback characteristic.

For reference, it is assumed that the level of the reference voltage VREFC2 is 0.75V. That is, since the control unit AMP2 receives the feedback-normal voltage FD_VCORE and the reference voltage VREFC2 having a 1/2 voltage ratio with respect to the normal voltage VREFC2, the generated normal voltage VCORE is 1.5. Has a level of V. Therefore, it can be seen that the normal voltage generator 20b shown in FIG. 3B has the same drive as that shown in FIG. 3A.

Meanwhile, FIG. 4 is a view illustrating an operation waveform diagram of the internal power supply device shown in FIGS. 2 to 3B and a level change of the normal voltage accordingly.

As shown in FIG. 4, when the external power-supply signal VDD_ON is activated, the external voltage driver PM1 is activated to supply the external power VDD to the supply terminal of the first driving power RTO. As described above, the bit line sense amplifier 10 of the positive / negative bit lines BL and BLB is overdriven by supplying the first driving power supply RTO to the external voltage VDD higher than the normal voltage VCORE. It will quickly perform the initial sensing operation to detect the level difference.

Subsequently, when the sensing operation is sufficiently performed, the external power-supply signal VDD_ON is deactivated and the normal power-supply signal VCORE_ON is activated. Then, the normal voltage driver PM2 is activated to supply the normal voltage VCORE to the supply terminal of the first driving power source RTO. In this case, it can be seen that the level of the first driving power source RTO increased due to the external voltage VDD flows into the supply terminal of the normal voltage VCORE, so that the level of the normal voltage VCORE increases by ΔV1.

Thereafter, the elevated normal voltage VCORE is lowered by ΔV2 due to a leakage phenomenon of the transistor or a discharge through a very small transistor intentionally attached to the normal voltage generator for level safety of the normal voltage VCORE. That is, as shown, it can be seen that there is a problem in that the amount of the voltage ΔV2 discharged is extremely small so that the level of the normal voltage VCORE cannot be maintained at the target value. Moreover, when the overdriving operation is repeated, the level of the normal voltage VCORE continues to rise, causing the problem to deepen.

Therefore, a circuit for lowering (recovering) the level of the elevated normal voltage VCORE to the target value level is necessary. Next, the normal-voltage discharge block for lowering the level of the normal voltage will be described.

5 is an internal circuit diagram of a normal voltage discharging unit according to the related art.

Referring to FIG. 5, the normal voltage discharging unit according to the related art includes a voltage feedback unit 32 for outputting a feedback voltage HFVCORE having a predetermined voltage ratio with respect to a voltage applied to a supply terminal of the normal voltage VCORE; A pull-down control unit 34 for detecting a level difference between the reference voltage VREFC3 and the feedback voltage HFVCORE in response to the driving signal DC_EN and outputting a pull-down control signal DC_CTRL, and a pull-down control signal DC_CTRL. In response to the pull-down driver NM1 for driving the supply terminal of the normal voltage (VCORE).

In addition, the pull-down control unit 34 receives the reference voltage VREFC3 and the feedback voltage HFVCORE as differential inputs, detects a level difference, and outputs the output signals A and B, and the differential amplifier 34a of the differential amplifier 34a. A control signal activator 34b for activating the pull-down control signal DC_CTRL in response to the output signals A and B and a control for deactivating the pull-down control signal DC_CTRL in response to the deactivation of the drive signal DC_EN. And a signal deactivation unit NM2.

The pull-down driver NM1 is implemented as an NMOS transistor having a pull-down control signal DC_CTRL as a gate input and having a drain-source path between a supply terminal of the normal voltage VCORE and a supply terminal of the ground voltage VSS.

The voltage feedback unit 32 includes first and second resistance diodes NM3 and NM4 connected in series between a supply terminal of the normal voltage VCORE and a supply terminal of the ground voltage VSS, and include the first and second resistance diodes. The voltage applied to the connected nodes of (NM3, NM4) is output as the feedback voltage (HFVCORE).

For reference, the reference voltage VREFC3 is supplied by the reference voltage generator although not shown.

Meanwhile, the level change of the normal voltage VCORE according to the driving of the normal voltage discharging unit will be described with reference to the drawings.

6A and 6B illustrate changes in the level of the normal voltage VCORE according to the driving of the normal voltage discharging unit illustrated in FIG. 5. For reference, it is assumed that the reference voltage VREFC3 has a ratio of 1/2 with respect to the normal voltage VCORE.

As shown in FIG. 6A, first, the external power-supply signal VDD_ON is activated during the overdriving period, thereby increasing the level of the normal voltage VCORE.

Subsequently, when the external power-supply signal VDD_ON is deactivated, the driving signal DC_EN is activated and the activation period is maintained for the time to be discharged, which is usually maintained for several tens of ns.

Subsequently, in response to the activation of the driving signal DC_EN, the differential amplifier 34a is activated to detect and output a level difference between the reference voltage VREFC3 and the feedback voltage HFVCORE. In this case, since the level of the normal voltage VCORE is increased due to overdriving, the feedback voltage HFVCORE also has a voltage level higher than the reference voltage VREFC3. Therefore, the differential amplifier 34a lowers the level of its output signal and outputs it.

Subsequently, when the level of the output signal B of the differential amplifier 34a falls, the control signal activator 34b raises the level of the pull-down control signal DC_CTRL in proportion to this.

Accordingly, the pull-down driver NM1 pulls down the supply terminal of the normal voltage VCORE in response to the level rise of the pull-down control signal DC_CTRL, thereby lowering the level of the normal voltage VCORE.

By the way, when the size of pull-down driver NM1 is large, it discharges excessively below a target value as shown in a figure. At this time, since the normal voltage generator 20 for driving the supply terminal of the normal voltage VCORE is also driven, the level of the normal voltage VCORE is restored to the target value.

As such, while the driving signal DC_EN is activated, the normal voltage discharging unit and the normal voltage generator 20 are driven together so that the level of the normal voltage VCORE oscillates. This has a problem that arises. Therefore, the loss of current becomes large.

On the contrary, when the size of the pull-down driver NM1 is small, as shown in FIG. 6B, the level of the normal voltage VCORE raised due to overdriving may not be sufficiently discharged.

Therefore, in the related art, failure analysis for solving problems such as ringing phenomenon due to excessive discharging or rising of the normal voltage level due to insufficient discharging is performed by adjusting the size and response speed of the pull-down driver, and driving time of the normal voltage discharging unit. The adjustment was carried out. Such a test has the disadvantage of taking a long time due to the complexity of the failure analysis.

On the other hand, a differential amplifier is included to detect the level of the feedback voltage with respect to the reference voltage in the pull-down controller, and when the differential amplifier is implemented, an offset voltage is generated for the differential input so that the normal voltage level does not maintain the target value. This happens the same way.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide an internal power supply device for providing a stable internal voltage.

According to an aspect of the present invention for achieving the above technical problem, the voltage feedback means for outputting a feedback voltage having a constant voltage ratio with respect to the voltage applied to the supply terminal of the internal voltage; Pull-down control means for detecting a level difference between a reference voltage and the feedback voltage in response to a drive signal and outputting a pull-down control signal; Level adjusting means for selectively connecting a pull-up resistor and a pull-down resistor to an output terminal of the pull-down control signal to adjust a width and a speed of a level change of the pull-down control signal; And a pull-down driver for pull-down driving the supply terminal of the internal voltage in response to the pull-down control signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

(First embodiment)

7 is a circuit diagram of a normal voltage discharging unit according to a first embodiment of the present invention.

Referring to FIG. 7, the normal voltage discharging unit according to the first embodiment of the present disclosure detects a level difference between the voltage applied to the supply terminal of the normal voltage VCORE and the reference voltage VREFC in response to the driving signal DC_EN. The control unit 100, 200 for outputting the pull-down control signal DC_CTRL, the level adjusting unit 300 for adjusting the width (speed) of the level change of the pull-down control signal DC_CTRL, and the pull-down control In response to the signal DC_CTRL, a pull-down driver NM5 is provided to pull down the supply terminal of the normal voltage VCORE.

In addition, the controller is configured to output a feedback voltage HFVCORE having a predetermined voltage ratio with respect to the voltage applied to the supply terminal of the normal voltage VCORE, and the reference voltage VREFC in response to the driving signal DC_EN. ) And a pull-down control unit 200 for detecting a level difference between the feedback voltage HFVCORE and outputting the pull-down control signal DC_CTRL.

Here, the pull-down control unit 200 detects the level difference between the reference voltage VREFC and the feedback voltage HFVCORE, and outputs the level detector 220 and the level detector 220 for outputting the output signals C and D. The control signal activation unit 240 for activating the pull-down control signal DC_CTRL in response to the signals C and D, and the control for deactivating the pull-down control signal DC_CTRL in response to the deactivation of the driving signal DC_EN. And a signal deactivator NM6.

The internal blocks of the pull-down control unit 200 will be described in more detail in terms of circuit implementation.

The level detector 220 is activated in response to the activation of the driving signal DC_EN, and is implemented as a differential amplifier having a reference voltage VREFC and a feedback voltage HFVCORE as differential inputs. The level detector 220 is connected to the driving power supply transistor NM7 for supplying the driving power in response to the driving signal DC_EN, and the driving power supply transistor NM7, and is connected to the reference voltage VREFC and the feedback voltage HFVCORE. ) Is disposed between the differential input transistors NM8 and NM9, which are differentially applied, between the supply terminal of the external voltage VDD and the differential input transistors NM8 and NM9 to control the amount of current regulated by the differential input transistors NM8 and NM9. Resistor transistors PM5 and PM6 for outputting corresponding first and second output signals C and D are included.

The control signal activator 240 receives the first and second output signals C and D of the level detector 220 and is implemented as a current mirror formed between the external voltage VDD and the ground voltage VSS. The control signal activation unit 240 has a first output signal D as a gate input, a first PMOS transistor PM7 having a source-drain path at the supply terminal of the external voltage VDD and the output node N1, and the first PMOS transistor PM7. A second PMOS transistor PM8 having its first output signal D as a gate input and having its source terminal connected to a supply terminal of an external voltage VDD, and its gate at the drain terminal of the second PMOS transistor PM8. The first terminal is connected to the source terminal and the drain terminal is connected to the supply terminal of the ground voltage VSS, and the gate terminal of the first NMOS transistor NM11 is connected to the gate terminal thereof, and the output node ( NMOS transistor NM10 having a drain-source path between N1) and a supply terminal of ground voltage VSS.

The control signal deactivator NM6 has the inverted drive signal DC_EN as a gate input and has a drain-source path between the output node N1 of the control signal enabler 240 and the supply terminal of the ground voltage VSS. Implemented as an NMOS transistor.

The level controller 300 includes a PMOS transistor PM9 having a source-drain path between a supply terminal of the external voltage VDD and a node N1 to which the pull-down control signal DC_CTRL is applied, and a pull-down control signal DC_CTRL. NMOS transistor NM12 having a drain-source path between the node N1 to which the signal is applied and the supply terminal of the ground voltage VSS, and the node to which the first output signal D of the level detector 220 is applied. And a first switch SW1 for switching the gate terminal of the PMOS transistor PM9, a gate terminal of the NMOS transistor NM10 of the control signal activation unit 240, and a gate terminal of the NMOS transistor NM12. It includes two switches (SW2).

The pull-down driver NM5 is implemented as an NMOS transistor having a pull-down control signal DC_CTRL as a gate input and having a drain-source path between a supply terminal of the normal voltage VCORE and a supply terminal of the ground voltage VSS.

The voltage feedback unit 100 includes first and second resistance diodes NM13 and NM14 connected in series between a supply terminal of the normal voltage VCORE and a supply terminal of the ground voltage VSS, and includes first and second resistance diodes. The voltage applied to the connection nodes of (NM13, NM14) is output as the feedback voltage (HFVCORE).

For reference, the reference voltage VREFC is supplied by the reference voltage generator although not shown.

Further, although not shown in the drawing, a normal voltage generator for driving a supply terminal of the normal voltage, a normal driver for driving the voltage applied to the supply terminal of the normal voltage to the driving power line RT0 of the bit line sense amplifier, and a driving power supply The line RTO has an overdriving driver for overdriving to an external voltage higher than the normal voltage. At this time, after driving of the overdriving driver, the normal driver is activated.

Meanwhile, as described above, the normal voltage discharging unit further includes a level adjusting unit 300, so that the level of the pull-down control signal DC_CTRL for controlling the supply terminal of the normal voltage VCORE is discharged. The speed of change and the level of change of level can be adjusted by turning the switches SW1 and SW2 On / Off. In other words, the PMOS and NMOS transistors PM9 and NM12 are switched through on / off of the switches SW1 and SW2, thereby changing the resistance ratio of the control signal activation unit 240, thereby reducing the pull-down control signal DC_CTRL. You can adjust the rising or falling speed of the level. Therefore, the normal voltage discharging unit for maintaining the normal voltage elevated due to overdriving can be adjusted only by turning on / off the switch so as to have an appropriate drive, thereby speeding up the test process.

8A and 8B are operation waveform diagrams of the normal voltage discharging unit of the present invention shown in FIG. 7. For reference, it is assumed that the reference voltage VREFC has a ratio of 1/2 to the target value of the normal voltage VCORE.

As shown in FIG. 8A, since the external power-supply signal VDD_ON is activated during the overdriving period, the external voltage VDD is applied to increase the level of the normal voltage VCORE.

Subsequently, when the external power-supply signal VDD_ON is deactivated, the driving signal DC_EN is activated.

Subsequently, in response to the activation of the driving signal DC_EN, the driving power supply transistor NM7 is activated to apply the driving power. At this time, since the level of the normal voltage is increased due to overdriving, the feedback voltage HFVCORE also has a voltage level higher than the reference voltage VREFC. Accordingly, the differential input transistors NM8 and NM9 have a lower level of the output signal D and a higher level of the output signal C due to the level of the feedback voltage HFVCORE higher than the reference voltage VREFC.

Subsequently, the PMOS transistor PM7 in the control signal activator 240 increases the level of the pull-down control signal DC_CTRL proportionally as the level of the output signal D is increased.

Subsequently, the pull-down driver NM6 pulls down the supply terminal of the normal voltage VCORE in response to the level rise of the pull-down control signal DC_CTRL, thereby causing the level of the normal voltage VCORE to decrease.

At this time, if the normal voltage is excessively discharged due to the large size of the pull-down driver NM6, the ringing phenomenon occurs as shown by the dotted line. In addition, the transistor NM9 receiving the feedback voltage HFVCORE has the offset voltage of −α in comparison with the transistor NM8 to which the reference voltage VREFC in the differential amplifier 220 is applied. Excessive discharging occurs.

Accordingly, when the second switch SW2 is turned on, the active NMOS transistor NM12 is connected in parallel with the NMOS transistor NM10 in the control signal activator 240. In other words, since the resistance value between the node N1 and the supply terminal of the ground voltage VSS is reduced by the NMOS transistors NM10 and NM12 connected in parallel, the level of the pull-down control signal DC_CTRL is lowered faster and lower. Descends. Accordingly, the pull-down driver NM6 having this as an input is easily turned off to discharge a small amount of current from the supply terminal of the normal voltage VCORE, so that the level of the normal voltage VCORE is excessively low below the target value. It can prevent losing phenomenon.

Meanwhile, as shown by a dotted line in FIG. 8B, when the pull-down driver NM6 has a small size, discharging of the normal voltage VCORE is insufficient, resulting in a problem in which the normal voltage VCORE has a level higher than a target value. do. Further, even when the transistor NM9 to which the feedback voltage HFVCORE is applied has an offset voltage of + α, the discharging is not sufficiently performed compared to the transistor NM8 to which the reference voltage VREFC in the differential amplifier is applied.

At this time, when the first switch SW1 is turned on, the PMOS transistor PM9 is activated to be connected in parallel with the PMOS transistor PM7 in the control signal activator 240. This causes the level of the pull-down control signal DC_CTRL to rise to a higher level more quickly, so that the pull-down driver NM1 is easily turned on to discharge a larger amount of current. Therefore, the level of the normal voltage VCORE can be maintained at the target value.

Therefore, the normal voltage discharging unit according to the first embodiment may adjust the level rising speed and the rising width of the pull-down control signal DC_CTRL through switching of the switches SW1 and SW2. Therefore, in order to maintain the level of the normal voltage (VCORE) at the target value, it has been cumbersome to perform various defect tests such as adjusting the discharge time of the discharge and adjusting the size and response speed of the pull-down driver. Including the normal voltage discharging unit may properly adjust the level of the normal voltage VCORE only through switching of the switches SW1 and SW2, thereby reducing test time.

For reference, when the resistance ratio is adjusted through switching of the switch, the dead zone of the PMOS transistor PM7 and the NMOS transistor NM10 in the control signal activator that activates the pull-down control signal is consequently adjusted. . Here, the dead zone means a region in which the level of the gate terminal input voltage of the PMOS transistor and the NMOS transistor does not activate both.

Meanwhile, by adjusting the level of the feedback voltage to correct the offset voltage, the degree of discharge of the normal voltage supply terminal can be adjusted. This will be described in detail with reference to the accompanying drawings.

(Second embodiment)

9 is a circuit diagram of a normal voltage discharging unit according to a second exemplary embodiment of the present invention.

Referring to FIG. 9, the normal voltage discharging unit outputs a feedback voltage HFVCORE having a constant voltage ratio with respect to a voltage applied to a supply terminal of the normal voltage VCORE. The voltage feedback units 400 and 500, which can adjust the voltage, and sense the level difference between the reference voltage VREFC and the feedback voltage HFVCORE in response to the driving signal DC_EN to pull down the supply terminal of the normal voltage VCORE. It has a pull-down driving unit for.

In addition, the pull-down driving unit detects a level difference between the reference voltage VREFC and the feedback voltage HFVCORE in response to the driving signal DC_EN and outputs a pull-down control signal DC_CTRL, and pull-down control. In response to the signal DC_CTRL, a pull-down driver NM5 is provided to pull down the supply terminal of the normal voltage VCORE.

Here, the voltage feedback units 400 and 500 may include the first and second diode resistors NM15 and NM16 connected in series between the supply terminal of the normal voltage VCORE and the output node N2, and the output node N2 and the ground voltage. A dividing unit 400 having third and fourth diode resistors NM17 and NM18 connected in series between the supply terminals of the VSS and outputting a voltage applied to the output node N2 as a feedback voltage HFVCORE. And an offset adjuster 500 including a first switch SW3 connected to both ends of the second diode resistor NM16 and a second switch SW4 connected to both ends of the fourth diode resistor NM18. It includes.

For reference, when comparing the normal voltage discharging unit illustrated in FIG. 8 with the first embodiment, only the voltage feedback units 400 and 500 are different, and the other configurations are the same. Therefore, like reference numerals refer to like blocks, and detailed description thereof will be omitted.

On the other hand, the normal voltage discharging unit according to the second embodiment further includes an offset control unit, to raise or lower the level of the feedback voltage (HFVCORE) by a predetermined level through the control of the switch irrespective of the normal voltage (VCORE). Therefore, the driving of the normal voltage discharging unit for discharging the supply terminal of the normal voltage through the correction of the offset voltage is controlled.

The driving of the voltage feedback unit 400. First, it is assumed that the first and second switches SW3 and SW4 are turned on.

Subsequently, when the level of the normal voltage VCORE is excessively discharged below the target value, the second switch SW4 in the level controller 500 is turned off. Then, since the fourth diode resistor NM18 is newly connected by the turned-off second switch SW4, the level of the feedback voltage HFVCORE is increased by the resistance value of the fourth diode resistor NM18.

Therefore, when the level of the feedback voltage HFVCORE increases, the level of the feedback voltage HFVCORE with respect to the reference voltage VREFC is increased, so that the pull-down control unit 200 deactivates the pull-down control signal DC_CTRL relatively quickly. Let's do it. Excessive discharging of the normal voltage VCORE by the pull-down driver NM5 is prevented.

In addition, when the normal voltage VCORE is not sufficiently discharged and has a value equal to or greater than the target value, the first switch SW3 is turned off. Then, since the second diode resistor NM16 is newly connected by the turned-off first switch SW3, the level of the feedback voltage HFVCORE decreases by the resistance value of the second diode resistor NM16.

Since the level of the feedback voltage HFVCORE with respect to the reference voltage VREFC is increased, the pull-down control unit 200 deactivates the pull-down control signal DC_CTRL relatively slowly. Since the pull-down driver NM5 is driven longer, the normal voltage VCORE is maintained at the target value.

Therefore, the normal voltage discharging unit according to the second embodiment further includes an offset adjusting unit to adjust the level of the feedback voltage through on / off of the switch, so that the offset voltage of the feedback voltage with respect to the reference voltage is easily adjusted to ± α. Be sure to That is, the amount of discharge of the supply terminal of the normal voltage is adjusted by adjusting the offset voltage.

Meanwhile, in the above-described present invention, only one transistor is further provided to control pull-down and pull-up swing of the pull-down control signal, but this may further include a plurality of transistors as one embodiment. The use of multiple transistors can provide additional margin for offset.

On the other hand, in the above-described invention, only the case of selectively providing only the level adjusting unit for controlling the swing width of the pull-down signal or the offset adjusting unit for adjusting the offset voltage, but provided with both the level adjusting unit or the offset adjusting unit Even if the same effect as described above is obtained.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The present invention described above adjusts the swing speed and the width of the control signal for adjusting the level of the voltage fed back through the on / off of the switch or the amount of voltage discharged, and by appropriately discharging the supply terminal of the voltage Keep the level of internal voltage stable.

Claims (36)

Voltage feedback means for outputting a feedback voltage having a constant voltage ratio with respect to the voltage applied to the supply terminal of the internal voltage; Pull-down control means for detecting a level difference between a reference voltage and the feedback voltage in response to a drive signal and outputting a pull-down control signal; Level adjusting means for selectively connecting a pull-up resistor and a pull-down resistor to an output terminal of the pull-down control signal to adjust a width and a speed of a level change of the pull-down control signal; And A pull-down driver for pull-down driving the supply terminal of the internal voltage in response to the pull-down control signal; Voltage discharging device having a. The method of claim 1, And the driving signal is a signal that is activated for a predetermined time after overdriving to a boosted voltage having a level higher than the internal voltage. The method of claim 2, The level adjusting means, And the pull-up resistor and the pull-down resistor are selectively connected to an output terminal (first node) of the pull-down control signal through a fuse option or a switch of a switch. The method of claim 3, The pull-down control means, A level detector for detecting a level difference between the reference voltage and the feedback voltage and outputting first and second output signals; A control signal activation unit for activating the pull-down control signal in response to the first and second output signals of the level sensing unit; And a control signal deactivation unit for deactivating the pull-down control signal in response to deactivation of the drive signal. Voltage discharge device characterized in that. The method of claim 4, wherein The control signal activator, A first PMOS transistor having the first output signal as a gate input and having a supply terminal for an external voltage and a source-drain path at the first node; A second PMOS transistor having the second output signal as a gate input and having its source terminal connected to a supply terminal of the external voltage; A first NMOS transistor having a gate terminal and a source terminal thereof connected to a drain terminal of the second PMOS transistor, and a drain terminal connected to a supply terminal of a ground voltage; A second NMOS transistor connected to a gate end of the first NMOS transistor and having a drain-source path between the first node and the supply terminal of the ground voltage; Voltage discharge device characterized in that. The method of claim 5, The level adjusting means, A third PMOS transistor having a source-drain path between the supply terminal of the external voltage and the first node; A third NMOS transistor having a drain-source path between the first node and the supply terminal of the ground voltage; A first switch for switching between the gate terminal of the first PMOS transistor and the gate terminal of the third PMOS transistor; And a second switch for switching the gate terminal of the second NMOS transistor and the gate terminal of the third NMOS transistor. Voltage discharge device characterized in that. The method of claim 6, The level detection unit, And a differential amplifier which is activated in response to the activation of the drive signal, and outputs the first and second output signals by bringing the reference voltage and the feedback voltage to a differential input. Voltage discharge device characterized in that. The method of claim 7, wherein The level detection unit, A current source transistor for supplying a bias voltage to the differential input transistor in response to the driving signal; A differential input transistor connected to the current source transistor and receiving the reference voltage and the feedback voltage differentially; And a loading unit connected to the differential input transistor for outputting the first and second output signals corresponding to the amount of current controlled by the differential input transistor. Voltage discharge device characterized in that. The method of claim 8, The loading unit, A fourth PMOS transistor having a voltage applied to a second node at which the first output signal is output as a gate input, and having a source-drain path between a supply terminal of the external voltage and a second node; A fifth PMOS transistor having a voltage applied to a third node at which the second output signal is output as a gate input, and having a source-drain path between a supply terminal of the external voltage and a third node; Wherein the second and third nodes are connection nodes with the differential input transistor. Voltage discharge device characterized in that. The method of claim 9, The voltage feedback means, First and second resistor diodes connected in series between the supply terminal of the internal voltage and the supply terminal of the ground voltage; Outputting the voltage across the connection node of the first and second resistor diodes as the feedback voltage Voltage discharge device characterized in that. A voltage feedback means for outputting a feedback voltage having a constant voltage ratio with respect to a voltage applied to a supply terminal of an internal voltage, and adjusting the constant voltage ratio; Pull-down control means for detecting a level difference between a reference voltage and the feedback voltage in response to a drive signal and outputting a pull-down control signal; And A pull-down driver for pull-down driving the supply terminal of the internal voltage in response to the pull-down control signal; Voltage discharging device having a. The method of claim 11, The driving signal is a voltage discharging device, characterized in that the signal is activated for a predetermined time after the overdrive to a voltage having a level higher than the internal voltage. The method of claim 12, The voltage feedback means, A dividing unit for dividing the internal voltage at the predetermined voltage ratio to output the feedback voltage; It includes a ratio adjusting unit for adjusting the constant voltage ratio through the fuse option or switching of the switch Voltage discharge device characterized in that. The method of claim 13, The dividing unit, First and second diode resistors connected in series between a supply terminal of the internal voltage and a first node for outputting the feedback voltage; Third and fourth diode resistors connected in series between the first node and the supply terminal of the ground voltage; Voltage discharge device characterized in that. The method of claim 14, The ratio adjusting unit, A first switch connected between the connection node of the first and second diode resistors and the first node; And a second switch connected between the connection node of the third and fourth diode resistors and the supply terminal of the ground voltage. Voltage discharge device characterized in that. The method of claim 15, The pull-down control means, A level detector for detecting a level difference between the reference voltage and the feedback voltage and outputting first and second output signals; A control signal activation unit for activating the pull-down control signal in response to the first and second output signals of the level sensing unit; And a control signal deactivation unit for deactivating the pull-down control signal in response to deactivation of the drive signal. Voltage discharge device characterized in that. The method of claim 16, The level detection unit, And a differential amplifier which is activated in response to the activation of the drive signal, and outputs the first and second output signals by bringing the reference voltage and the feedback voltage to a differential input. Voltage discharge device characterized in that. Feedback means for outputting a feedback voltage having a constant voltage ratio with respect to the voltage applied to the supply terminal of the internal voltage; Ratio adjusting means for adjusting the constant voltage ratio; Pull-down control means for detecting a level difference between a reference voltage and the feedback voltage in response to a drive signal and outputting a pull-down control signal; Level adjusting means for selectively connecting a pull-up resistor and a pull-down resistor to an output terminal of the pull-down control signal to adjust a width and a speed of a level change of the pull-down control signal; And A pull-down driver for pull-down driving the supply terminal of the internal voltage in response to the pull-down control signal; Voltage discharging device having a. The method of claim 18, And the driving signal is a signal which is activated for a predetermined time after overdriving the supply terminal of the internal voltage above the internal voltage. The method of claim 19, The level adjusting means, And a level adjusting means for selectively connecting the pull-up resistor and the pull-down resistor to an output terminal (first node) of the pull-down control signal through a fuse option or a switch of a switch. Device. The method of claim 20, The feedback means, First and second diode resistors connected in series between a supply terminal of the internal voltage and a second node for outputting the feedback voltage; Third and fourth diode resistors connected in series between the first node and the supply terminal of the ground voltage; Voltage discharge device characterized in that. The method of claim 21, The ratio adjusting means, A first switch connected between the connection node of the first and second diode resistors and the second node; And a second switch connected between the connection node of the third and fourth diode resistors and the supply terminal of the ground voltage. Voltage discharge device characterized in that. The method of claim 22, The pull-down control means, A level detector for detecting a level difference between the reference voltage and the feedback voltage and outputting first and second output signals; A control signal activation unit for activating the pull-down control signal in response to the first and second output signals of the level sensing unit; And a control signal deactivation unit for deactivating the pull-down control signal in response to deactivation of the drive signal. Voltage discharge device characterized in that. The method of claim 23, wherein The control signal activator, A first PMOS transistor having the first output signal as a gate input and having a supply terminal for an external voltage and a source-drain path at the first node; A second PMOS transistor having the second output signal as a gate input and having its source terminal connected to a supply terminal of the external voltage; A first NMOS transistor having a gate terminal and a source terminal thereof connected to a drain terminal of the second PMOS transistor, and a drain terminal connected to a supply terminal of a ground voltage; A second NMOS transistor connected to a gate end of the first NMOS transistor and having a drain-source path between the first node and the supply terminal of the ground voltage; Voltage discharge device characterized in that. The method of claim 24, The level adjusting means, A third PMOS transistor having a source-drain path between the supply terminal of the external voltage and the first node; A third NMOS transistor having a drain-source path between the first node and the supply terminal of the ground voltage; A first switch for switching between the gate terminal of the first PMOS transistor and the gate terminal of the third PMOS transistor; And a second switch for switching the gate terminal of the second NMOS transistor and the gate terminal of the third NMOS transistor. Voltage discharge device characterized in that. The method of claim 25, The level detection unit, And a differential amplifier which is activated in response to the activation of the drive signal, and outputs the first and second output signals by bringing the reference voltage and the feedback voltage to a differential input. Voltage discharge device characterized in that. The method of claim 26, The level detection unit, A current source transistor for supplying a bias voltage to the differential input transistor in response to the driving signal; A differential input transistor connected to the current source transistor and receiving the reference voltage and the feedback voltage differentially; And a loading unit connected to the differential input transistor for outputting the first and second output signals corresponding to the amount of current controlled by the differential input transistor. Voltage discharge device characterized in that. The method of claim 27, The loading unit, A fourth PMOS transistor having a voltage applied to a third node at which the first output signal is output as a gate input, and having a source-drain path between a supply terminal of the external voltage and a third node; A fifth PMOS transistor having a voltage applied to a fourth node at which the second output signal is output as a gate input, and having a source-drain path between a supply terminal of the external voltage and a fourth node; And the third and fourth nodes are connection nodes with the differential input transistors. The method of claim 28, The control signal deactivation unit, And an NMOS transistor having the inverted driving signal as a gate input and having a drain-source path between the first node and the supply terminal of the ground voltage. Voltage discharge device characterized in that. The method of claim 29, The pull-down driver, A NMOS transistor having a pull-down control signal as a gate input and having a drain-source path between the supply terminal of the internal voltage and the supply terminal of the ground voltage; Voltage discharge device characterized in that. A drive power line of the bit line sense amplifier; Internal voltage supply means for supplying an internal voltage; High voltage supply means for supplying an external voltage having a level higher than the internal voltage; A first driver for driving the driving power line with a voltage applied to a supply terminal of the external voltage in response to an external voltage-supply signal; A second driver for driving the driving power line with a voltage applied to a supply terminal of the internal voltage in response to an internal voltage supply signal; And A pull-down control unit configured to output a pull-down control signal by detecting a level difference between a voltage applied to the supply terminal of the internal voltage and a reference voltage in response to a driving signal activated together with the internal voltage-supply signal; A level adjusting unit for selectively connecting a pull-up resistor and a pull-down resistor to an output terminal of the level control unit to adjust a width and a speed of the level change of the pull-down control signal; Discharging means having a pull-down driver for driving down Internal power supply having a. The method of claim 31, wherein The level control unit, And selectively connecting the pull-up resistor and the pull-down resistor to an output terminal of the pull-down control signal through a fuse option or switching of a switch. A drive power line of the bit line sense amplifier; A first supply terminal of an internal voltage; A second supply terminal to which an external voltage having a level higher than the internal voltage is supplied; A first driver for driving the driving power line with a voltage applied to the second supply terminal in response to an external voltage-supply signal; A second driver for driving the driving power line with a voltage applied to the first supply terminal in response to an internal voltage supply signal; And A feedback voltage having a constant voltage ratio with respect to the voltage applied to the first supply terminal, the voltage feedback unit capable of adjusting the constant voltage ratio, and a reference in response to a driving signal activated together with the internal voltage-supply signal; Voltage discharging means including a pull-down driving unit for detecting a level difference between a voltage and the feedback voltage to pull-down the first supply terminal. Internal power supply having a. The method of claim 33, wherein The voltage feedback unit, A dividing unit for dividing the internal voltage at the predetermined voltage ratio to output the feedback voltage; It includes a ratio adjusting unit for adjusting the constant voltage ratio through the fuse option or switching of the switch Internal voltage supply, characterized in that. The method of claim 34, wherein The dividing unit, First and second diode resistors connected in series between the first supply terminal and a first node for outputting the feedback voltage; Third and fourth diode resistors connected in series between the first node and the supply terminal of the ground voltage; Internal voltage supply, characterized in that. 36. The method of claim 35 wherein The ratio adjusting unit, A first switch connected between the connection node of the first and second diode resistors and the first node; And a second switch connected between the connection node of the third and fourth diode resistors and the supply terminal of the ground voltage. Internal voltage generator, characterized in that.

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