KR100795916B1 - Semiconductor device, electro-optic device, and electronic device - Google Patents

Abstract

An object of the present invention is to provide a semiconductor device, an electro-optical device, and an electronic device having a small change in the characteristics of a transistor even when the substrate is curved (deformed).

And a semiconductor layer and first and second transistors 100 and 200 formed using the semiconductor layer, wherein the conductances of the first and second transistors are complementarily changed with respect to the curvature of the semiconductor layer. Even if the substrate is curved, it is possible to suppress the characteristic change of the semiconductor device due to the bending.

Semiconductor layer, transistor, gate, drain

Description

Semiconductor devices, electro-optical devices and electronic devices {SEMICONDUCTOR DEVICE, ELECTRO-OPTIC DEVICE, AND ELECTRONIC DEVICE}

1 is a perspective view for explaining a first embodiment.

2 is a plan view for explaining a first embodiment.

3 is a circuit diagram for explaining an equivalent circuit of the first embodiment.

Fig. 4 is a graph for explaining the characteristic change of the P-type transistor due to the flexure of the substrate.

Fig. 5 is a graph for explaining a characteristic change of an N-type transistor due to the flexure of the substrate.

6 is a circuit diagram illustrating a configuration of a transistor amplifier circuit.

7 is a graph illustrating a configuration of an example of operating characteristics of a transistor amplifier circuit.

8 is an explanatory diagram illustrating an example of configuring a semiconductor device using four transistors.

9 is a perspective view illustrating an example of a transistor having an L-shaped gate.

10 is a plan view for explaining an example of a transistor including an L-shaped gate.

11 is an explanatory diagram for explaining an example of a transistor including a ring-shaped gate.

12 is an explanatory diagram showing an equivalent circuit of a transistor having an annular gate.

13 is an explanatory diagram for explaining another example of a transistor having a ring-shaped gate.

14 is an explanatory diagram for explaining another example of a transistor having a ring-shaped gate.

15 is an explanatory diagram illustrating an example of a circuit pattern of an amplifier using the transistor of the present invention.

16 is a circuit diagram illustrating a configuration example of a regulator circuit.

FIG. 17 is a graph for explaining a change in the output voltage of a regulator with respect to a change in the channel length L direction of a transistor;

Fig. 18 is a graph for explaining a change in the output voltage of a regulator with respect to a change in the channel width W direction of a transistor.

Fig. 19 is an explanatory diagram for explaining an example of a circuit pattern (part) of a regulator using the transistor of the present invention.

20 is a circuit diagram illustrating a configuration example of a differential amplifier circuit.

Fig. 21 is a graph for explaining a characteristic change due to bending of a differential amplifier circuit board.

Fig. 22 is an explanatory diagram for explaining an example of a circuit pattern of a differential amplifier using the transistor of the present invention.

23 is an explanatory diagram illustrating an example of a plurality of substrates.

24 is an explanatory diagram illustrating an application example of an electronic device of the semiconductor device of the present invention.

25 is an explanatory diagram illustrating an application example of an electronic device of the semiconductor device of the present invention.

Explanation of symbols for the main parts of the drawings

11: substrate 100, 200, 300, 400: transistor

101, 201: gate 102, 202: drain

103, 104: Source S: Source

D: Drain G: Gate

L: Channel Length W: Channel Width

The present invention relates to a semiconductor device using a semiconductor element such as a transistor on a flexible substrate.

In recent years, flexible sheet-like display devices, such as flexible electronic devices and organic EL display devices, have been started. In such a display device, for example, an electronic circuit such as a pixel or a transistor is formed on a flexible substrate. As the transistor, semiconductors such as an amorphous silicon film, a polycrystalline silicon film, and a single crystal silicon film (see Patent Document 1) are used.

[Patent Document 1] Japanese Unexamined Patent Publication No. 9-312349

However, when the sheet-shaped display device is bent and used, for example, a transistor formed on a flexible substrate in a flat state is minutely deformed in accordance with the curvature of the substrate. It was found that the characteristics of the transistor were changed by this modification. If the transistor characteristics are changed, there is a possibility that the electronic circuit formed on the substrate may not operate correctly.

Therefore, an object of the present invention is to provide a semiconductor device, an electro-optical device, and an electronic device having a small change in the characteristics of a transistor even when the substrate is bent (deformed).

In order to achieve the above object, the semiconductor device of the present invention includes a semiconductor layer and first and second transistors formed using the semiconductor layer, and the curvature of the first and second transistors with respect to the curvature of the semiconductor layer. Each conductance changes complementarily.

According to such a structure, even if the board | substrate which formed the semiconductor device is curved, the characteristic change of the semiconductor device by the said curvature, for example, the characteristic of the drain voltage Id which flows between a source and a drain, and the applied voltage Vds between a source and a drain (Id -Vds characteristic) change can be suppressed. Thereby, for example, it is possible to arrange electronic circuits in the curved part of the board | substrate which electrically connects two units, the curved display body, etc., and the apparatus can be miniaturized easily. Here, the conductance (conductivity coefficient) g is expressed as g = ΔId / ΔVds.

Preferably, with respect to the curvature of the semiconductor layer, the channel region of the first transistor is stretched or compressed in its length L direction, and the channel region of the second transistor is stretched or compressed in its width W direction. .

As a result, the drain current increase and decrease of the first transistor due to the curvature of the semiconductor layer is canceled by the drain current increase and decrease of the second transistor due to the curvature of the semiconductor layer. Herein, the curvature of the semiconductor layer is different from the curvature of the semiconductor layer itself (for example, a silicon substrate thinned by polishing or the like), and a semiconductor layer (for example, silicon layer formation by CVD method, liquid silicon deposition, or the like) deposited on the substrate. Silicon layer formation by drying, etc.) is bent in accordance with the curvature of the substrate. The substrate is not limited to, for example, a so-called flexible substrate made of resin or the like. If the substrate is curved, a substrate polished thinly, a large substrate bent by its own weight, and the like are also included.

It can be seen that the drain current (absolute value) decreases when the channel region of the transistor is stretched in the length L direction (current flow direction / source / drain direction) by the curvature of the substrate, and the drain current increases when compressed. . Further, it was found that the curvature of the substrate causes the drain current to decrease when the channel region of the transistor is stretched in the width W direction (the width direction to the current path), and increases when the channel region of the transistor is compressed.

As one reason for this phenomenon, the channel region deformation of the transistor can be considered. The drain current Id of the transistor is proportional to the width W of its (effective) channel region and inversely proportional to the length L of the (effective) channel region. In other words, Id = g VD = (W / L) f (VD, VG). Where g is the conductance of the channel (transistor), VD is the drain voltage, VG is the gate voltage, and f is a function.

Preferably, the first and second transistors are arranged such that the extending directions of their gates cross each other. As a result, the channel width direction of the second transistor can be present in the channel length direction of the first transistor. It is possible to suppress the change in conductance by increasing or decreasing the channel region in the channel width direction of the second transistor in correspondence with the channel region in the channel length direction of the first transistor.

Preferably, the first and second transistors are connected in parallel, and the gates of both transistors are connected. As a result, the outputs of the first and second transistors are combined to cancel the level variation of the output due to the curvature.

Preferably, the first and second transistors are each formed by a plurality of transistors. As a result, a transistor with a larger output current in which the influence of curvature is compensated for is obtained.

Preferably, the configuration number of each of the first and second transistors or the shape and size of the channel region are different, and the degree of influence of the tension and compression in the channel length direction and the degree of influence of the tension and compression in the channel width direction. Allows you to adjust the difference. This makes it possible to more accurately cancel the influence on the curvature by the two groups of transistors.

Preferably, the semiconductor layer is a semiconductor layer formed by grinding a semiconductor layer or a semiconductor substrate deposited on a substrate and thinning it. For example, a semiconductor layer can be formed by polishing or etching a silicon substrate (wafer) forming a transistor from the back surface to form a semiconductor layer. Even in a silicon substrate, it can be curved by thinning it.

In addition, the semiconductor device of the present invention includes a semiconductor layer formed on a substrate, a gate electrode formed in a ring shape on the semiconductor layer through a gate insulating film, a channel region formed in a ring shape on the semiconductor layer overlapping the gate electrode, One source / drain region surrounding the channel region and the other source / drain region surrounded by the channel region are included. Here, the semiconductor layer formed on the substrate is made thin by thinning a semiconductor substrate (for example, a silicon substrate) by polishing or the like, but the semiconductor layer is formed on the flexible insulating resin substrate by the CVD method, the coating method, the vapor deposition method, or the like. And a thin semiconductor layer bonded to a flexible insulating substrate. The organic semiconductor material mentioned later may be used.

As a shape of an annular gate electrode, square shape, a circular shape, etc. are mentioned, for example. In the case of a quadrangle, the difference in influence between the longitudinal direction and the width direction of the channel can be adjusted by making the longitudinal side and the transverse side of the same shape different.

By setting it as such a structure, the gate electrode of several transistor can be made common.

The source / drain region is a region for injecting charge into the channel region, and is usually divided into a source region and a drain region with a channel region interposed therebetween. Current flows from the source region through the channel region to the drain region. However, the direction of the current flowing through the channel region such as the pixel transistor of the liquid crystal device may be reversed. When the direction of the current is reversed, the portion that was the drain region functions as the source region, and the portion that was the source region functions as the drain region. Therefore, in this specification, two parts which sandwich a channel region are generally called a source-drain region. When one part plays the function of the source region, the other part plays the function of the drain region, for example, both parts do not have the function of the source region at the same time.

In addition, the semiconductor device of the present invention includes a semiconductor layer formed on a substrate, a first gate electrode formed on the semiconductor layer through a first gate insulating film, and a first channel formed on the semiconductor layer under the first gate electrode. A region, first and second source / drain regions formed between the first channel region, a second gate electrode formed on the semiconductor layer through a second gate insulating film, and below the second gate electrode. A second channel region formed in the semiconductor layer and third and fourth source / drain regions formed with the second channel region interposed therebetween, and extending directions of the first and second channel regions intersect each other. The first and third source and drain regions are connected to each other, and the second and fourth source and drain regions are connected to each other.

With such a configuration, the longitudinal direction of the channel region of the first transistor formed on the flexible substrate and the width direction of the channel region of the second transistor can be aligned in the same direction. Thereby, the characteristic fluctuation | variation of the semiconductor device by the curvature and curvature of a board | substrate can be suppressed.

Preferably, further, a third gate electrode formed through a third gate insulating layer with respect to the semiconductor layer, a third channel region formed in the semiconductor layer overlapping the third gate electrode, and the third channel region. And fifth and sixth source and drain regions formed therebetween, and an extension direction of the third channel region intersects an extension direction of the first or second channel region, and the fifth source and drain region. The first and third source and drain regions are connected, and the sixth source and drain regions are connected to the second and fourth source and drain regions. This makes it possible to compensate for the difference by further using the third transistor even when the difference in the transistor characteristic change with respect to the curvature between the first and second transistors is large.

Preferably, the electro-optical device of the present invention includes the semiconductor device described above. Thereby, for example, it becomes possible to arrange | position an electronic circuit (semiconductor apparatus) in the curved part of the flexible board | substrate which makes the electrical connection of the wiring provided in the edge part of an image display panel. Thereby, for example, it becomes possible to obtain an image display device (LCD (liquid crystal panel), organic EL panel, etc.) of a narrow frame.

Preferably, the electronic device of the present invention includes the semiconductor device or the electro-optical device described above. This makes it possible to obtain a personal computer, a video camera, a portable information device, or the like having a smaller or narrower frame display device.

Preferably, in the semiconductor device described above, a transistor pair for suppressing characteristic variations due to curvature and a pattern on a substrate of an electronic circuit using the transistor pair are symmetrical. Thereby, it becomes possible to make the grade of curvature and curvature of a board | substrate uniform.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described, referring drawings.

First, the instrument of this invention is demonstrated. The inventor of this application thinned the board | substrate with which the transistor was formed, and gave flexibility, curved the said transistor, and observed the change of the transistor characteristic. The results are shown in FIGS. 4 and 5.

4 shows an example of drain current Id and drain voltage Vd characteristics (I-V characteristics) when the P-channel MOS transistor is bent to a bending radius R of 30 mm. In FIG. 4, a plot of white square dots shows I-V characteristics when the channel region of the MOS transistor is compressed in the channel width W direction by curvature of the substrate. The plot of the white triangular dot shows the I-V characteristic when the channel region is stretched in the channel length L direction by the curve. The plot of the white circular point shows the I-V characteristics of the MOS transistor in the absence of curvature. The plot of x points shows the I-V characteristics when the channel region of the MOS transistor is stretched in the channel width W direction due to the curvature of the substrate. The plot of the black circular point shows the I-V characteristic when the MOS transistor is compressed in the channel length L direction by the curvature of the substrate. In addition, a constant gate voltage Vgs = -3.3 [V] was applied to the gate of the MOS transistor.

From the graph of Fig. 4, when the tensile force acts in the width W direction of the channel region of the MOS transistor due to the curvature of the substrate, the drain current increases (absolute value) compared with the characteristic at the time of non-curvature. Even when the compressive force acts in the length L direction of the channel region due to the curvature of the substrate, the drain current increases.

Further, when the compressive force acts in the width W direction of the channel region of the MOS transistor due to the curvature of the substrate, the drain current decreases (absolute value). Even when the tensile force acts in the length L direction of the channel region due to the curvature of the substrate, the drain current decreases.

5 shows an example of the drain current Id and the drain voltage Vd characteristics (I-V characteristics) when the N-channel MOS transistor is bent at a bending radius R of 30 mm. Similarly to FIG. 4, also in FIG. 5, the plot of the white square point shows I-V characteristic in the case where the channel region of the MOS transistor is compressed in the channel width W direction by the curvature of the substrate. The plot of the white triangular dot shows the I-V characteristic when the channel region is stretched in the channel length L direction by the curve. The plot of the white circular point shows the I-V characteristics of the MOS transistor in the absence of curvature. The plot of x points shows the I-V characteristics when the channel region of the MOS transistor is stretched in the channel width W direction due to the curvature of the substrate. The plot of the black circular point shows the I-V characteristic when the MOS transistor is compressed in the channel length L direction by the curvature of the substrate. In addition, a constant gate voltage Vgs = 3.3 [V] was applied to the gate of the NMOS transistor.

From the graph of Fig. 5, when the tensile force acts in the width W direction of the channel region of the NMOS transistor due to the curvature of the substrate, the drain current increases as compared with the non-curvature. When the compressive force acts in the length L direction of the channel region due to the curvature of the substrate, the drain current increases.

Further, when the compressive force acts in the width W direction of the channel region of the MOS transistor due to the curvature of the substrate, the drain current decreases. When the tensile force acts in the length L direction of the channel region due to the curvature of the substrate, the drain current decreases.

As described above, it can be seen that when the MOS transistor is curved, a level shift occurs in the I-V characteristic. This level shift may cause a difference in driving current Id of about 20% at maximum.

Such a level shift of the MOS transistor due to the curvature of the substrate changes the operating point of the transistor circuit as described below.

6 shows an example of a source ground amplifier circuit of a MOS transistor. The input voltage Vin is applied to the gate G of the PMOS transistor MP, the circuit power supply Vdd (= 5V) is connected to the source S thereof, and the resistance R1 (= The circuit voltage Vss (= 0 V) is connected via 30 Hz). The output of this drain is a circuit output.

Fig. 7 shows the results of a circuit simulation of the input voltage Vin and the output voltage Vout characteristics of the circuit by the circuit simulator HSPICE (registered trademark). The solid line in Fig. 7 shows reference characteristics without curvature in the substrate, and when the gate bias voltage Vbp is 2.5 [V], 2.5 [V] is obtained for the output voltage Vout.

Next, when the substrate is bent so that the channel width W of the PMOS transistor is compressed or the channel length L is compressed, the output level is increased as shown by the dashed-dotted line in FIG. 7 (the characteristic curve is shifted to the right direction). The operating point (bias point) is shifted by level shifting. In addition, when the substrate is bent so that the channel width W of the PMOS transistor is compressed or the channel length L is tensioned, the output level is reduced (characteristic curve shifts leftward), as shown by the dashed-dotted line in FIG. The operating point moves by level shifting.

Therefore, when the substrate or the like on which the transistor is formed is curved, it is necessary to take into account the characteristic change of the transistor. In particular, when the transistor is disposed on a flexible wiring circuit board (FPC) or an IC card, the substrate and the like are curved, so consideration is necessary.

(Example 1)

1 to 3 show a first embodiment of a semiconductor device according to the present invention. 1 is a perspective view schematically illustrating a semiconductor device, FIG. 2 is a plan view, and FIG. 3 is an equivalent circuit diagram.

As shown in each figure, the semiconductor device 10 includes two transistors 100 and 200 as first and second transistors on one substrate 11. As will be described later, the substrate 10 is formed by forming a transistor by forming a semiconductor layer on a flexible insulating substrate such as plastic, or the CMP (chemical mechanical polishing) method on the back surface of the silicon substrate on which the transistor is formed. By grinding | polishing, for example, it is made into thickness about 10 micrometers, and to make it flexible. The transistor 100 includes a gate 101, a drain 102, a source 103, and a channel region is formed under the electrode of the gate 101. The transistor 200 includes a gate 201, a drain 202, and a source 203, and a channel region is formed under an electrode of the gate 201.

The transistors 100 and 200 are arranged so that their respective extending directions of the gates 101 and 201 are substantially perpendicular to each other. As a result, the center lines in the width W direction of the channel regions of both transistors or the center lines in the length L direction (not shown) intersect. Therefore, the channel length L direction of the transistor 200 exists in the channel width W direction of the transistor 100, and the channel width W direction of the transistor 200 exists in the channel length L direction of the transistor 100.

As shown in FIG. 3, the drains 102 and 202 of both transistors are electrically connected to each other on the substrate 11 or by wiring (not shown). Similarly, the sources 103 and 203 of both transistors are also electrically connected.

When the semiconductor device 10 configured as described above is curved in a convex shape in the z direction in the x direction (left and right direction in FIG. 1) of the substrate 11, the channel region of the transistor 100 is stretched in the width W direction. In addition, the channel region of the MOS transistor 200 is stretched in the length L direction.

As a result, the conductance g of the transistor 100 becomes (W + ΔW) / L equivalently, and increases from W / L to increase the drain current Id. Here, ΔW is an influence on the channel width due to curvature. On the other hand, in the transistor 200, the conductance g becomes equivalent to W / (L + ΔL) and decreases from W / L to decrease the drain current Id. DELTA L is an influence part to channel length by curvature.

In this way, the transistors 100 and 200 complementarily change the conductance g with respect to the convex curvature of the substrate 11. By using the MOS transistors 100 and 200 as pair transistors and combining both outputs, the MOS transistors 100 and 200 can be functioned as one transistor that is hardly subject to variations due to substrate curvature.

Further, when the substrate 11 is curved in a concave shape in the x direction and the z direction, the channel region of the MOS transistor 100 is compressed in the width W direction. In addition, the channel region of the MOS transistor 200 is compressed in the length L direction.

As a result, in the MOS transistor 100, the conductance g becomes equivalent to (W-ΔW) / L, and decreases from W / L to decrease the drain current Id. On the other hand, in the MOS transistor 200, the conductance g becomes equivalent to W / (L-ΔL), and increases from W / L to increase the drain current Id.

In this way, the transistors 100 and 200 complementarily change the conductance g with respect to the concave curvature of the substrate 11, respectively. By using the transistors 100 and 200 as pair transistors, and combining both outputs, the transistors 100 and 200 can function as one transistor that is hardly subject to variations due to substrate curvature.

In the first embodiment, the transistors 100 and 200 are substantially L-shaped, but may be T-shaped in order to impart the same curvature (curvature) to both transistors.

As described above, according to the semiconductor device of the first embodiment of the present invention, one transistor is constituted by the first and second transistors, the channel width of the first transistor exists in one curved direction of the substrate, and the curved Since the channel length of the second transistor is present in the direction, and the outputs of both transistors are synthesized to function as one transistor, it is necessary to cancel the change in transistor characteristics due to the curvature of the substrate to obtain a semiconductor device with less influence of curvature. It becomes possible.

(Example 2)

8 shows a second embodiment of the present invention. In FIG. 8, the same code | symbol is attached | subjected to the part corresponding to FIG. 2, and description of this part is abbreviate | omitted.

In this embodiment, four transistors are formed on the substrate 11. In other words, the transistors 300 and 400 are added to the above-described transistors 100 and 200. Four transistors are arranged on the substrate 11 so as to be cross-shaped.

By connecting four transistors in parallel, a semiconductor device with a larger output, which is less susceptible to the curvature of the substrate, can be obtained.

(Example 3)

9 shows a third embodiment of the present invention. 9, the same code | symbol is attached | subjected to the part corresponding to FIG. 1, and description of this part is abbreviate | omitted.

In this embodiment, two transistors 100 and 200 are formed on the substrate 11, and the gates of both transistors are composed of one L-type common gate.

Even in such a configuration, it becomes possible to obtain a semiconductor device which is hardly affected by the curvature of the substrate.

(Example 4)

10 shows a fourth embodiment of the present invention. 10, the same code | symbol is attached | subjected to the part corresponding to FIG. 1, and description of this part is abbreviate | omitted.

In the present embodiment, the two transistors 100 and 200 described above are integrally formed on the substrate 11. The gates of both transistors are composed of one L-type common gate, and drains 102 and sources 103 are formed on both sides of the gate 101, respectively.

Even in such a configuration, it becomes possible to obtain a semiconductor device which is hardly affected by the curvature of the substrate.

(Example 5)

11 and 12 show a fifth embodiment of the present invention. In FIG. 11 and FIG. 12, the same code | symbol is attached | subjected to the part corresponding to FIGS. 1-10, and description of this part is abbreviate | omitted.

In this embodiment, four transistors 100 to 400 are integrally formed on the substrate 11. The gate of each transistor is composed of one rectangular common gate 101, and a drain 102 is formed inside the annular gate 101. In addition, the source 103 is formed in a ring shape on the outer side of the annular gate 101.

Even in such a configuration, since the width direction of the channel of the transistors 100 and 300 and the length direction of the channel of the transistors 200 and 400 become the same direction, or the length direction of the channel of the transistors 100 and 300 and the transistor ( Since the width directions of the channels 200 and 400 are in the same direction, it is possible to obtain a semiconductor device that is less susceptible to the curvature of the substrate.

As shown in FIG. 12, the transistor using the annular gate shown in FIG. 11 can be represented as the semiconductor device 10 in which each gate, each source, and each drain of four transistors are commonly connected (parallel connection). By using four transistors, it becomes possible to obtain a larger drive current (drain current).

(Example 6)

13 shows a sixth embodiment of the present invention. In FIG. 13, the same code | symbol is attached | subjected to the part corresponding to FIG. 11, and description of this part is abbreviate | omitted.

In this embodiment, the semiconductor layer is formed on the substrate 11 in a cross pattern. Four transistors 100 to 400 are integrally formed on the substrate 11. The gates of the transistors are formed in a band shape on the semiconductor layer so as to form one common gate 101. The strip-shaped gate 101 is formed in a ring shape, and a drain 102 is formed inside the ring-shaped gate 101. Further, sources 103a to 103d are formed outside the annular gate 101.

The difference between the embodiment shown in FIG. 11 and the present embodiment is that, as in the embodiment shown in FIG. 9, four corner portions of the rectangular gate 101 are not used as transistors. This avoids the uncertainty (uncertainty of the current distribution) of the operation as the transistor in the above-described portion when the transistor is formed in the four corner portions of the gate 101.

Even in such a configuration, since the width direction of the channel of the transistors 100 and 300 and the length direction of the channel of the transistors 200 and 400 become the same direction, or the length direction of the channel of the transistors 100 and 300 and the transistor ( Since the width directions of the channels 200 and 400 are in the same direction, it is possible to obtain a semiconductor device that is less susceptible to the curvature of the substrate.

(Example 7)

14 shows a seventh embodiment of the present invention. In FIG. 14, the same code | symbol is attached | subjected to the part corresponding to FIG. 13, and description of this part is abbreviate | omitted.

Also in this embodiment, four transistors 100 to 400 are integrally formed on the substrate 11. The gate of each transistor is composed of one rectangular common gate 101, and a drain 102 is formed inside the annular gate 101. Further, sources 103a to 103d are formed outside the annular gate 101.

The difference between the embodiment shown in FIG. 13 and the present embodiment is that ion implantation is performed by using a mask in the region SEM of the rectangular semiconductor layer, and a high concentration impurity region is formed in the cross-shaped region shown by the dotted lines in FIG. 13. And the drains 102 are formed inside the annular gate 101 and sources 103a to 103d are formed outside the gate 101.

Thereby, similarly to the embodiment shown in FIG. 13, the channel region is not formed in the four corner portions of the rectangular gate 101. This avoids the uncertainty of the operation as the transistor at the four corner portions of the gate 101 (the uncertainty of the current distribution).

Even in such a configuration, since the width direction of the channel of the transistors 100 and 300 and the length direction of the channel of the transistors 200 and 400 become the same direction, or the length direction of the channel of the transistors 100 and 300 and the transistor ( Since the width directions of the channels 200 and 400 are in the same direction, it is possible to obtain a semiconductor device that is less susceptible to the curvature of the substrate.

(Example 8)

FIG. 15 shows an example of a circuit pattern by a multilayer wiring film when the amplifier circuit shown in FIG. 6 is composed of a transistor having a ring gate.

As shown in Fig. 15, a transistor according to the embodiment is disposed in the center, a dummy resistor not electrically connected to another on the left side of the transistor, and a resistor R1 on the right side of the transistor. Further, a power supply wiring Vdd extending in the left and right directions on the upper side of the transistor and a power supply wiring Vss extending in the left and right directions are disposed on the lower side.

The transistor has the above-described annular gate, and the input signal Vin is applied to the gate through the input signal wiring. On the annular source region outside the gate, two source wirings branched from the power supply wiring Vdd are arranged so as to surround the gate from both sides. The source wiring is connected to the source through a plurality of contact holes.

The drain located inside the gate is connected to the drain wiring through the plurality of contact holes and connected to one end of the resistor R1. The pattern of the resistor R1 is zigzag, and the other end thereof is connected to the power supply wiring Vss. The drain wiring is branched to supply the signal output Vout to a blocking circuit (not shown).

In this embodiment, since the pattern of the amplifying circuit using the transistor is substantially symmetrical, the curvature of the substrate tends to be uniform. As a result, improvement in the compensation accuracy of curvature in the transistor can be easily obtained.

(Example 9)

16 to 19 illustrate an example in which the transistor of the above-described embodiment is used for a regulator (constant voltage) circuit, and FIG. 16 is a circuit diagram thereof, and FIGS. 17 and 18 are graphs illustrating changes in output characteristics due to curvature of a substrate. 19 is a circuit pattern diagram illustrating a circuit pattern around a transistor.

As shown in FIG. 16, the regulator circuit is comprised by the level comparator CMP, PMOS transistor M6, resistor R1 (200 [kV]), R2 (250 [kV]), etc. As shown in FIG. The power source Vdd of 3.3 [V] is supplied to the source of the transistor M6 from the outside. This voltage is adjusted in the transistor M6 to which the voltage Vo is applied to the gate, and is output as the output voltage Vout from its drain. A part of the output voltage Vout is divided by the resistors R2 and R1 connected to the drain and fed back to the level comparator CMP as the comparison input voltage Vi. A comparison reference voltage Vref (for example, 0.89 [V]) is applied to the reference input of the level comparator CMP. The level comparator CMP compares the reference voltage Vref with the input voltage Vi, gives a comparison output Vo according to the level difference to the transistor M6, and maintains the output voltage Vout of the transistor M6 at a constant value.

In the case where the above-described regulator circuit is formed on a substrate and a conventional transistor which does not take measures against curvature of the substrate is used, the output voltage Vout of the regulator circuit is changed by the curvature of the substrate.

17 shows an example of output voltage and output current characteristics of the regulator circuit when the substrate is bent in the channel length L direction of the transistor. In Fig. 17, the characteristic shown by the solid line does not bend the substrate, the dashed line indicates the case where the channel of the transistor is compressed in the channel length direction, and the dashed line indicates the case where the channel of the transistor is tensioned in the channel length direction. Represent each.

When the channel of the transistor is compressed in the channel length direction, the output voltage level of the regulator circuit increases (shifts in the right direction in Fig. 17). When tensioned in the channel length direction, the output voltage level of the regulator circuit decreases (shift in the left direction in FIG. 17).

18 shows an example of output voltage and output current characteristics of the regulator circuit when the substrate is curved in the channel width W direction of the transistor. In Fig. 18, the characteristic shown by the solid line indicates that the substrate is not curved, the dashed line indicates the case where the channel of the transistor is stretched in the channel width direction, and the dashed line indicates the case where the channel of the transistor is compressed in the channel width direction. Represent each.

When the channel of the transistor is pulled in the channel width direction, the output voltage level of the regulator circuit increases (shift in the right direction in FIG. 18). When tensioned in the channel length direction, the output voltage level of the regulator circuit decreases (shift in the left direction in FIG. 18).

Thus, although the range in which a regulator circuit keeps an output voltage constant changes with curvature of a board | substrate, such a fault is avoided by using the transistor which implemented the above-mentioned curvature countermeasure.

Fig. 19 shows an example of a circuit pattern (near the transistor) in which the transistor M6 of the regulator circuit described above is constituted by a transistor having an annular gate for curvature. The dummy circuit DM is suitably inserted in such a manner that the circuit pattern is symmetrical. Thereby, it becomes possible to equalize the curvature degree (bending degree) of a board | substrate.

(Example 10)

20 to 22 illustrate an example of using the transistor of the above-described embodiment in a differential amplifier, where FIG. 20 is a circuit diagram, FIG. 21 is a graph illustrating a change in output characteristics due to curvature of a substrate, and FIG. 19 is a transistor. It is a circuit pattern diagram explaining the circuit pattern of the surrounding.

As shown in Fig. 20, the differential amplifier circuit is constituted by a constant current source transistor, a differential transistor pair, a current mirror circuit, and the like connected in series between a circuit power supply Vdd (e.g., 3.3 [V]) and Vss (ground potential). have.

The constant current source transistor is constituted by the P-type transistor M11, whose source is connected to the circuit power supply Vdd, and its drain is connected to the common connection point (source) of the differential transistor pair. The differential transistor pair is constituted by the P-type transistors M12 and M13. Each source of both transistors is commonly connected, and each drain is connected to the first and second current paths of the current mirror circuit, respectively. The signal inputs Vpin and Vnin are applied to the gates of both transistors, respectively.

The current mirror circuit is constituted by the N-type transistors M14 and M15. The source of the N-type transistor M14 is connected to the drain of the transistor M12 which is the first current path, and the source of the transistor M12 is connected to the drain of the transistor M13 which is the second current path. The gates of the N-type transistors M14 and M15 are commonly connected, and the gate and the source of the transistor M14 are connected to each other. The drains of the N-type transistors M14 and M15 are commonly connected and connected to the circuit power supply Vss. In this configuration, the drain of the transistor M13 is connected to the circuit output terminal, and the terminal is grounded through the capacitor CL (for example, 5 [pF]).

In such a configuration, for example, the circuit power supply Vdd is 3.3 [V], the circuit power supply Vss is grounded, the gate voltage Vb of the transistor M11 is 2.2 [V], and the differential input terminal on the transistor M13 side is a constant voltage of 1.65 [V]. ], When the voltage Vpin is applied to the differential input terminal of the transistor M12 side, the differential output characteristic as shown by the white circular plot in FIG. 21 can be obtained. However, when the substrate is bent, the characteristics of the transistor change, so that the output characteristics of the differential amplifier circuit change.

FIG. 21 shows an example of change in output voltage characteristics when local bending (curvature) is applied locally to the region indicated by the dotted line in FIG. 20, for example.

As shown in Fig. 21, when the substrate is bent and the transistor is compressed in the channel width W direction, the characteristic curve shifts to the right direction as shown by a plot of white square dots. When the transistor is compressed in the channel length L direction, the output is saturated as shown by the plot of the black circular point and does not function as a differential amplifier. In the case where the transistor is pulled in the channel width W direction, the level shifts to the left direction as shown by the plot of the x point and does not function as a differential amplifier. When the transistor is pulled in the channel length L direction, it is in a low output state as shown by a plot of triangle points, and does not function as a differential amplifier.

Such a defect is preferable because the influence of curvature of the substrate is eliminated by using the transistor of the above-described embodiment.

Fig. 22 shows an example in which a transistor according to the present invention is used for the transistors M11 to M15 of the above-described differential amplifier circuit in a circuit pattern.

Thus, by forming a circuit pattern symmetrically, the curvature of a board | substrate can become equal curvature. Further, as described above, by appropriately disposing a dummy pattern on the substrate, the degree of bending of the substrate can be made uniform by making the symmetry of the pattern and the occupancy rate of the pattern per unit area equal to each other. Thereby, the curvature countermeasure by the transistor of this application can also improve accuracy more.

(Example 11)

As shown in Fig. 23, the present invention can be applied to various transistors.

23A illustrates an example in which a bulk is used, and a source 512, a drain 513, a gate 514, a gate insulating film 515, and a sidewall spacer are formed on a semiconductor substrate (silicon substrate) 511. 516, a channel 517, and the like. Such a semiconductor substrate is subjected to CMP (chemical mechanical polishing) from the back side to make the substrate thin to obtain a substrate having flexibility.

FIG. 23B shows an example of a transistor of a top gate. For example, a semiconductor layer 532, a source 533, a drain 534, a gate 535, a gate insulating film 536, a channel 537, and the like are formed on a flexible insulating substrate 531 such as plastic. .

FIG. 23C shows an example of a transistor of a bottom gate. For example, a gate 535, a gate insulating film 536, a semiconductor layer 532, a source 533, a drain 534, a channel 537, and the like are formed on a flexible insulating substrate 531 such as plastic. .

In addition, the material of the semiconductor layer which comprises these transistors is not limited to inorganic materials, such as silicon, and may be organic materials. Examples of the organic semiconductor material include naphthalene, anthracene, tetracene, pentacene, hexacene, phthalocyanine, perylene, hydrazone, triphenylmethane, diphenylmethane, stilbene, arylvinyl, pyrazoline, triphenylamine, Low molecular weight organic semiconductor materials such as triarylamine, phthalocyanine or derivatives thereof, poly-N-vinylcarbazole, polyvinylpyrene, polyvinylanthracene, polythiophene, polyhexylthiophene, poly (p-phenylenevinyl) Ethylene), polyethylenevinylene, polyarylamine, pyreneformaldehyde resin, ethylcarbazoleformaldehyde resin, fluorenebithiophene copolymer, fluorenearylamine copolymer or derivatives thereof. These can be used 1 type or in combination or 2 or more types of these. Alternatively, oligomers containing thiophene, triphenylamine, naphthalene, perylene, fluorene and the like can be used.

As described above, it is possible to provide a semiconductor device resistant to bending by using the transistor according to the embodiment of the present invention.

(Electro-optical devices, electronic equipment)

The semiconductor device 10 as described above can be integrally formed with the electro-optical device 1 such as a liquid crystal device, an organic EL device, and an electrophoretic device. The electronic device of the present invention including the electro-optical device 1 will be described.

24 is a diagram illustrating an example of an electronic apparatus to which the above-described electro-optical device 1 can be applied. FIG. 24A illustrates an application example to a mobile phone. The mobile phone 630 includes an antenna unit 631, a voice output unit 632, a voice input unit 633, an operation unit 634, and the present invention. The electro-optical device 1 is provided. In this way, the electro-optical device according to the present invention can be used also as a display portion.

24B shows an application example to a portable electronic book, and the electronic book 750 includes a dial operation unit 751, a button operation unit 752, and an electro-optical device 1 according to the present invention.

FIG. 25A shows an application example to an image display device, and the pixel display device 800 includes the electro-optical device 1 according to the present invention. In addition, the electro-optical device 1 according to the present invention can be similarly applied to a monitor device used for a personal computer or the like.

FIG. 25B shows an application example to a roll-up type image display device (TV, etc.), and the roll-up still picture display device 910 includes the electro-optical device 1 according to the present invention. have.

As mentioned above, although the semiconductor device, the electro-optical device, and the electronic device of the present invention have been described, the present invention is not limited thereto, and the configuration of each part is of any configuration having the same function. It can be substituted. In addition, other arbitrary structures may be added to the present invention. In addition, this invention may combine the arbitrary 2 or more structure (characteristics) of each said embodiment.

As described above, according to the present invention, a semiconductor device, an electro-optical device, and an electronic device having a small change in characteristics of a transistor can be provided even when the substrate is bent (deformed).

Claims (11)

A semiconductor layer, First and second transistors formed using the semiconductor layer, A semiconductor device in which respective conductances of the first and second transistors change complementarily with respect to curvature of the semiconductor layer. The method of claim 1, With respect to the curvature of the semiconductor layer, the channel region of the first transistor is stretched or compressed in its longitudinal direction, and the channel region of the second transistor is stretched or compressed in its width direction. The method according to claim 1 or 2, And the first and second transistors are arranged such that the extending directions of their gates cross each other. The method of claim 1, And the first and second transistors are connected in parallel, and gates of both transistors are connected to each other. The method of claim 1, And the first and second transistors are each formed by a plurality of transistors. The method of claim 1, The semiconductor device is a semiconductor device which is a semiconductor layer formed by grinding a semiconductor layer or a semiconductor substrate deposited on a flexible substrate to form a thin film. A semiconductor layer formed on the substrate, A gate electrode formed in a ring shape on the semiconductor layer through a gate insulating film; A channel region formed in a ring shape in the semiconductor layer overlapping the gate electrode; One source / drain region surrounding the channel region; A semiconductor device comprising the other source / drain region surrounded by the channel region. A semiconductor layer formed on the substrate, A first gate electrode formed on the semiconductor layer through a first gate insulating film; A first channel region formed in the semiconductor layer under the first gate electrode; First and second source and drain regions formed with the first channel region interposed therebetween, A second gate electrode formed on the semiconductor layer through a second gate insulating film; A second channel region formed in the semiconductor layer under the second gate electrode; Third and fourth source and drain regions formed with the second channel region interposed therebetween, The extending direction of the said 1st and 2nd channel area | region cross | intersects, the said 1st and 3rd source / drain area | region are mutually connected, and the said 2nd and 4th source / drain area | region are mutually connected. The method of claim 8, A third gate electrode formed on the semiconductor layer through a third gate insulating film; A third channel region formed in the semiconductor layer overlapping the third gate electrode; Further comprising fifth and sixth source / drain regions formed between the third channel regions, The extension direction of the third channel region crosses the extension direction of the first or second channel region, and the fifth source and drain regions are connected to the first and third source and drain regions, and the sixth source A semiconductor device in which a drain region is connected with said second and fourth source and drain regions. An electro-optical device comprising the semiconductor device according to any one of claims 1 to 7. The electronic device provided with the semiconductor device of any one of Claims 1-7.

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