KR100794947B1 - Memory testing equipment - Google Patents

Abstract

assignment

A memory inspection apparatus capable of performing address superimposition processing of inspection results in an inspection mode having a different data width without using software processing.

Resolution

A memory inspection apparatus for inspecting a DUT having a different address and data read structure according to a different data width, wherein a storage location for fail data of a fail data is arbitrarily arranged according to an address and a check mode designation signal given to the DUT. And a data storage control means for controlling the data storage control means. The data storage control means includes means for rearranging addresses in accordance with the inspection mode of the DUT, and failing from the rearranged addresses for each inspection mode of the DUT and for each region of the DUT. Means for selecting an address for determining storage allocation of data.

Failed Memory, Memory Check

Description

Memory Test Device {MEMORY TESTING EQUIPMENT}

1 is a block diagram illustrating an embodiment of the invention.

FIG. 2 is a specific circuit example of FIG. 1. FIG.

3 shows a different test mode.

4 is another specific circuit example of FIG.

5 is an example of storage allocation of fail data in inspection mode 1. FIG.

6 is an example of storage allocation of fail data in inspection mode 2. FIG.

FIG. 7 is another specific circuit diagram of FIG. 1. FIG.

8 is a block diagram showing an example of a conventional memory test apparatus.

9 is a block diagram illustrating an example of a fail detection device.

10 is a conceptual diagram of inspection according to a data width of 16 bits.

11 is a conceptual diagram of inspection according to an 8-bit data width.

* Description of the sign *

6: fail memory 8: address conversion unit

9: address bit selector 10: check mode designation

11: check mode selector 12: data enable bit storage memory

13: Data Validation Bit Selector 14: Data Gate

15: data selector 16: test mode selector

17: inspection mode setting unit 18 to 27, 29 to 42: selector

28: fail data allocation unit 43: address rearrangement unit

[Patent Document 1] Japanese Unexamined Patent Publication No. 2002-367396

The present invention relates to a memory test apparatus, and more particularly, to storage control of fail data for a fail memory.

In recent semiconductor memories, a plurality of spare memory cells (hereinafter referred to as spare cells) are formed on the premise that generation of some defective memory cells in the manufacturing process is unavoidable due to high integration. When a defective cell (hereinafter referred to as a fail cell) is detected by a test by the memory inspection apparatus, a predetermined pattern in the semiconductor memory under test (hereinafter referred to as a DUT) is cut by a laser to spare the fail cell. Move it to the cell. Accordingly, the fail cell can be saved, and the defect of the DUT resulting from the fail cell can be saved. The data necessary for such defect repair is created in the redundancy computing device.

In the redundancy arithmetic unit, redundancy arithmetic processing for saving the fail cell is performed based on the fail information obtained from the DUT. Here, the measurement of the DUT based on the redundancy calculation is called redundancy measurement.

The redundancy calculation is normally performed according to an algorithm based on predetermined regular processing by a redundancy calculation dedicated CPU formed in the memory test apparatus.

When a fail cell is detected from the DUT, it is determined whether all fail can be repaired by combining and assigning a column spare cell and a row spare cell to each of the detected fail cells, and if it is determined that the rescue is possible, the allocated replacement address information. Is output to the control unit of the memory test apparatus.

8 is a block diagram illustrating an example of a conventional memory test apparatus having a redundancy measurement function described in Patent Document 1. FIG. The memory test apparatus 1 is comprised of the fail detection apparatus 2, the redundancy calculating apparatus 3, and the control part 4. As shown in FIG.

The fail detection device 2 detects a fail cell of a memory cell included in the DUT 5, writes the detected fail data to the fail memory 6 as shown in FIG. 9, and then via the buffer memory 7. It is sent to the redundancy arithmetic unit 3.

The redundancy arithmetic unit 3 prepares data necessary for the defect relief of the DUT 5 based on the fail data sent from the fail detection apparatus 2, and sends it to the control unit 4. In addition, the DUT 5 incorporates a spare cell for repairing defects.

The redundancy arithmetic apparatus 3 is comprised by the computer, for example, and the function is implement | achieved by this computer executing the redundancy calculation program loaded.

The control unit 4 performs redundancy measurement using the data sent from the redundancy calculating unit 3.

By the way, during the inspection of the DUT 5, a combination of a plurality of data widths, for example, 2 bits, 4 bits, 8 bits, 16 bits, and the like is appropriately performed. The inspection results in these bit widths are recorded so as to overlap each bit position of the common fail memory 21 corresponding to the bit pattern of the DUT.

10 is a conceptual diagram of inspection by a data width of 16 bits. In Fig. 10, checks are performed in accordance with the address direction at data widths of 16 bits from 0 to 15, and these check results are written to the fail memory having the same bit pattern as the DUT.

11 is a conceptual diagram of inspection by 8-bit data width. In Fig. 11, checks are performed in accordance with the address direction at 8-bit data widths from 0 to 7, and these check results are also written to the fail memory having the same bit pattern as the DUT. When the data width is 8 bits, the address depth is twice as large as when the data width is 8 bits, but when writing to the fail memory, since the same DUT is used, the same bit position as the test result of the 16-bit data width is obtained. You should nest as much as possible.

Therefore, in the conventional memory inspection apparatus, address superimposition processing of inspection results in different inspection modes such as these 16-bit data widths and 8-bit data widths has been performed in software.

However, there has been a problem that the execution time of the software process for superimposing the addresses of the inspection results in these different inspection modes becomes an increase factor of the inspection time.

SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional problem, and an object thereof is to provide a memory inspection apparatus capable of performing address overlap processing of inspection results in an inspection mode having a different data width without using software processing.

Means to solve the problem

In order to achieve such a problem, the invention of claim 1,

A memory test apparatus for inspecting a DUT having a different address and data read structure according to a test mode having a different data width,

A data storage control means for controlling the storage position of the fail data for the fail memory can be arbitrarily arranged in accordance with the address and the check mode designation signal given to the DUT.

The invention according to claim 2, wherein in the memory test apparatus according to claim 1,

The data storage control means,

And a data selector for selecting data to be written to the fail memory according to the test mode, and an address bit selector for selecting bits for validating data from the address according to the test mode.

The invention according to claim 3, wherein in the memory test apparatus according to claim 1,

The data storage control means,

Means for rearranging addresses according to the check mode of the DUT,

And means for selecting an address for determining a storage allocation of fail data for each inspection mode of the DUT and for each region of the DUT from the rearranged addresses.

The invention according to claim 4, wherein in the memory test apparatus according to claim 2,

The data storage control means,

Means for rearranging addresses according to the check mode of the DUT,

And means for selecting an address for determining a storage allocation of fail data for each inspection mode of the DUT and for each region of the DUT from the rearranged addresses.

Best Mode for Carrying Out the Invention

EMBODIMENT OF THE INVENTION Hereinafter, this invention is demonstrated using FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention.

The address conversion section 8 converts the bit width of the address ADRS output from the fail detection device (not shown) to match the address width of the fail memory 6.

The address bit selector 9 performs a fail memory in accordance with the test mode specified by the test mode designation unit 10 via the test mode selector 11 from the address ADRS output from a fail detection device (not shown). (6) An address of the data validation bit storage memory 12 in which data validation bits for selectively validating data to be input into the data is stored is selected. For example, when storing 32 sets of data enable bits in the fail memory 6, 5 bits are selected.

The bit selected by the address bit selector 9 becomes the address of the data validating bit storage memory 12 formed for each test mode in accordance with the test mode specified by the test mode designation unit 10.

The data validation bits stored in the data validation bit storage memory 12 depend on the inspection mode specified by the inspection mode designation section 10 in the data validation bit selection section 13 and the address selected by the address bit selection section 9. The bits stored in the predetermined memory are selected and input to one input terminal of the data gate 14.

The data selector 15 outputs the fail data DATA output from the fail detection device (not shown) according to the inspection mode specified by the inspection mode designation unit 10 via the inspection mode selection unit 16. Select the data to be entered into the fail memory (6). In FIG. 1, the example which selects 48-bit data and 32-bit data and inputs it to the other input terminal of the data gate 14 is shown.

The test mode setting unit 17 outputs a mode setting signal corresponding to each test mode to the test mode selecting units 11 and 16.

By such a configuration, an address suitable for the address width of the fail memory 6 is input to the address terminal of the fail memory 6 via the address conversion unit 8. On the other hand, data corresponding to each test mode is selectively input to the data terminal of the fail memory 6 via the data gate 14.

Accordingly, in the case of examining a DUT having a different address and data reading structure depending on the test mode, any specific bit on the DUT is read at a different address bit position according to each test mode, and writing to the fail memory 6 is performed. At the time of writing, the data is overwritten at the same bit position.

Therefore, the superimposition process by software like the conventional one becomes unnecessary, and the inspection time can be shortened significantly.

In the above embodiment, the example in which the check data width of the DUT is set to 8 bits and 16 bits has been described. However, the present invention is not limited to these examples, and a plurality of bits including 1 bit may be appropriately combined.

FIG. 2 is a specific circuit example of FIG. 1, and the same reference numerals are given to parts common to FIG. In Fig. 2, the selector 18 performs rearrangement so that the partition bits of the main region, the X spare region, the Y spare region, and the XY spare region are regularly arranged with respect to the X / Y address of the input DUT. .

The selector 19 selects the address bits corresponding to each of the main area, the X spare area, the Y spare area, and the XY spare area from the address output rearranged by the selector 18, and selects the selected address bits into a fail memory. Output to (6) and selector (24).

The selector 20 selects an effective address in the main area from the address output rearranged by the selector 18, and outputs the selected address to the selector 24.

The selector 21 selects an effective address in the X spare area from the address output rearranged by the selector 18, and outputs the selected address to the selector 24.

The selector 22 selects an effective address in the Y spare area from the address output rearranged by the selector 18, and outputs the selected address to the selector 24.

The selector 23 selects an effective address in the XY spare area from the address output rearranged by the selector 18, and outputs the selected address to the selector 24.

The selector 24 selects an effective address of each area selected by the selectors 20 to 23 based on the address bits corresponding to each area partition selected by the selector 19, and inputs the address to the fail memory 6 as an address. do. These selectors 19 to 24 constitute the address conversion section 8 in FIG.

The selector 25 selects an address for determining allocation of a fail bit number in one mode from the address output rearranged by the selector 18, and outputs the selected address to the selector 27.

The selector 26 selects an address that determines allocation of a fail bit number in the other mode from the address output rearranged by the selector 18, and outputs the selected address to the selector 27.

The selector 27 selects one of the addresses selected by the selectors 25 and 26 based on the mode designation signal, and inputs it to the fail data allocating unit 28 as an allocation decision address.

The fail data allocation unit 28 also inputs fail data of the DUT. The fail data allocating unit 28 determines the storage allocation of the fail data of the input DUT with reference to the address input from the selector 27, and the fail memory 6 as fail data to be stored in the fail memory 6. Output to The fail data allocating unit 28 includes a data validating bit storage memory 12, a data validating bit selecting unit 13, a data gate 14, and a data selecting unit 15 in FIG.

By the way, in the DUT having two or more test modes as shown in FIG. 3, when the address indicating the partition of each area is different in each test mode, the circuit configuration of FIG. 2 performs the test due to the following two factors. Can not. In addition, in the example of FIG. 3, (a) is the inspection mode 1 and the area switching address is set to (X3, Y2), and (b) is the inspection mode 2 and the area switching address is set to (X4, Y4). .

1) In order to switch the output of the selectors 20 to 23, it is necessary to make the address output from the selector 24 common in each test mode. This is for storing the main / spar area in the structure of the fail memory 6 in each physically different memory.

2) The selectors 25 and 26 are not prepared separately in each area.

FIG. 4 is another specific circuit example of FIG. 1, in which a DUT having two or more inspection modes as shown in FIG. 3 can be inspected, and the same reference numerals are given to parts common to FIG. 2.

In Fig. 4, the selectors 29 and 30 have the same arrangement of address bits indicating the division of the main area, the X spare area, the Y spare area and the XY spare area with respect to the X / Y address of the input DUT. The rearrangement process in the device test mode allocated to each is performed as much as possible, and the rearranged address is output to the selector 31.

The selector 31 selects any one of the addresses rearranged by the selectors 29 and 30 based on the mode designation signal, and is input to the selectors 19 to 26 connected to the rear ends.

The selector 19 selects the same area switch address bits as in Fig. 2, and the selectors 20 to 24 perform the same address conversion processing as in Fig. 2 and input them to the fail memory 6 as addresses.

The selectors 32 to 35 and the selectors 37 to 40 each have an address for determining the storage allocation of the input DUT from the X / Y address of the input DUT and the main area, the X spare area and the Y spare area, for each test mode. Select individually for each XY spare area.

The selector 36 and the selector 41 are the main area and the X spare area of the DUT selected by the selectors 32 to 35 and the selectors 37 to 40 based on the area switch address bits selected by the selector 19. And an address for determining the storage allocation for the fail memory 6 of the fail data in the Y spare area and the XY spare area.

The selector 42 switches the output of the selector 36 and the selector 41 based on the mode designation signal.

As in FIG. 2, the fail data allocating unit 28 determines storage allocation of fail data of the input DUT with reference to an address input from the selector 42 and stores the fail data as fail data to be stored in the fail memory 6. Output to the fail memory 6.

In the configuration of Fig. 2, the inspection could not be performed when the address bits representing the divisions of the respective areas were different in the respective device inspection modes. This is because in the structure of the fail memory 6, in order to store the main area, the X spare area, the Y spare area and the XY spare area in physically different memories, respectively, the address input to the selector 19 is always the same regardless of the check mode. It is based on the need. That is, by switching the selector 19 for each test mode, the address input to the selector 19 changes for each test mode, and the allocation to each area of the area switch address bits selected by the selector 19 is changed.

In contrast, in Fig. 4, the address rearrangement unit is constituted by the selectors 29 to 31, and the addresses are rearranged so that the address bits indicating the partition of the area selected by the selector 19 are the same for each test mode. It is possible to cope with the inspection of the DUT having a plurality of inspection modes as shown in Fig. 3, in which the address bits indicating the partition of the region are not switched without changing the selector 19 for each inspection mode.

The setting example of FIG. 4 in the inspection mode 1 shown in FIG. 3 is demonstrated.

1) The selector 29 rearranges the input address bits as follows.

(MSB) {X3, Y2, Y1, Y0, X2, X1, X0} (LSB)

Subsequently, the arrangement of the address bits is referred to as {A7, A6, A5, A4, A3, A2, A1, A0}.

Selector 29: {A7, A6, A5, A4, A3, A2, A1, A0} = {X3, Y2, Y1, Y0, X2, X1, X0}

2) When the inspection mode 1 is selected, the selector 31 is selected by the selector 31 by the mode designation signal.

3) The selectors 20 to 23 determine the allocation of the physical address of the selector 29 and the fail memory in each area.

   Main area: (A5, A4, A3, A2, A1, A0)

   X spare area: (A7, A6, A4, A3, A1, A0)

   Y spare area: (A7, A6, A3, A2, A1, A0)

   XY spare area: (A7, A6, LOW, A3, A1, A0)

4) The selector 29 selects the partitioned address bits of each area.

   X address: A7

   Y address: A6

5) The selectors 32 to 35 select respective addresses for determining storage allocation of fail data in each area in the inspection mode 1 of the DUT.

   Main area: (X0)

   X spare area: (X0)

   Y spare area: (X0)

   XY spare area: (X0)

6) The fail data allocating unit 28 determines the storage allocation of fail data for the fail memory 6 in the test mode 1. For example, if the bit width of the fail memory 6 is assumed to be 16, allocation is performed as shown in FIG.

Next, the setting example of FIG. 4 in the inspection mode 2 shown in FIG. 3 is demonstrated.

7) The selector 29 rearranges the input address bits as follows.

(MSB) {X4, Y4, Y3, Y2, Y1, Y0, X3, X2, X1, X0} (LSB)

Subsequently, the arrangement of the address bits is referred to as {A7, A6, A5, A4, A3, A2, A1, A0}.

Selector 29: {A9, A8, A7, A6, A5, A4, A3, A2, A1, A0} = {X4, Y4, Y3, Y2, Y1, Y0, X3, X2, X1, X0}

8) When the inspection mode 2 is selected, the selector 29 is selected by the selector 31 by the mode designation signal.

9) The selectors 20 to 23 determine the allocation of the physical address of the selector 29 and the fail memory in each area.

   Main area: (A5, A4, A3, A2, A1, A0)

   X spare area: (A7, A6, A4, A3, A1, A0)

   Y spare area: (A7, A6, A3, A2, A1, A0)

   XY spare area: (A7, A6, LOW, A3, A1, A0)

10) The selector 29 selects the address bits of the partition of each area.

   X address: A7

   Y address: A6

11) The selectors 32 to 35 select respective addresses for determining storage allocation of fail data of each area in the DUT's inspection mode 2.

   Main area: (Y3, Y2, X3, X0)

   X spare area: (Y3, Y2, X2, X0)

   Y spare area: (Y2, Y1, X3, X0)

   XY spare area: (Y2, Y1, X2, X0)

12) The fail data allocating unit 28 determines storage allocation of fail data for the fail memory 6 in the test mode 2. For example, when it is determined that the bit width of the fail memory 6 is 16, allocation is performed as shown in FIG.

In addition, the selector 30 and the selectors 37 to 41 in FIG. 4 can be omitted by determining at the start of fail data input without switching the inspection mode of the DUT during input of fail data.

In addition, when switching the DUT inspection mode can be arbitrarily performed during the input of the fail data, the selector system and the fail data allocating unit 28 constituting the address rearrangement unit are input according to the number of the switching inspection modes. The selector system for determining an address may be added. For example, when there are three types of inspection modes of the DUT, three selectors input to the selector 31 constituting the address rearrangement unit of FIG. 4 are determined, and an address input to the fail data allocating unit 28 is determined. The combination of the four selectors and one selector (32 to 36 and 37 to 41) input to the selector 42 to be used may also be three.

In addition, the storage bit width per address of the fail memory 6 is fixed, limiting the range of the number of IOs in the inspection mode of the DUT (for example, 2 bits / 4 bits / 8 bits), If the addresses for determining storage allocation of fail data of the DUT are the same, the circuit of FIG. 4 may be configured as shown in FIG.

In Fig. 7, the address rearrangement 43 receives inputs from the selector 24 and the selector 27 according to the number of IOs in the check mode of the DUT and the bit width of the fail memory 6. The address rearrangement unit 43 selects and rearranges these addresses and outputs them to the fail data allocation unit 28. The fail data allocating unit 28 determines storage allocation of fail data for the fail memory 6.

For example, the rearrangement when the bit width of the fail memory 6 is 1, the number of IOs in the test mode 1 is 8 and the number of IOs in the test mode 2 is 16 is as follows. Here, since the bit width is 16, the address for determining storage allocation of fail data is at most 4 bits.

The address output from the address rearranging unit 43 that determines storage allocation of fail data in the test mode 1 may be 1 bit because the bit width of the fail memory is 16 and the number of IOs in the test mode 1 is 8, and the selector (24) is used. ), The LSB1 bit of the address outputted from "

The address output from the address rearrangement unit 43 that determines storage allocation of fail data in the test mode 2 is 4 bits because the bit width of the fail memory is 16 and the number of IOs in the test mode 2 is 1. Therefore, the LSB1 bit of the address output from the selector 24 is selected to be the LSB of the address output from the address rearrangement unit 43, and the remaining three bits allocate an address output from the selector 27.

As described above, according to the present invention, it is possible to provide a memory inspection apparatus capable of performing an overlapping process of an address on a fail memory of inspection results in an inspection mode having a different data width without using software processing.

In this way, an address superimposition process on the fail memory of the inspection result in the inspection mode having a different data width can be performed without using software processing.

Claims (4)

A memory test apparatus for inspecting a DUT having a different address and data read structure according to a test mode having a different data width, And a data storage control means for controlling the storage position of the fail data to be arbitrarily arranged in accordance with an address and a test mode designation signal given to the DUT. The method of claim 1, The data storage control means, And a data selector for selecting data to be written to the fail memory according to the test mode, and an address bit selector for selecting bits for validating data from the address according to the test mode. The method of claim 1, The data storage control means, Means for rearranging addresses according to the check mode of the DUT, And means for selecting from the rearranged addresses an address for determining storage allocation of fail data for each inspection mode of the DUT and for each region of the DUT. The method of claim 2, The data storage control means, Means for rearranging addresses according to the check mode of the DUT, And means for selecting from the rearranged addresses an address for determining storage allocation of fail data for each inspection mode of the DUT and for each region of the DUT.

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