JP2001006388A - Semiconductor memory with built-in redundant circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory with built-in redundant circuit which decreases capital investment and cost necessary for relieving defectives, and also shortens an examination time. SOLUTION: As a circuit for relief processing by detecting a defective part and replacing it with a redundant circuit, this device comprises therein a test controller 33, an APG(Algorithmic Pattern Generator) 32, a replacement line selecting circuit 31a, a row and column spare part 11, 21, a row and column replacing circuit 12, 22, a row line and column line data reading circuit 13, 14, a row line and column line comparison circuit 14, 24, a row and column defective counter 15, 25, a row and column defective number storing register 16, 26, and a replacement circuit 41. Thus, the device with defects can be relieved only by inputting a simple signal such as an external trigger to the test controller.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a device having a built-in redundancy circuit for relieving a defect in a main body cell.

[0002]

2. Description of the Related Art In recent years, as the capacity of a semiconductor memory device has been increased, it has been widely practiced to improve the yield by replacing a defective portion of a main body cell with a built-in redundant circuit. Conventionally, when repairing a defective part, a semiconductor memory device is tested using a semiconductor test device, the obtained test result is stored in a fail memory in the test device, and how the test device is used to relieve The rescue information is generated by determining whether to perform the remedy. Then, using the obtained rescue information, a fuse for replacing a defective portion with a redundant circuit is blown by a laser rescue device.

[0003]

However, as the capacity of the semiconductor memory device further increases, a large amount of expensive semiconductor test equipment and laser rescue equipment are required, and the capital investment becomes enormous. In addition, when the circuit configuration of the semiconductor memory device becomes complicated with the increase in capacity, the time required for the test and the repair processing also increases.

SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a semiconductor memory device with a built-in redundant circuit, which can reduce the capital investment and cost required for repairing a defect and can shorten the test time.

[0005]

According to the present invention, there is provided a semiconductor memory device with a built-in redundant circuit, comprising: a test circuit for generating a signal necessary for processing for replacing a defective portion of the main body cell with the redundant circuit;
A row line and column line data read circuit for reading data stored in the main body cell in units of row lines or column lines, and data read by the row line and column line data read circuit;
A low-line and column-line comparator for comparing the expected value included in the signal generated by the test circuit with a unit other than the line for which the replacement destination is set and determining whether or not the line is defective, A row and column failure counter that counts the number of failures determined by the row and column line comparators on a row and column line basis, and a row and column failure given the number of failures counted by the row and column failure counter A row and column defect number storage register that stores a line as a unit, and a non-zero row line or a column line in which the number of defects stored in the row and column defect number storage register is a row line or a column line of the redundant circuit. A replacement line selection circuit for generating a replacement combination; and And row and column permutation circuit for storing the replaced destination address the test circuit is performed for each row line and column line is temporarily set using a combination,
According to the replacement destination address stored in the replacement circuit,
A replacement circuit for replacing a defective portion of the main body cell with the redundant circuit.

Here, the test circuit includes a pattern generator for generating a test vector necessary for reading data from the main body cell, and a trigger signal supplied from the outside, the pattern generator, the row line, and the column. A line data readout circuit, a row and column line comparator, a row and column failure counter, a row and column failure count storage register, a row and column replacement circuit, and a control signal for controlling operations of the replacement circuit. And a test controller.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration of a semiconductor memory device having a built-in redundant circuit according to the first embodiment. The device according to the present embodiment has the following features.

(1) A test circuit is built in.

(2) For the purpose of testing, data is read from the main body cell in units of row lines or column lines.

(3) The read data is compared with an expected value to judge whether or not the data is defective, the number of defects is counted, and the count is stored in a register.

(4) According to the number of stored defects, repair is performed in units of row lines or column lines.

The present apparatus having such features includes a main body cell 10, a row spare section 11, and a column spare section 21, similarly to an apparatus having a normal redundant circuit.

Here, the main body cell 10 is a memory cell array in which memory cells are arranged in a matrix, and may include a defective portion. The row spare section 11 has at least one row of redundant circuits for replacing a defective portion included in the main body cell 10 with a row line as a unit. The row replacement circuit 12 replaces a defective portion with the row spare unit 11 according to the decoder address information written in the replacement circuit 41 as described later.

The column spare unit 21 includes one redundant circuit for replacing a defective portion in the main body cell 10 on a column line basis.
More than rows. The column replacement circuit 22 is a circuit that replaces a defective portion with the column spare unit 11 according to the decoder address information written in the replacement circuit 41.

Further, the present apparatus automatically and optimally performs the process of replacing the row spare section 11 or the column spare section 21 in accordance with the location and the number of defective portions, so that the test controller 33 and the APG (Algorithmic Pattern Generator) are used.
r) The test circuit 10, the row line data read circuit 13, and the column line data read circuit 2
3, row line comparator 14, column line comparator 24,
Row failure counter 15, column failure counter 25, row failure number storage register 16, column failure number storage register 2
6, a replacement line selection circuit 31a, a row replacement circuit 12, a column replacement circuit 22, and a replacement circuit 41.

The test controller 33 is supplied with an external signal from a computer (not shown) outside the apparatus, and performs sequence control integrally on the entire circuit in the apparatus. Further, the replacement line selection circuit 31a informs the user whether or not replacement is possible, and outputs the result of replacement as an external signal to the computer. Then, after receiving an external signal from the computer again and performing an operation of writing the content of the replacement to the replacement circuit 41 as address decoder information, the replacement circuit 41 outputs a replacement processing end signal to the outside.

The APG 32 receives a signal from the test controller 33, and receives an address signal indicating an address of a cell to be read from the main cell 10, a control signal for controlling read and comparison operations, and a test vector including expected value data. And the low-line data read circuit 13,
The signal is supplied to the row line comparator 14, the column line data read circuit 23, and the column line comparator 24.

The low line data reading circuit 13
According to the address information and the control signal included in the test vector given from the PG 32, cell data for one row is read out from the main body cell 10 at a time, and the row line comparator 14
Give to. Similarly, the column line data read circuit 2
3 collectively reads cell data for one column from the main body cell 10 according to the test vector,
Give to 4.

The row line comparator 14 is supplied with cell data for one row from the row line data read circuit 13, and further compares the cell data with expected value data contained in the test vector supplied from the APG 32, and compares the comparison result. Is output. Here, the comparison is not performed on the row line for which the replacement is already provisionally set by the row replacement circuit 12.

The column line comparator 24 receives cell data for one column from the column line data read circuit 23, compares the cell data with expected value data for each cell, and outputs a comparison result. In this case, similarly to the row line, the comparison is not performed on the column line for which the replacement has already been provisionally set by the column replacement circuit 22.

The row defect counter 15 receives the comparison result from the row line comparator 14, counts the number of defects for each cell present on the row line, and supplies the count result to the row defect number storage register 16. Column failure counter 2
5 receives the comparison result from the column line comparator 24, counts the number of defects for each cell in the column line, and supplies the count result to the column defect number storage register 26.

The row defect number storage register 16 stores the given row defect number, and the column defect number storage register 26 stores the given column defect number. The number of row defects and the number of column defects are given to the test controller 33.

The replacement line selection circuit 31a is given the number of row failures and the number of column failures from the test controller 33, and performs replacement with a defective portion using either the row of the row spare section 11 and / or the column of the column spare section 21. Or a combination of the replacement destinations, and further, any one of the replacement destinations is assumed.

When the replacement line selection circuit 31a assumes row replacement, the information is given to the row replacement circuit 12, and the row replacement circuit 12a sets the replacement destination of the row line.

When the replacement line selection circuit 31a assumes column replacement, the information is given to the column replacement circuit 22 to set the replacement destination of the column line.

The replacement circuit 41 includes a row replacement circuit 12 and / or
Or, based on the replacement destination set by the column replacement circuit 22,
The defective part is replaced with the row replacement circuit 12 and / or the column replacement circuit 22. Specifically, the row spare part 11 or / and /
And decoder address information indicating a correspondence relationship with the address of the column spare unit 21 is written. For example, fuses are arranged in a matrix, and decoder address information is written by blowing the corresponding fuse. Alternatively, it has a ROM cell such as an EEPROM and the decoder address information is written in the cell.

Here, of the above-mentioned circuits, there are those that need to survive when cutting each semiconductor chip from a semiconductor wafer and those that do not. The circuits that should survive as the device are the main body cell 10, the row spare unit 11, the column spare unit 21, and the replacement circuit 41. After writing the decoder address information into the replacement circuit 41, those that do not need to survive as a device include the test controller 33, the APG 32, the replacement line selection circuit 31a, the row replacement circuit 12, the column replacement circuit 22, the row line readout circuit 13, and the column. A line readout circuit 23, a row line comparator 14, a column line comparator 24, a row failure counter 15, a column failure counter 25, a row failure number storage register 16, and a column failure number storage register 26.

Area penalties can be reduced by arranging circuits that do not need to survive as such a device on the scribe line. For this reason, although a new circuit is added by the present embodiment as compared with the related art, it is possible to prevent a substantial increase in the element area.

Next, a description will be given of a procedure of a process for replacing a defective portion in the present apparatus having such a configuration.

(1) A trigger signal is input from an external computer to the test controller 33, and the operation starts. The test controller 33 presets which of the row and the column is to be preferentially replaced. Further, the test controller 33 determines the defective part by the row spare part 11 and / or
Alternatively, the number of trials to be replaced by the column spare unit 21 is set.

(2) The test controller 33 uses the APG
32 is started. The APG 32 generates a test vector necessary for specifying a defective portion existing in the main body cell 10. The test vector includes address information necessary for reading data from the main body cell 10, control signals for controlling the read operation, input data, and the like. The generated test vector is supplied to the main body cell 10, the cell data is collectively read in units of row lines by the row line data reading circuit 13, and the cell data is read by the column line data reading circuit 23 for each column line. Is read. The data read for each row line is compared with the expected value generated by the APG 32 by the row line comparator 14. Row defect counter 15
Thus, the number of defects existing in the row line is counted and stored in the row defect number storage register 16. The data read for each column line is compared with an expected value by a column line comparator 24, and the column failure number counter 2
5, the number of defects existing in the column line is counted and stored in the column defect number storage register 26.

Here, if the row line address and the column line address of the replacement destination are set at this time by the row replacement circuit 12 and the column replacement circuit 22, no comparison is made with respect to those addresses.

If the count value of the defect is "0" in both the row and the column, the row defect number storage register 16
Then, the information is provided to the test controller 33 from the column defect number storage register 26. The test controller 33 determines that the product is non-defective, and outputs a replacement process end signal to the outside. If the number of defects of at least one of the row line and the column line is not “0”, the process proceeds to the next process.

(3) The number of defects stored in the row defect number storage register 16 and the column defect number storage register 26, respectively, is the total number of bits (row spare line number * column) that can be rescued by the row spare section 11 and the column spare section 21. If the number exceeds the number of spare lines * 2), the test controller 33 determines that the repair is impossible and outputs the information as an external signal.

It is assumed that the number of row spare lines in the row spare section 11 is m and the number of column spare lines in the column spare section 21 is n. In this case, if there is a defect along one row-side line, the number of defects that can be remedied by the column spare unit 21 is n column spare lines. Since there are m row spare lines on the row side, n * m number of defects can be relieved for defects existing along the m lines on the row side.

Similarly, when a defect exists along one column-side line, the number of defects that can be repaired by the row spare unit 11 is m, the number of row spare lines. Since there are n number of column spare lines on the column side, m * n number of defects can be relieved for defects existing along the n lines on the column side. Therefore, by summing both, n * m + m * n = 2 * n * m.

(4) Based on the number of row failures and the number of column failures, whether there is a line to be replaced in the row spare unit 11 or the column spare unit 21 (hereinafter, such a line is referred to as a replacement mast line). Is determined by the test controller 33, and if it exists, that line is preferentially used as the replacement destination. If there is no replacement mast line, it is determined whether to select a row or a column in accordance with the priority set in step (1).

Here, the replacement mast line is a replacement mast line when the number of defects in the row direction exceeds the number of spare row lines and there is a defect, and conversely, the number of defects in the column direction is the column mast line. When there is a defect exceeding the number of spare lines, the row line becomes the replacement mast line.

When the number of defects is the same between the row line and the column line, the row line or the column line is selected according to the priority determined in advance by the test controller 33. In this way, the replacement line selection circuit 31a temporarily sets the replacement destination line.

(5) The address decoder information indicating the correspondence between the address of the defective portion of the main cell 10 and the address of the replacement destination is written into the replacement circuit 41 in accordance with the provisionally set replacement destination line.

(6) As in the above step (2), data is read from the main body cell 10 again and the number of defects is counted. For lines that have already been replaced,
Do not compare the read data with the expected value. If the number of defective products is “0”, the test controller 33 determines that the product is non-defective, and outputs a replacement processing end signal to the outside. If the number of defects is not “0”, the number of defects is stored in the row and column defect storage registers 16 and 26.

(7) A replacement process is performed on the priority line determined in (4). While the spare line remains and can be replaced with an address where a defect exists in the row defect number storage register 16 or the column defect number storage register 26 in the priority line, an address having a large number of defects is preferentially provided. Assign a replacement address.
If the number of defects is equal in the row and column lines, the test controller 33 operates the replacement circuit line selection circuit 31a to randomly select one of the lines and assign a replacement address. The test controller 33 writes the address to the replacement circuit 41 for the allocated line.

(8) The APG 32 is started by the test controller 33, and a test vector is generated and given to the main cell 10. The row line data read circuit 13 and the column line data read circuit 23 read data for each line. The read line data and the expected value are compared by the road line comparator 14 and the column line comparator 24. Also in this case, the line to which replacement is already set in the row replacement circuit 12 and the column replacement circuit 22 is not compared with the expected value. The number of defects that do not match the expected value is counted by the row defect counter 15 and the column defect counter 25, and the row defect number storage register 16 and the column defect number storage register 26
The count number is stored in. When the number of defects is “0” in both the row line and the column line, the test controller 33 outputs a replacement processing end signal to the outside. If the number of defects is not “0”, the process proceeds to the next process.

(9) Perform relief processing on a non-priority line different from the priority line determined in (4).
The replacement destination address is set for each non-priority line. In this case, as many spare lines as the number of remaining spare lines are allocated in order from the line with the largest number of defects. If the number of defects is equal, a line is selected at random and the number of spare lines is divided. If the number of defectives is larger than the number of spare lines remaining in the non-priority line, the process returns to the priority line rescue process in (7).

(10) The APG 32 is started by the test controller 33, and a test vector is generated and given to the main cell 10. Low line data read circuit 13
The column line data read circuit 23 reads data for each line. The read data and the expected value are compared by the row line comparator 14 and the column line comparator 24. Also in this case, the row replacement circuit 1
No comparison is made with the expected value for the lines for which replacement has already been set in the second and column replacement circuits 22. The number of failures that do not match the expected value is the row failure counter 1
5 and the column failure counter 25, and the counted number is stored in the row failure number storage register 16 and the column failure number storage register 26. If the number of defects is “0” in both the row line and the column line, the test controller 33 outputs a replacement processing end signal to the outside. If the number of defects is not “0”, the above (7)
Then, the same processing is repeated up to the preset replacement trial number.

(11) The replacement process is repeated up to the number of replacement trials. If the number of defects still does not become “0”, it is determined that the replacement process is not possible, and the test controller 33 generates a replacement disable signal outside.

(12) The replacement is actually executed by using the address information to be replaced written in the replacement circuit 41.
Specifically, for example, when the replacement circuit 41 has fuses arranged in a matrix, the replacement circuit 41 is blown by a high-voltage input or laser irradiation. The replacement circuit 41
When a ROM cell such as a PROM is provided, address decoder information is written.

FIG. 3 shows a specific example of the above-described replacement processing.
And the procedure of the process will be described. As shown in FIG. 3A, the main body cell 10 has 16 cells of 4 rows × 4 columns, and addresses of defective portions are (00, 00), (00, 1).
0), (01, 00), (01, 01), (01, 10), (01, 1
1), (10, 11), and (11, 11). The row replacement circuit 12 and the column replacement circuit 22 each have two replaceable spare lines. The APG 32 is operated to compare the output data with the expected value,
, The number of defects “2” in the order of row addresses (00) to (11),
“1”, “2”, and “3” are stored. Similarly, the column defect number storage register 26 has column addresses (00) to
The number of defects “2”, “4”, “1”, and “1” are stored in the order of (11).

If the number of defects per line is larger than the number of row line spares or column line spares,
This is “4” of the column line along the column address (01). Therefore, as shown in FIG. 3B, the column line (01) which is the replacement mast line is determined. As a result, all the defective portions (01, 00), (01, 01), (01, 10), (01, 11) located along the column line (01) become one column of the column replacement circuit 22. Replaced by line (O1) and relieved. The address of the remaining defective part is (00,
00), (00, 10), (10, 11), (11, 11).

The APG 32 is operated again, and the main cell 10
The data is read out from the memory and compared with the expected value to count the number of failures. Here, comparison is not performed for the column line (01) for which the replacement destination has already been set.

As a result, as shown in FIG. 3B, the row address (00) is stored in the row defect number storage register 16.
To (11), the number of defects is “1”, “0”, “1”, “2”
Is stored. Similarly, the column defect number storage register 26
Stores the number of defects "2", "0", "1", and "1" in the order of column addresses "00" to "11".

The largest number of defects is "2" on the row line along the row address (11) or "2" on the column line along the column address (00). Although the number of defects is the same in the row line and the column line, but the row line has priority, the row replacement line (11) is assumed as shown in FIG. This allows the low line (1
The defective portions (10, 11) and (11, 11) located in 1) are replaced.

The address of the remaining defective part is (00, 00)
And (00,10). The APG 32 is operated again to read data from the main body cell 10 and compare it with an expected value to count the number of defects. The number of defects "2" is stored in the row defect number storage register 16 in the order of the row addresses (00) to (11),
“0”, “0”, and “0” are stored. The column defect number storage register 26 stores the defect numbers “2”, “0”, “0”, and “0” in the order of column addresses “00” to “11”.

As shown in FIG. 3C, a defective portion (00, 00) located on the row line (00) is replaced by assuming a row replacement line (00). The APG 32 is operated to read data from the main body cell 10 and compare it with an expected value to count the number of defects. The comparison with the expected value is not performed for the row line (00) for which the replacement destination has already been set.

As shown in FIG. 4, the row defect number storage register 1
6, the number of defects “0” is stored in all the columns, and the column defect number storage register 26 stores the number of all defects “0”. Since the number of defects has become "0", the process is terminated. It determines that the product has been rejected and outputs a replacement search end signal to the outside. Then, replacement is performed based on the information set in the replacement circuit 41.

As described above, according to the first embodiment, a circuit for performing a repair process for detecting a defective portion and replacing it with a redundant circuit is provided inside the apparatus, and a simple signal such as a trigger is externally provided. Can be remedied just by giving
The equipment required for the test and replacement processing is simple and inexpensive. Conventionally, as described above, an expensive semiconductor test apparatus that costs as much as 100 million yen, a laser repair apparatus for blowing a fuse, and a system for transmitting information from the semiconductor test apparatus to the laser repair apparatus. Needed. Since such an expensive device is unnecessary, it can contribute to cost reduction.

Further, as the storage capacity increases, the capacity of the redundancy circuit itself also increases, and the configuration of the replacement circuit is complicated. For this reason, several tens of minutes are required for a test time for detecting a defective portion using a semiconductor test apparatus. However, according to the present embodiment, it is possible to read out cell data collectively for each row and column line, and to count the number of defects in comparison with an expected value, so that the test time can be reduced.

Next, a semiconductor memory device according to a second embodiment of the present invention will be described. This embodiment is shown in FIG.
Are provided. In the first embodiment shown in FIG. 1, the replacement line selection circuit 31a operates by being given information about the rescue method set by the test controller 33. On the other hand, the present embodiment is different in that such information is given in advance in the form of a program from the outside, stored in the replacement line selection circuit 31b, and this information is read out to perform an operation. Other configurations are the same as those in the first embodiment, and a description thereof will be omitted.

The above embodiment is an example and does not limit the present invention. For example, in the configuration shown in FIG. 1 or FIG. 2, a test controller for controlling the entire apparatus and an APG for generating a signal necessary for a test are provided separately, but they may be provided integrally as a test circuit. Good.

[0061]

As described above, the semiconductor memory device with a built-in redundant circuit according to the present invention has a structure necessary for replacement inside the device and can automatically replace a defective portion with a redundant circuit inside. In addition, expensive test equipment such as a laser repair device is not required, and the test time required for setting a replacement address can be shortened, so that the test cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a procedure for performing a repair process for a defective portion according to the first or second embodiment.

FIG. 4 is an explanatory diagram showing a procedure for performing a repair process for a defective portion according to the first or second embodiment.

[Explanation of symbols]

 11 Row Spare Unit 12 Row Replacement Circuit 13 Row Line Data Read Circuit 14 Row Line Comparator 15 Row Failure Counter 16 Row Failure Number Storage Register 21 Column Spare Unit 22 Column Replacement Circuit 23 Column Line Data Read Circuit 24 Column Line Comparator 25 Column Failure Counter 26 Column defect number storage register 31a, 31b Replacement line selection circuit 32 APG 33 Test controller 41 Replacement circuit

Claims (2)

[Claims] 1. A semiconductor memory device having a main body cell and a redundant circuit, comprising: a test circuit for generating a signal necessary for processing for replacing a defective portion of the main body cell with the redundant circuit; A row line and column line data read circuit for reading data stored in the body cell as a unit; data read by the row line and column line data read circuit; and an expectation included in the signal generated by the test circuit. A row line and a column line comparator for comparing the value with a unit other than the line for which the replacement destination is set and determining whether or not the line is defective, and the row line and the column line comparator are determined to be defective. A row and column failure counter for counting the number in units of row lines and column lines; A row and column defect number storage register for storing the number of defects counted by the column defect counter in units of row and column lines, and a row line in which the number of defects stored in the row and column defect number storage register is not zero Or, for a column line, a replacement line selection circuit that generates a combination to replace a row line or a column line of the redundant circuit, a row line that the test circuit temporarily sets using the combination generated by the replacement line selection circuit, and A row and column replacement circuit for storing replacement addresses in units of column lines, and a replacement address stored in the replacement circuit,
A semiconductor memory device with a built-in redundant circuit, comprising: a replacement circuit that replaces a defective portion of the main body cell with the redundant circuit. 2. The test circuit, comprising: a pattern generator for generating a test vector required to read data from the main body cell; and a trigger signal supplied from outside, the pattern generator, the row line, and the column line. A test for outputting a data readout circuit, the row and column line comparator, the row and column failure counter, the row and column failure count storage register, the row and column replacement circuit, and a control signal for controlling the operation of the replacement circuit. The semiconductor memory device with a built-in redundant circuit according to claim 1, further comprising: a controller.