KR100794865B1 - Multi-memory card package structure and method for manufacturing the same - Google Patents

Multi-memory card package structure and method for manufacturing the same Download PDF

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KR100794865B1
KR100794865B1 KR1020060038763A KR20060038763A KR100794865B1 KR 100794865 B1 KR100794865 B1 KR 100794865B1 KR 1020060038763 A KR1020060038763 A KR 1020060038763A KR 20060038763 A KR20060038763 A KR 20060038763A KR 100794865 B1 KR100794865 B1 KR 100794865B1
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South Korea
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memory card
connection terminal
signal connection
substrate
package structure
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KR1020060038763A
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Korean (ko)
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KR20070106183A (en
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에디 루
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킹맥스 디지탈 인코포레이티드
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R25/00—Coupling parts adapted for simultaneous co-operation with two or more identical counterparts, e.g. for distributing energy to two or more circuits
    • H01R25/006—Coupling parts adapted for simultaneous co-operation with two or more identical counterparts, e.g. for distributing energy to two or more circuits the coupling part being secured to apparatus or structure, e.g. duplex wall receptacle
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
    • H01R12/70—Coupling devices
    • H01R12/71—Coupling devices for rigid printing circuits or like structures
    • H01R12/712—Coupling devices for rigid printing circuits or like structures co-operating with the surface of the printed circuit or with a coupling device exclusively provided on the surface of the printed circuit
    • H01R12/716—Coupling device provided on the PCB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Credit Cards Or The Like (AREA)

Abstract

본 발명은 멀티-메모리 카드 팩키지에 관한 것으로서, 제 1 메모리 카드, 제 2 메모리 카드, 및 회로 연결 보드를 포함한다. 상기 제 1 메모리 카드는 제 1 신호 연결 터미널이 형성된 제 1 말단부 및 제 2 말단부를 가진다. 상기 제 2 메모리 카드는 제 2 신호 연결 터미널이 형성된다. 상기 회로 연결 보드는 제 1 메모리 카드의 제 1 신호 연결 터미널을 제 2 메모리 카드의 제 2 신호 연결 터미널에 전기적으로 연결한다.The present invention relates to a multi-memory card package, comprising a first memory card, a second memory card, and a circuit connection board. The first memory card has a first end portion and a second end portion on which a first signal connection terminal is formed. The second memory card has a second signal connection terminal. The circuit connection board electrically connects the first signal connection terminal of the first memory card to the second signal connection terminal of the second memory card.

Description

멀티-메모리 카드 팩키지 구조 및 이의 제조 방법{MULTI-MEMORY CARD PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME}MULTI-MEMORY CARD PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

도 1은 종래의 메모리 카드 팩키지 구조를 도시한 구성도이다.1 is a block diagram showing a conventional memory card package structure.

도 2는 본 발명의 멀티-메모리 카드 구조를 도시한 단면 구성도이다.2 is a cross-sectional configuration diagram showing a multi-memory card structure of the present invention.

도 3은 본 발명의 멀티-메모리 카드 구조를 도시한 제 1 구성도이다.3 is a first configuration diagram showing a multi-memory card structure of the present invention.

도 4는 본 발명의 멀티-메모리 카드 구조를 도시한 제 2 구성도이다.4 is a second configuration diagram showing a multi-memory card structure of the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

40: 제 1 메모리 카드 42: 제 2 메모리 카드40: first memory card 42: second memory card

44: 회로 연결 보드 45: 합성 수지44: circuit connection board 45: synthetic resin

46: 제 1 기판 48: 제 1 칩46: first substrate 48: first chip

50: 제 1 와이어 52: 제 1 말단부50: first wire 52: first end portion

54: 제 2 말단부 56: 제 1 신호 연결 터미널54: second end 56: first signal connection terminal

58: 골든 핑거부 60: 제 2 기판58: golden finger 60: second substrate

62: 제 2 칩 64: 제 2 와이어62: second chip 64: second wire

66: 제 2 신호 연결 터미널 68: 제 1 연결 말단부66: second signal connection terminal 68: first connection end

70: 제 2 연결 말단부 72: 볼 그레이드 어레이70 second connection end 72 ball grade array

74: 프린트된 회로 보드74: printed circuit board

본 발명은 멀티-메모리 카드 팩키지 구조 및 이를 제조하는 방법에 관한 것으로서, 더욱 상세하게는 두 개의 메모리 카드를 연결하여 메모리의 양을 증대시키는 구조에 관한 것이다.The present invention relates to a multi-memory card package structure and a method of manufacturing the same, and more particularly, to a structure for increasing the amount of memory by connecting two memory cards.

도 1을 참조하면, 종래의 메모리 카드 팩키지 구조는 기판(10), 접착된 층(22), 칩(24), 및 합성물 층(30)을 포함한다.Referring to FIG. 1, a conventional memory card package structure includes a substrate 10, an bonded layer 22, a chip 24, and a composite layer 30.

상기 기판(10)은 제 1 전극(16) 및 제 1 전극(16)에 전기적으로 연결된 골든 핑거부(golden fingers)(18), 및 수동 부품(20)이 형성된 상위 표면(12)을 가진다. 상기 접착된 층(22)은 기판(10)의 상위 표면(12) 위에 코팅되어 있다. 상기 칩(24)에는 본딩 패드(26)가 형성되며, 접착된 층(22)에 의하여 기판(10)의 상위 표면(12) 위에 부착된다. 복수의 와이어(28)는 칩(24)의 본딩 패드(26)를 제 1 전극(16)에 전기적으로 연결한다. 그리고 합성물 층(30)은 칩(24) 및 와이어(28)를 밀봉한다.The substrate 10 has a first electrode 16, a golden fingers 18 electrically connected to the first electrode 16, and an upper surface 12 on which the passive component 20 is formed. The bonded layer 22 is coated over the upper surface 12 of the substrate 10. Bonding pads 26 are formed on the chip 24, and are adhered on the upper surface 12 of the substrate 10 by means of a bonded layer 22. The plurality of wires 28 electrically connect the bonding pads 26 of the chip 24 to the first electrode 16. And composite layer 30 seals chip 24 and wire 28.

본 발명의 목적은 메모리의 양을 증대시키는 효과를 가지는 멀티-메모리 카 드 팩키지 구조 및 이를 제조하는 방법을 제공하는 것이다. It is an object of the present invention to provide a multi-memory card package structure having the effect of increasing the amount of memory and a method of manufacturing the same.

상기한 본 발명의 기술적 과제를 달성하기 위하여, 본 발명은 제 1 메모리 카드, 제 2 메모리 카드, 및 회로 연결 보드를 포함한다. 상기 제 1 메모리 카드는 제 1 신호 연결 터미널이 형성된 제 1 말단부 및 제 2 말단부를 가진다. 상기 제 2 메모리 카드에는 제 2 신호 연결 터미널이 형성된다. 상기 회로 연결 보드는 제 1 메모리 카드의 제 1 신호 연결 터미널을 제 2 메모리 카드의 제 2 신호 연결 터미널에 전기적으로 연결한다.In order to achieve the above technical problem, the present invention includes a first memory card, a second memory card, and a circuit connection board. The first memory card has a first end portion and a second end portion on which a first signal connection terminal is formed. A second signal connection terminal is formed on the second memory card. The circuit connection board electrically connects the first signal connection terminal of the first memory card to the second signal connection terminal of the second memory card.

도 2 및 도 3을 참조하면, 본 발명의 멀티-메모리 카드 팩키지 구조는 제 1 메모리 카드(40), 제 2 메모리 카드(42), 회로 연결 보드(44), 및 합성 수지(45)를 포함한다.2 and 3, the multi-memory card package structure of the present invention includes a first memory card 40, a second memory card 42, a circuit connection board 44, and a synthetic resin 45. do.

상기 제 1 메모리 카드(40)는 제 1 기판(46), 및 제 1 칩(48)을 포함하며, 제 1 칩(48)은 제 1 기판(46)의 위에 탑재되고, 제 1 와이어(50)에 의하여 제 1 기판(46)에 전기적으로 연결된다. 제 1 기판(46)은 제 1 말단부(52)를 가지며, 제 1 신호 연결 터미널(56)이 그 위에 형성되고, 제 2 말단부(54) 위의 골든 핑거부(58)는 전기적 장치에 전기적으로 연결되도록 형성된다.The first memory card 40 includes a first substrate 46 and a first chip 48, the first chip 48 being mounted on the first substrate 46, and the first wire 50. ) Is electrically connected to the first substrate 46. The first substrate 46 has a first end 52, a first signal connection terminal 56 formed thereon, and the golden finger 58 over the second end 54 is electrically connected to the electrical device. It is formed to be connected.

상기 제 2 메모리 카드(42)는 제 2 기판(60), 및 제 2 칩(62)을 포함하며, 제 2 칩(62)은 제 2 기판(60) 위에 탑재되고, 제 2 와이어(64)에 의하여 제 2 기판(60)에 연결된다. 상기 제 2 기판(60)에는 제 2 신호 연결 터미널(66) 및 볼 그 레이드 어레이(ball grad array)(72)가 형성된다.The second memory card 42 includes a second substrate 60 and a second chip 62, the second chip 62 being mounted on the second substrate 60, and the second wire 64. By the second substrate 60. A second signal connection terminal 66 and a ball grad array 72 are formed on the second substrate 60.

상기 회로 연결 보드(44)는 유연성있는 회로 보드로 이루어지며, 제 1 메모리 카드(40)의 제 1 신호 연결 터미널(56)을 전기적으로 연결하기 위한 제 1 연결 말단부(68), 제 2 메모리 카드(42)의 제 2 신호 연결 터미널(66)을 전기적으로 연결하기 위한 제 2 연결 말단부(70)을 포함한다.The circuit connection board 44 is made of a flexible circuit board, and includes a first connection end portion 68 and a second memory card for electrically connecting the first signal connection terminal 56 of the first memory card 40. A second connection end 70 for electrically connecting the second signal connection terminal 66 of 42.

상기 합성 수지(45)는 회로 연결 보드(44)의 제 1 말단부(68) 및 제 1 기판의 제 1 칩(48)의 위에 성형되어 제 1 메모리 카드(40)을 형성하며, 회로 연결 보드(44)의 제 2 말단부(70) 및 제 2 기판(60)의 제 2 칩(62)의 위에 성형되어 제 2 메모리 카드(42)를 형성한다.The synthetic resin 45 is molded on the first end portion 68 of the circuit connection board 44 and the first chip 48 of the first substrate to form the first memory card 40, and the circuit connection board ( The second end 70 of 44 and the second chip 62 of the second substrate 60 are molded to form a second memory card 42.

도 4를 참조하면, 제 2 메모리 카드(42) 위의 제 2 기판(60)에는 볼 그레이드 어레이(ball grad array, BGA)(72)가 형성되어 프린트된 회로 보드(74)와 연결된다. 상기 회로 보드(44)는 구부러질 수 있으며, 이로써 제 1 메모리 카드(40)의 합성 수지(45)는 제 2 메모리 카드(42)의 합성 수지(45)에 부착될 수 있다.Referring to FIG. 4, a ball grad array (BGA) 72 is formed on the second substrate 60 on the second memory card 42 and connected to the printed circuit board 74. The circuit board 44 may be bent, such that the synthetic resin 45 of the first memory card 40 may be attached to the synthetic resin 45 of the second memory card 42.

본 발명이 실시예 및 최적의 구현예를 들어 설명되었으나, 본 발명이 기술된 구현예에 한정되지 않으며, 다양한 수정 및 변형을 포함하는 것은 자명하다. 따라서, 이하에 첨부된 청구범위는 모든 수정 및 변형을 포함하여 최광의로 해석되어야 할 것이다.Although the present invention has been described with reference to embodiments and optimal embodiments, it is obvious that the invention is not limited to the described embodiments, and includes various modifications and variations. Accordingly, the claims appended hereto should be construed broadly, including all modifications and variations.

본 발명에 따른 멀티-메모리 카드 팩키지 구조 및 제조 방법은 제 1 메모리 카드(40)가 회로 연결 보드(44)에 의하여 제 2 메모리 카드(42)에 전기적으로 연결됨으로써 멀티-메모리 카드의 메모리 양이 증대되는 잇점을 가진다.In the multi-memory card package structure and manufacturing method according to the present invention, the first memory card 40 is electrically connected to the second memory card 42 by the circuit connection board 44, thereby reducing the amount of memory of the multi-memory card. Has the advantage of increasing

Claims (12)

제 1 신호 연결 터미널이 형성된 제 1 말단부 및 제 2 말단부를 가지는 제 1 메모리 카드;A first memory card having a first end portion and a second end portion having a first signal connection terminal formed thereon; 제 2 신호 연결 터미널이 형성된 제 2 메모리 카드; 및A second memory card having a second signal connection terminal formed thereon; And 제 1 메모리 카드의 제 1 신호 연결 터미널을 제 2 메모리 카드의 제 2 신호 연결 터미널에 전기적으로 연결하는 회로 연결 보드를 포함하고, A circuit connection board electrically connecting the first signal connection terminal of the first memory card to the second signal connection terminal of the second memory card, 상기 회로 연결 보드는 유연성 있는 회로 보드로 만들어진 멀티-메모리 카드 팩키지 구조.The circuit connection board is a multi-memory card package structure made of a flexible circuit board. 제 1항에 있어서, 상기 제 1 메모리 카드의 제 2 말단부는 골든 핑거부(golden finger)가 형성된 것을 특징으로 하는 멀티-메모리 카드 팩키지 구조.2. The multi-memory card package structure of claim 1, wherein a second end of the first memory card is formed with a golden finger. 삭제delete 제 1항에 있어서, 상기 제 2 메모리 카드는 볼 그레이드 어레이(BGA)가 형성된 것을 특징으로 하는 멀티-메모리 카드 팩키지 구조.2. The multi-memory card package structure as recited in claim 1, wherein said second memory card is formed with a ball grade array (BGA). 제 1 신호 연결 터미널이 형성된 제 1 말단부 및 제 2 말단부를 가지는 제 1 메모리 카드를 제공하는 단계;Providing a first memory card having a first end portion and a second end portion having a first signal connection terminal formed thereon; 제 2 신호 연결 터미널이 형성된 제 2 메모리 카드를 제공하는 단계; 및 Providing a second memory card having a second signal connection terminal formed thereon; And 제 1 메모리 카드의 제 1 신호 연결 터미널을 제 2 메모리 카드의 제 2 신호 연결 터미널에 전기적으로 연결하며, 제 1 메모리 카드 및 제 2 메모리 카드의 팩키지를 통합하는 회로 연결 보드를 제공하는 단계를 포함하고,Providing a circuit connection board electrically connecting the first signal connection terminal of the first memory card to the second signal connection terminal of the second memory card and integrating the packages of the first memory card and the second memory card. and, 상기 회로 연결 보드는 유연성 있는 회로 보드로 만들어진 멀티-메모리 카드 팩키지 구조의 제조 방법.The circuit connection board is a method of manufacturing a multi-memory card package structure made of a flexible circuit board. 제 5항에 있어서, 상기 제 1 메모리 카드의 제 2 말단부는 골든 핑거부가 형성된 것을 특징으로 하는 멀티-메모리 카드 팩키지 구조의 제조 방법.6. The method of claim 5, wherein the second end of the first memory card has a golden finger formed therein. 삭제delete 제 5항에 있어서, 상기 제 2 메모리 카드는 볼 그레이드 어레이(BGA)가 형성된 것을 특징으로 하는 멀티-메모리 카드 팩키지 구조의 제조 방법.6. The method of claim 5, wherein the second memory card is formed with a ball grade array (BGA). 제 1 신호 연결 터미널을 가지는 제 1 말단부 및 제2 말단부가 형성된 제 1 기판 및 상기 제 1 기판 위에 탑재된 제 1 칩을 포함하며, 제 1 와이어에 의하여 제 1 기판에 전기적으로 연결된 제 1 메모리 카드를 제공하는 단계;A first memory card including a first substrate having a first end portion and a second end portion having a first signal connection terminal, and a first chip mounted on the first substrate, the first memory card being electrically connected to the first substrate by a first wire; Providing a; 제 2 신호 연결 터미널이 형성된 제 2 기판 및 상기 제 2 기판 위에 탑재된 제 2 칩을 포함하며, 제 2 와이어에 의하여 제 2 기판에 전기적으로 연결된 제 2 메모리 카드를 제공하는 단계;Providing a second memory card comprising a second substrate having a second signal connection terminal and a second chip mounted on the second substrate, the second memory card being electrically connected to the second substrate by a second wire; 제 1 메모리 카드의 제 1 신호 연결 터미널에 전기적으로 연결된 제 1 연결 말단부 및 제 2 메모리 카드의 제 2 신호 연결 터미널에 전기적으로 연결된 제 2 연결 말단부가 형성된 회로 연결 보드를 제공하는 단계; 및Providing a circuit connection board having a first connection end electrically connected to the first signal connection terminal of the first memory card and a second connection end electrically connected to the second signal connection terminal of the second memory card; And 회로 연결 보드의 제 1 말단부 및 제 1 기판의 제 1 칩 위에 성형되어 제 1 메모리 카드를 형성하고, 회로 연결 보드의 제 2 말단부 및 제 2 기판의 제 2 칩 위에 성형되어 제 2 메모리 카드를 형성하는 합성 수지를 제공하는 단계를 포함하고, Formed on the first end of the circuit connection board and the first chip of the first substrate to form a first memory card, and formed on the second end of the circuit connection board and the second chip of the second substrate to form a second memory card Providing a synthetic resin, 상기 회로 연결 보드는 유연성 있는 회로 보드로 만들어진 멀티-메모리 카드 팩키지 구조의 제조 방법.The circuit connection board is a method of manufacturing a multi-memory card package structure made of a flexible circuit board. 제 9항에 있어서, 상기 제 1 메모리 카드의 제 2 말단부는 골든 핑거부가 형성된 것을 특징으로 하는 멀티-메모리 카드 팩키지 구조의 제조 방법.10. The method of claim 9, wherein the second end of the first memory card has a golden finger formed therein. 삭제delete 제 9항에 있어서, 상기 제 2 메모리 카드는 볼 그레이드 어레이(BGA)가 형성된 것을 특징으로 하는 멀티-메모리 카드 팩키지 구조의 제조 방법.10. The method of claim 9, wherein the second memory card is formed with a ball grade array (BGA).
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH061095A (en) * 1992-06-19 1994-01-11 Toshiba Corp Memory card
JPH10250275A (en) 1997-03-18 1998-09-22 Hitachi Ltd Memory card and its manufacture
KR19990059037A (en) * 1997-12-30 1999-07-26 마이클 디. 오브라이언 Ball Grid Array Semiconductor Package Using Flexible Circuit Board and Manufacturing Method Thereof
KR20050037674A (en) * 2003-10-20 2005-04-25 삼성전자주식회사 Semiconductor memory card

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH061095A (en) * 1992-06-19 1994-01-11 Toshiba Corp Memory card
JPH10250275A (en) 1997-03-18 1998-09-22 Hitachi Ltd Memory card and its manufacture
KR19990059037A (en) * 1997-12-30 1999-07-26 마이클 디. 오브라이언 Ball Grid Array Semiconductor Package Using Flexible Circuit Board and Manufacturing Method Thereof
KR20050037674A (en) * 2003-10-20 2005-04-25 삼성전자주식회사 Semiconductor memory card

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