KR100783694B1 - Liquid crystal display device and apparatus for driving the same - Google Patents

Abstract

The present invention discloses a liquid crystal display and a driving device thereof for high speed response.

According to the present invention, the gray voltage generator extracts a voltage corresponding to the gray levels of the negative side and the positive side VT from the built-in resistor array, and outputs a gray voltage adapted to each gray level to the data driver. In this case, the gray voltage generator according to an embodiment may include a resistor array of one line connected in series to extract a voltage corresponding to the gray of the negative side and the positive side of the VT, and output the voltage to the data driver, according to another embodiment. The generator generates a pair of series-connected resistor arrays and draws a voltage corresponding to the gray level of the negative side and the positive side VT, and outputs the voltage to the data driver.

As a result, by changing the position of the output voltage drawn out from the resistor array of the gray voltage generator, the overshoot amount can be amplified to drive the liquid crystal display at high speed.

Fast response, common electrode, swing, overshoot, resistance, gradation, LCD

Description

Liquid crystal display and its driving device {LIQUID CRYSTAL DISPLAY DEVICE AND APPARATUS FOR DRIVING THE SAME}

1 is a diagram for explaining a pixel equivalent circuit of a general TFT-LCD.

2 is a diagram for explaining the effect of a general CCD.

FIG. 3 is a diagram illustrating a pixel equivalent circuit of a TFT-LCD using a front gate proposed by Matsushita.

4 is a waveform diagram illustrating an improvement in response speed using the front gate signal of FIG. 3.

5 is a waveform diagram illustrating a change in pixel voltage due to a periodic swing common voltage.

FIG. 6 is a diagram for explaining a VT curve converted as the swing width of the common electrode voltage is increased.

7 is a view for explaining the relationship between the resistance array and the VT curve in the driving PCB.

FIG. 8 is a diagram for describing a liquid crystal display for high speed response according to an exemplary embodiment of the present invention.

9 is a view for explaining a specific resistor array according to an embodiment of the present invention.

10 is a view for explaining a specific resistor array according to another embodiment of the present invention.

The present invention relates to a liquid crystal display device and a driving device thereof, and more particularly, to a liquid crystal display device and a driving device thereof for amplifying an amount of overshoot for a high speed response of the liquid crystal display device.

Recently, display devices are also required to be lighter and thinner in accordance with lighter and thinner personal computers and televisions, and flat panel displays such as liquid crystal displays (LCDs) are being developed instead of cathode ray tubes (CRTs). It is being used in various fields.

An LCD is a display device that obtains a desired image signal by applying an electric field to a liquid crystal material having an anisotropic dielectric constant injected between two substrates, and controlling the amount of light transmitted through the substrate by adjusting the intensity of the electric field. Such LCDs are typical of portable flat panel display devices, and among them, TFT-LCDs using thin film transistors (TFTs) as switching elements are mainly used.

1 is a diagram for explaining a pixel equivalent circuit of a general TFT-LCD.                         

As shown in FIG. 1, a pixel of a typical TFT-LCD includes a TFT switching element, a liquid crystal capacitor Clc, a storage capacitor Cst, a first parasitic capacitor Cgd, and a second parasitic connected to a data line and a gate line, respectively. Capacitors Cds and Overlap Capacitors (Cover) are included.

In driving, when a bipolar pulse is applied through the gate line, the TFT switching element is turned on. At this time, the signal voltage applied to the source electrode of the TFT switching element through the signal line is applied to the liquid crystal capacitor Clc and the storage capacitor Cst through the drain. The signal voltage applied with the gate pulse is maintained even after the gate voltage is turned off and is applied to the liquid crystal capacitor Clc. However, due to the first parasitic capacitor Cgd between the gate and the drain, the pixel voltage is shifted by a certain voltage level.

In responding to such a liquid crystal display (LCD) in a large screen application or the like, the biggest limitation is the response speed. In order to improve the response speed of the large-screen liquid crystal display, Matsushita Corporation improves the response speed of the liquid crystal display by improving the CCD (Capacitive Coupled Driving) method currently applied.

2 is a diagram for explaining the effect of a general CCD.

As shown in FIG. 2, the direction of overshoot / undershoot applied to the pixel is determined by the liquid crystal characteristics having a low dielectric constant.

When a pulse is applied to the common electrode, the amount of capacitive coupling is greater in the pulse direction when the dielectric constant of the liquid crystal is small.

When the voltage applied to the common electrode is reversed from (+) to (-), the voltage is lowered first, and when the voltage is raised or lowered (-) to (+), normal white is applied. In the case of (Normal white), when changing from the high gray level to the low gray level, or when the change from the low gray level to the high gray level occurs, the liquid crystal always shows the on-shoot than the desired steady state voltage. Under shoot and over shoot occur, causing the liquid crystal to rotate faster.

Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide a driving device of a liquid crystal display device for amplifying an amount of overshoot for a high speed response of the liquid crystal display device.

Another object of the present invention is to provide a liquid crystal display for amplifying an amount of overshoot for a high speed response of the liquid crystal display.

According to one aspect of the present invention, there is provided a driving apparatus of a liquid crystal display device comprising a plurality of data lines, a plurality of gate lines arranged orthogonal to the data lines, the data lines and the gate lines. A liquid crystal display panel formed in a predetermined region arranged in a lattice therebetween, and having an end connected to the gate line and the other end connected to the data line so as to be inverted so as to have a polarity different from that of the previous frame for each frame In the driving device of the liquid crystal display device comprising:

Outputs a first drive signal and a second drive signal according to an image signal applied from the outside, and outputs a third drive signal defining a period and an amplitude according to the vertical sync signal, the horizontal sync signal and the main clock signal applied from the outside. A timing controller;

A data driver for outputting an image signal for driving a polarity of a liquid crystal capacitor to the data line based on the first driving signal;

A gradation voltage generator for extracting a voltage corresponding to the gradations of the negative side and the positive side VT from the built-in resistor array and outputting a gradation voltage adapted to each gradation to the data driver;

A gate driver configured to output a scan signal to the gate line based on the second driving signal; And

And a driving voltage generator configured to receive a level of the third driving signal, increase or decrease a level, and output a common electrode voltage swinging at a predetermined cycle to a gate driving voltage to the liquid crystal display panel.

In addition, the liquid crystal display device according to one feature for realizing the above object of the present invention,

Outputs a first drive signal and a second drive signal according to an image signal applied from the outside, and outputs a third drive signal defining a period and an amplitude according to the vertical sync signal, the horizontal sync signal and the main clock signal applied from the outside. A timing controller;                     

A gradation voltage generator for extracting a voltage corresponding to the gradations of the negative side and the positive side VT from the built-in resistor array and outputting a gradation voltage adapted to each gradation;

A data driver outputting an image signal for driving a polarity of a liquid crystal capacitor based on the first driving signal and the gray voltage;

A gate driver configured to output a scan signal based on the second driving signal;

A driving voltage generator configured to receive the third driving signal to increase or decrease a level, and output a common electrode voltage swinging at a predetermined cycle with a gate driving voltage; And

A plurality of data lines for transmitting the image signal, a plurality of gate lines orthogonal to the data lines, and a scan signal, and a predetermined region formed in a lattice arrangement between the data lines and the gate lines, one end of which is And a liquid crystal display panel connected to a gate line and having a pixel electrode connected to the data line at the other end thereof to be inverted so as to have a polarity different from that of the previous frame for each frame.

Here, the gray voltage generator according to the exemplary embodiment of the present invention incorporates a line of resistance arrays connected in series to draw voltages corresponding to the gray levels of the negative side and the positive side VT.

In addition, the gray voltage generator according to another embodiment of the present invention incorporates a pair of series connected resistor arrays to extract voltage corresponding to the gray levels of the negative side and the positive side VT.                     

According to the driving apparatus of the liquid crystal display and the driving method thereof, the liquid crystal display can be driven at high speed by amplifying the overshoot amount by changing the position of the output voltage drawn from the resistance array of the gray voltage generator.

Then, embodiments will be described so that those skilled in the art can easily implement the present invention.

FIG. 3 is a diagram illustrating a pixel equivalent circuit of a TFT-LCD using a front gate proposed by Matsushita, and FIG. 4 is a waveform illustrating a response speed improvement using the front gate signal of FIG. 3. It is also.

As illustrated in FIG. 3, the pixel equivalent circuit of the TFT-LCD proposed by Matsushita Corporation is connected to one end of the storage capacitor Cst and the other end to the front gate.

In operation, a magnitude of a voltage finally applied to a pixel by a common electrode voltage swinging by applying a pulse to a data line is expressed by Equation 1 below.

Where Vs is the source terminal applied voltage, Cst is the capacitance of the storage capacitor, Cgd is the parasitic capacitance between the gate and drain terminals, Clc is the capacitance of the liquid crystal capacitor, and ΔVcom is the swing width of the voltage applied to the common electrode.

5 is a waveform diagram illustrating a change in pixel voltage due to a periodic swing common voltage.

As shown in FIG. 5, a voltage applied to a pixel is swinged by swinging a common electrode voltage in a waveform diagram showing voltages applied to a pixel. In this case, the average voltage Vp applied to the pixel is as shown in Equation 1 above.

에 비례하는 값이므로 액정 캐패시터(Ccl)에 의한 메모리 효과에 의해 계조가 변화될 때 오버슈트(overshoot)가 발생하여 응답 속도를 향상시킬 수 있게 된다.As in Equation 1, the voltage additionally applied to the common electrode is

Since the value is proportional to, overshoot occurs when the grayscale is changed by the memory effect of the liquid crystal capacitor Ccl, thereby improving the response speed.

In order to apply the above method, if all three conditions are satisfied, the response speed of the liquid crystal display may be improved.

(Iii) Condition 1.

When the pixel voltage changes from negative polarity to positive polarity, the common electrode voltage terminates with negative polarity at the gate-on time.

(Ii) condition 2.

When the pixel voltage changes from positive polarity (+) to negative polarity (-), the common electrode voltage ends with positive polarity at the gate-on time.

(Iii) Condition 3.

After the gate is closed, swing the negative (-) and positive (+) repeatedly.

On the other hand, the amount of overshoot generated due to the liquid crystal capacitor Clc is given as follows.

First, when the capacitances of the liquid crystal capacitors Clc are Clc1 and Clc2 when the first gray state changes from the second gray state, the value of the second right term in Equation 1 corresponds to the overshoot in each state. Equation 2 to be described below.

The overshooting amount in Equation 2 serves as an absolute factor in improving the response speed. By the way, various capacitances can be changed through the design to some extent, but the width of the change is limited for the characteristics of the panel.

Therefore, in order to amplify the overshoot amount, the swing width ΔVcom of the common electrode voltage must be amplified. However, when Vs is 0 in Equation 1, the second right term should be smaller than the threshold voltage Vth of the liquid crystal. Therefore, the swing width ΔVcom of the common electrode voltage is limited.

This is because, in the dot inversion driving, when 0 V is applied to the pixel based on the upper common electrode, the voltage induced due to the swing of the independent common electrode voltage must be smaller than the threshold voltage Vth of the liquid crystal in order to become black. .

이다. In other words,

to be.

의 조건을 만족해야 하므로, 결국 상기한 수학식 2에서 오버 슈트되는 양은 제한된다. 예를 들어 Clc1=0.5Cst인 경우에는 Cgs는 무시하고, Vth=1.6V일 때, 상기한 수학식 2에서 오버 슈트되는 전압의 크기는 최고 0.4V 정도이다.therefore,

Since the condition must be satisfied, the amount of overshoot in Equation 2 is limited. For example, when Clc1 = 0.5Cst, Cgs is ignored, and when Vth = 1.6V, the voltage overshooted in Equation 2 above is about 0.4V at most.

Since this value is the magnitude of the moving value between 1 and 64 gray levels, the amount of overshoot is smaller when moving between grays at the low gray level. In practice, this value is impossible to reduce the response time between grayscales to 20 msec or less.

Therefore, the overshoot size of Equation 2 needs to be larger in order to fully realize the high-speed response using the swing multi common capacity.

Then, the reason why the size of the swing width ΔVcom of the common electrode voltage is limited in Equation 2 will be described in more detail with reference to FIG. 6.

FIG. 6 is a diagram for explaining a VT curve converted by swing width amplification of a common electrode voltage.

As shown in FIG. 6, when the voltage does not swing the voltage of the storage common electrode, it moves along the normal VT curve, but the VT curve is left as the swing width ΔVcom of the common electrode voltage is amplified. Go to.

The reason is that there is a voltage added in Equation 1, Vs, which is added as a common swing. Therefore, even if the same voltage is applied, if the swing width ΔVcom of the common electrode voltage is large, the effective voltage applied to the actual pixel becomes larger. As shown in FIG. 6, VT increases as the swing width ΔVcom of the common electrode voltage is amplified. The curve moves to the left.

As shown in FIG. 6, in general, the vertical alignment (VA) mode is ΔV <about 0.5. If it is more than that, the black value cannot be obtained.

This effect is explained on the high voltage driving.

FIG. 7 is a diagram illustrating a relationship between a resistor array and a VT curve in a driving PCB. The first stage of FIG. 7 illustrates a resistor array for gray scale representation on a control PCB. ) VT is shown in the second to fourth stages of FIG.

In the normal driving of the second stage of FIG. 7, the left line represents the (-) side VT curve, the right line represents the (+) side VT curve, and the graph drawn portion is a voltage used for driving.

In the third stage of FIG. 7, the swing width ΔV of the common electrode voltage Vcom is about 5V. As described above with reference to FIG. 6, the overshoot is made the largest using the conventional driving method. to be. In this case, the black part is met at the center part.

By the way, the graph shown in the fourth stage of Figure 7 is the case where the VT is formed beyond the boundary of each other. Applying a voltage in such a structure on the drive can swing the swing width ΔV of the common electrode voltage Vcom to be larger.

In order to realize this, various examples of a resistor array included in a gray voltage generator according to an exemplary embodiment of the present invention will be described.                     

FIG. 8 is a diagram for describing a liquid crystal display for high speed response according to an exemplary embodiment of the present invention.

As shown in FIG. 8, the liquid crystal display device for high-speed response according to an exemplary embodiment of the present invention includes a timing controller 10, a gray voltage generator 20, a driving voltage generator 30, and a gate driver 40. , A data driver 50 and an LCD panel 60.

The timing controller 10 distinguishes R, G, and B data signals R (0: N), G (0: N), and B (0: N) from the graphic controller (not shown) outside the LCD module. The vertical synchronization signal (Vsync), the line distinction signal (Hsync), and the high level signal (DE) and the main clock signal (MCLK) only during the period in which the data is output. Each of them is provided and outputs a digital signal for driving the data driver 50 and the gate driver 40.

In more detail, the timing controller 10 receives the digital data signals R (0: N), G (0: N), and B (0: N) from the graphic controller (not shown). The data driver receives a signal Hstart for input start, a signal LOAD for applying data to the LCD panel 60, and a clock signal HCLK for shifting data in the data driver 50. Output to 50.

In addition, the timing controller 10 may include a vertical line start signal STV that commands the start of the gate on signal, and a gate clock signal Gate clk for sequentially performing the gate on signal on each gate line. Output to.

That is, a digital signal for driving the data driver and the gate driver is generated and output to the corresponding drivers 40 and 50.

The gate driving voltage generator 30 may include a voltage Von for producing a gate-on signal, a voltage Voff for producing a gate-off signal, and a data voltage difference in the LCD panel 60, more specifically, a TFT-LCD panel. The common voltage Vcom serving as a reference is output to the gate driver 40. In the present invention, the application of the common voltage has been described in the gate driving voltage generator, but the application of the common voltage can also be output from other external components.

The gate driver 40 includes a shift register, a level shifter, a buffer, and the like, and receives a gate clock signal Gate clk and a vertical line start signal Vstart from the timing controller 10, and the gate driving voltage generator 30. The voltages Von, Voff, and Vcom are provided to open the path so that voltage values of each pixel on the LCD panel 60 are transferred to the pixels.

The gradation voltage generator 20 is adapted to a digital code value according to the number of bits of RGB data R (0: N), G (0: N), and B (0: N) provided from a graphic controller (not shown). Appropriate gradation voltages (V0, V1, V2, ..., V3n) are generated and provided to the data driver 50, respectively. For example, if R data is applied with 6 bits (R (0: 5)), 2 ⁶ = 64 gradations are produced and R of 64 gradations is represented. Here, the gray voltage generator 20 draws a voltage corresponding to the gray level of the negative side and the positive side VT from the built-in resistor array, and outputs a gray voltage adapted to each gray level to the data driver 50.

The data driver 50 receives R, G, and B digital data (R (0: N), G (0: N), and B (0: N)) from the timing controller 10 and stores the received digital data. When a load signal LOAD for instructing 60 to be applied is applied, the voltage corresponding to each data is selected in association with the gray voltage provided from the gray voltage generator 20 and the data voltage is applied to the LCD panel 60. Pass (V1, V2, V3, ..., Vn).

Further, the data driver 50 outputs data voltages V1, V2, V3, ..., Vn so that the polarities of the pixels arranged on the LCD panel 60 are inverted different from each other in every frame. In this case, the inversion of the pixels so that the polarities are different every frame is due to the general characteristics of the liquid crystal, as is already known.

The LCD panel 60 is formed in n data lines, m gate lines arranged orthogonal to the data lines, and in a predetermined area arranged in a lattice arrangement between the data lines and the gate lines, and one end thereof is connected to the gate lines. And the other end of the pixel electrode connected to the data line, and provided from the data driver 50 as the gate voltages G1, G2,..., Gn provided from the gate driver 40 are applied to the corresponding pixel. In response to the data voltages D1, D2, ..., Dm, the corresponding pixel electrode is driven.

In this case, since the common electrode voltage applied to one end of the pixel electrode is overshooted, the response speed is increased when the gray scale changes due to the memory effect of the liquid crystal capacitor.

As described above, the amplified overshoot amount can be obtained by changing the position of the output voltage drawn from the resistor array included in the gray voltage generator for high-speed driving of the liquid crystal display, and thereby the response speed of the liquid crystal. Can be speeded up.

It is also obvious that the data driver must be modified to receive the output voltage from the resistor array built into the data driver.

Hereinafter, a liquid crystal display and a driving device thereof for high-speed response according to the present invention will be described in detail.

9 is a view for explaining a specific resistor array according to an embodiment of the present invention.

Referring to FIG. 9, a resistor array according to an embodiment of the present invention uses a line of resistor arrays connected in series to change a position of a voltage applied to each gray level.

10 is a view for explaining a specific resistor array according to another embodiment of the present invention.

Referring to FIG. 10, a resistor array according to another embodiment of the present invention creates a pair of series-connected resistor arrays RA1 and RA2 between 0 volts and 10 volts so that the negative and negative poles (-) in each of them are formed. It is a method to draw and apply the voltage corresponding to the gray level of + T side. For example, the resistor array RA1 draws the negative voltage having the VT curve C1 and the resistor array RA2 draws the positive voltage having the VT curve C2. will be. This method will make it easier to adjust the gamma curve.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. I can understand that you can.

As described above, according to the present invention, the overshoot amount must be amplified for the high speed response of the liquid crystal, and the swing width (ΔVcom) of the common electrode voltage must be amplified to obtain the amplified overshoot amount, but this value is also limited. Therefore, the overshoot amount amplified can be obtained by changing the position of the output voltage drawn out from the resistor array of the gray scale voltage generator and changing the data driver in conjunction with this.

Claims (6)

A plurality of data lines, a plurality of gate lines arranged orthogonally to the data lines, and formed in a predetermined region lattice arranged between the data lines and the gate lines, one end of which is connected to the gate line, and the other end of the data A driving apparatus of a liquid crystal display device comprising a liquid crystal display panel having pixel electrodes connected to a line and invertedly driven so as to have a polarity different from that of a previous frame for each frame. Outputs a first drive signal and a second drive signal according to an image signal applied from the outside, and outputs a third drive signal defining a period and an amplitude according to the vertical sync signal, the horizontal sync signal and the main clock signal applied from the outside. A timing controller; A data driver for outputting an image signal for driving a polarity of a liquid crystal capacitor to the data line based on the first driving signal; A gradation voltage generator for extracting a voltage corresponding to the gradations of the negative side and the positive side VT from the built-in resistor array and outputting a gradation voltage adapted to each gradation to the data driver; A gate driver configured to output a scan signal to a gate line based on the second driving signal; And A driving voltage generator configured to receive a level of the third driving signal and to increase or decrease a level, and output a common electrode voltage swinging at a predetermined cycle to the gate driving voltage to the liquid crystal display panel; Driving device for a liquid crystal display comprising a. The method of claim 1, wherein the gray voltage generator, A drive device for a liquid crystal display device, comprising: a line of resistor arrays connected in series to draw a voltage corresponding to the gray level of the negative side and the positive side VT. The method of claim 1, wherein the gray voltage generator, And a pair of series-connected resistor arrays to draw voltages corresponding to the gray levels of the negative side and the positive side VT. Outputs a first drive signal and a second drive signal according to an image signal applied from the outside, and outputs a third drive signal defining a period and an amplitude according to the vertical sync signal, the horizontal sync signal and the main clock signal applied from the outside. A timing controller; A gradation voltage generator for extracting a voltage corresponding to the gradations of the negative side and the positive side VT from the built-in resistor array and outputting a gradation voltage adapted to each gradation; A data driver outputting an image signal for driving a polarity of a liquid crystal capacitor based on the first driving signal and the gray voltage; A gate driver configured to output a scan signal based on the second driving signal; A driving voltage generator configured to receive the third driving signal to increase or decrease a level, and output a common electrode voltage swinging at a predetermined cycle with a gate driving voltage; And A plurality of data lines for transmitting the image signal, a plurality of gate lines orthogonal to the data lines, and a scan signal, and a predetermined region formed in a lattice arrangement between the data lines and the gate lines, one end of which is A liquid crystal display panel connected to a gate line and having a pixel electrode connected to the data line at the other end thereof, and being inverted so as to have a polarity different from that of the previous frame for each frame; Liquid crystal display comprising a. The method of claim 4, wherein the gray voltage generator, A liquid crystal display device comprising a line of resistor arrays connected in series to draw a voltage corresponding to the gray level of the negative side and the positive side VT. The method of claim 4, wherein the gray voltage generator, And a pair of series-connected resistor arrays to draw a voltage corresponding to the gray level of the negative side and the positive side VT.

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