KR100772692B1 - Cell structure of ferroelectric memory device and fabricating method of the same - Google Patents

Abstract

The present invention uses the top and three sides instead of the top and four sides of the ferroelectric memory capacitor, and the other side is used as a space for the cell plate line, thereby reducing cell size and processing margins. In order to provide a cell of a ferroelectric memory capable of securing the cell of the ferroelectric memory of the present invention, a plurality of lower electrodes arranged in a first direction, one side of the plurality of lower electrodes are simultaneously opened and the plurality of The other portion of the lower electrode of the ferroelectric memory includes a module consisting of one upper electrode corresponding to the plurality of lower electrodes so as to cover at the same time, the module is a plurality of capacitor modules arranged in a second direction crossing the first direction Element.

Ferroelectric, cell, lower electrode, upper electrode, capacitor

Description

Ferroelectric memory cell and manufacturing method thereof {Cell structure of ferroelectric memory device and fabricating method of the same}             

1A is a plan view showing a cell of a conventional ferroelectric memory.

Fig. 1B is a sectional view showing a cell of a ferroelectric memory according to the prior art.

2 is a plan view showing a ferroelectric memory cell according to an embodiment of the present invention.

FIG. 3A is a cross-sectional view taken along the line XX 'of FIG.

Fig. 3B is a sectional view showing the Y-Y 'cross section of Fig. 2;

4A-4C are cross-sectional views of a ferroelectric memory cell formation process in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21: contact plug

22: lower electrode

23: ferroelectric

24: upper electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory (FeRAM), and more particularly, to a cell having an upper electrode for driving a cell of a three-dimensional structure used in a ferroelectric memory, and a manufacturing method thereof.

FeRAM is a kind of non-volatile memory device that not only stores the stored information even when the power is cut off, but also its operation speed is comparable to the conventional Dynamic Random Access Memory (DRAM). non-volatile) FeRAM is a device that stores information by defining "0" and "1" according to its direction by using the property of ferroelectric material that residual polarization exists and its direction can be reversed even if the electric field is removed. . The FeRAM cell consists of a word line, a bit line, a ferroelectric capacitor, and a transistor, and has a structure similar to that of a conventional DRAM.

On the other hand, in the FeRAM cell, the dielectric layer of the information storage capacitor is generally made of ferroelectric, and ferroelectric materials such as Pb (Zr, Ti) O ₃ (PZT) and SrBi ₂ Ta ₂ O ₉ (SBT) are used as the ferroelectric. As the electrode, noble metals (Novel Metal) such as Pt, Ru, Ir, and precious metal oxides such as RuO ₂ and IrO ₂ are used.

In a plug-type DRAM, the upper electrode of the capacitor functions as a cell plate, and the lower electrode serves as a storage node, whereas in a strap-type FeRAM currently used in mass production, the upper electrode is It acts as a storage electrode, and the lower electrode functions as a cell plate. Therefore, in the strap-type FeRAM, the storage electrode and the transistor are interconnected through local interconnection using a metal film in the cell.

In addition, in FeRAM, the cell plate may be driven depending on the driving method, so that the cell plate may be divided to selectively drive only a part of the cell plate for fast driving. All of these are driven. Therefore, one of the upper and lower electrodes must be formed in a line to be connected to the driving circuit in the peripheral circuit.

1A is a plan view showing a cell of a conventional ferroelectric memory. Fig. 1B is a sectional view showing a cell of a ferroelectric memory according to the prior art.

Referring to FIG. 1B, after depositing the interlayer insulating layer 10 on the substrate 100 having a predetermined process, a contact plug 11 connecting the lower electrode 12 and the active region is formed. Thereafter, the lower electrode 12 and the ferroelectric 13 are deposited and selectively etched by physical vapor deposition or chemical vapor deposition. Subsequently, the upper electrode 14 is deposited by physical vapor deposition or chemical vapor deposition.

In the case of DRAM, the upper electrodes are patterned largely by block rather than by lines, and connected by voltage. However, in the case of ferroelectric memories, the upper electrodes must be separated by lines to separate the upper electrodes.                         

Therefore, when setting the cell design rule, the space between the lower electrodes should be determined in consideration of the thickness of the upper and lower electrodes, the thickness of the ferroelectric, and the space required to separate the upper electrodes. In the case of a highly integrated ferroelectric memory using a three-dimensional capacitor, the upper and four sides of the lower electrode are used to secure a sufficient amount of charge even in a small area to cope with the reduction of the capacitor size.

In order to pattern the upper electrode covering the lower electrode, sufficient space of the lower electrode should be secured. That is, since the ferroelectric and the upper electrode should be deposited between the lower electrode and the lower electrode, and the upper electrode should be separated, the space between the lower electrodes must be twice the thickness of the ferroelectric plus the upper electrode to separate the upper electrode. It becomes a space. This sufficient space is an obstacle to device integration due to an increase in cell size and a reduction in design rules.

The present invention uses the top and three sides instead of the top and four sides of the ferroelectric memory capacitor, and the other side is used as a space for the cell plate line, thereby reducing cell size and processing margins. An object of the present invention is to provide a cell of a ferroelectric memory.

The cell structure of the ferroelectric memory of the present invention for achieving the above object is a plurality of lower electrodes arranged in a first direction, one side of the plurality of lower electrodes are opened at the same time and the other side of the plurality of lower electrodes cover at the same time And a module including one upper electrode corresponding to the plurality of lower electrodes, and the module includes a ferroelectric memory device, which is a capacitor module arranged in a plurality of second directions crossing the first direction.

The cell manufacturing method of the ferroelectric memory of the present invention comprises the steps of: forming a plug on a substrate having a predetermined process; Forming a lower electrode connected to the plug; Forming a ferroelectric on the lower electrode; Forming an oxide film on one side of the ferroelectric; And forming an upper electrode on an upper side of the ferroelectric and side surfaces of the ferroelectric except for the oxide layer.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. do.

2 is a plan view illustrating a capacitor of a ferroelectric memory device according to an embodiment of the present invention.

As shown in FIG. 2, the plurality of lower electrodes 22 disposed in the first direction and one side of the plurality of lower electrodes 22 are simultaneously opened and the other portions of the plurality of lower electrodes 22 are simultaneously opened. A capacitor module including one upper electrode 24 corresponding to the plurality of lower electrodes 22 is formed to cover the plurality of capacitor modules, and the capacitor modules are arranged to be arranged in a plurality of second directions crossing the first direction. . Here, A, B, and C represent capacitor modules in which ferroelectric cells are connected to one upper electrode 24, respectively. In addition, the X-X 'line shows a 2nd direction, and the Y-Y' line shows a 1st direction.

3A is a cross-sectional view taken along the line X-X 'of FIG. 2, wherein an interlayer insulating layer 20 is formed on a substrate 30 having a predetermined structure, and passes through the interlayer insulating layer 20 to form a lower portion of the capacitor. A contact plug 21 connected to the electrode 22 and a dielectric 23 formed on the lower electrode 22 and an upper electrode 24 covering a portion of the upper and side surfaces of the dielectric 23 are formed.

3B is a cross-sectional view taken along the line Y-Y 'of FIG. 2, wherein an interlayer insulating layer 20 is formed on a substrate 30 having a predetermined structure, and passes through the interlayer insulating layer 20 to form a lower portion of the capacitor. A contact plug 21 connected to the electrode 22, a dielectric 23 formed on the lower electrode 22, and an upper electrode 24 covering the upper portion of the dielectric 23 are formed.

Here, the upper electrode 24 uses only one side of the lower electrode 22 when viewed in the X-X 'direction and uses both sides of the lower electrode 22 when viewed in the Y-Y' direction. Therefore, when viewed in a plan, the upper surface and three sides are used. As shown in FIG. 2B, since only one portion of the contact plug 21 is formed between the lower electrodes of the contact plug 21, the space between the lower electrodes can be reduced than in the related art.

Hereinafter, a description of the manufacturing process of the ferroelectric device according to the present invention will be described in detail with reference to the drawings.

First, as shown in FIG. 4A, an interlayer dielectric (ILD) 20 is formed on a semiconductor substrate 30 on which a manufacturing process of a transistor and a bit line (not shown) is completed. The interlayer insulating layer 20 is etched with a storage node contact mask (not shown) to form a storage node contact hole in which a predetermined surface of the semiconductor substrate 30 is exposed.

Next, after the polysilicon is formed on the interlayer insulating layer 22 including the storage node contact hole, the polysilicon plug is recessed by a predetermined depth by an etch back process to fill a predetermined depth of the storage node contact hole. 21).

Although not shown in the figure, titanium silicide (Ti-silicide) is formed as an ohmic contact layer for improving contact resistance between the polysilicon plug 21 and the lower electrode 22, and the lower portion is formed on the titanium silicide. Titanium nitride (TiN) is formed as a diffusion barrier for preventing mutual diffusion between the electrode and polysilicon. At this time, a chemical mechanical polishing process is performed to bury the titanium nitride in the storage node contact hole.

Next, after the lower electrode conductive film is formed on the interlayer insulating film 20 in which the polysilicon plug 21 is embedded, the lower electrode conductive film is selectively etched to align the polysilicon plug 20 to the adjacent intercell lower electrode ( 22. Isolate.

In this case, platinum (Pt), ruthenium (Ru), iridium (Ir), or a metal oxide thereof deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD) is used as the lower electrode conductive film, or A combination film of these is used, and since the metal and metal oxides have a weak adhesive strength with the interlayer insulating film 20, an adhesion layer such as TiO ₂ may be formed before forming the lower electrode.

Next, after the ferroelectric 23 is deposited on the entire surface including the lower electrode 22, the ferroelectric is selectively etched to leave the ferroelectric 23 on the lower electrode 22. In this case, the ferroelectric 23 uses any one of PZT, SBT, or BLT deposited through any one of chemical vapor deposition or atomic layer deposition (ALD), which has excellent step coverage. . After the etching of the ferroelectric 23, a thermal process for restoring the ferroelectric characteristics of the deteriorated ferroelectric is performed, but a rapid thermal process (RTP) or a furnace heat treatment is performed.

As shown in FIG. 4B, after the oxide film 25 is deposited and planarized on the entire surface including the ferroelectric 23, a photoresist film is coated on the oxide film and patterned by exposure and development to form a photoresist pattern, and the photoresist pattern is etched. The oxide layer 25 is etched with a mask to open the upper electrode region 24 exposing the surface of the ferroelectric 23.

At this time, the oxide film 25 is deposited to a thickness sufficient to cover the lower electrode 22 to a position higher than the lower electrode 22, and the etching of the oxide film 25 is performed so that the entire surface of the ferroelectric 23 is exposed. Rather, one surface of the ferroelectric 25 and a predetermined surface of the adjacent inter-cell interlayer insulating film 20 are biased to be simultaneously exposed.

As shown in FIG. 4C, after depositing the upper electrode conductive layer on the entire surface including the open upper electrode region 24, the upper electrode conductive layer is chemically mechanically polished or etched back until the surface of the oxide layer 25 is exposed. An upper electrode 24 embedded in the electrode region 24 is formed.

Here, the upper electrode 24 uses Pt, Ir, Ru, or Rh, metal oxides thereof, or a laminated film in which these are combined.                     

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The present invention as described above can reduce the size of the cell by reducing the area of the upper electrode of the capacitor of the ferroelectric memory, there is an effect that can secure the lower electrode space and the cell plate line more easily according to the design rule reduced. .

Claims (4)

A plurality of lower electrodes disposed in a first direction; And A module comprising one upper electrode corresponding to the plurality of lower electrodes to open at one side of the plurality of lower electrodes at the same time and cover the other side of the plurality of lower electrodes at the same time And the module is a capacitor module arranged in plural in a second direction crossing the first direction. Forming a plug on a substrate on which a predetermined process is completed; Forming a lower electrode connected to the plug; Forming a ferroelectric on the lower electrode; Forming an oxide film on one side of the ferroelectric; And Forming an upper electrode on an upper side of the ferroelectric and a side of the ferroelectric except for the oxide layer Capacitor manufacturing method of the ferroelectric memory comprising a. The method of claim 2, And the upper electrode is formed using an oxide, a nitride, or a combination thereof. The method of claim 2, The upper electrode is a capacitor manufacturing method of a ferroelectric memory, characterized in that the entire surface of the conductive layer is deposited on the substrate using a method of chemical mechanical polishing or etch back.

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