KR100772136B1 - Fm transmitter - Google Patents

Abstract

The present invention is to provide an FM transmitter that can operate with improved performance while reducing the volume to the maximum. To this end, the present invention uses a carrier signal and a pilot signal for stereo, and combines a light audio signal and a left audio signal. A signal synthesizer for synthesizing and outputting the stereo signal of the signal; A frequency synthesizer for modulating and outputting a stereo signal synthesized by the signal synthesizer to a carrier signal using a reference signal; And a signal generator for generating and providing the pilot signal and the reference signal.

FM transmitter, crystal, oscillator, stereo, interface.

Description

FM transmitter {FM TRANSMITTER}

1 is a circuit diagram showing an integrated circuit for implementing an FM transmitter according to the prior art and external connection elements connected to the integrated circuit.

2 is a basic block diagram for synthesizing a stereo signal of a conventional FM transmitter.

3 is a block diagram showing an FM transmitter according to a preferred embodiment of the present invention.

FIG. 4 is a block diagram showing a first interface section of the frequency combining section shown in FIG.

FIG. 5 is a waveform diagram showing the operation of the first interface unit shown in FIG. 4; FIG.

FIG. 6 is a block diagram showing a second interface section of the frequency combining section shown in FIG.

FIG. 7 is a waveform diagram showing the operation of the second interface unit shown in FIG. 6; FIG.

Explanation of symbols on the main parts of the drawings

100: signal synthesis unit

200: signal generator

300: frequency synthesizer

400: interface circuit

The present invention relates to an FM transmitter for transmitting an audio signal using frequency modulation, that is, FM (Frequency Modulation), and more particularly to an FM transmitter for transmitting an FM stereo signal.

1 is a circuit diagram illustrating an integrated circuit for implementing an FM transmitter according to the related art and an external connection device connected to the integrated circuit.

Referring to FIG. 1, an integrated circuit for implementing an FM transmitter according to the related art generates and outputs a left audio signal input processor 70, a write audio signal input processor 80, a 38 kHz signal and a 19 kHz signal. The left audio signal, the right audio signal, and the first signal generator 50a processed by the first signal generator 50a, the left audio signal input processor 70, and the right audio signal input processor 80 are respectively generated. The stereo signal synthesizing unit 90 for synthesizing the stereo signals using the 38 kHz signal and the 19 kHz signal, the second signal generating unit 50b for generating and outputting the 100 kHz signal, and the second signal generating unit 50. And a frequency synthesizer 60 for synthesizing the generated 100 kHz signal and the signal synthesized by the stereo signal synthesizer 90. Here, the integrated circuit shown in FIG. 1 is implemented as a BiCMOS circuit.

In addition, the FM transmitter includes crystals X2 and capacitors C3 and C4 for connection with the first signal generation unit 50a of the integrated circuit, crystals X1 for connection with the second signal generation unit 50b, and Capacitors C1 and C2 are provided.

In addition, the FM transmitter reduces the output level of the stereo signal output from the integrated circuit to adjust the frequency in response to the signal attenuator (200) for adjusting the FM modulation amount and the signal output from the frequency synthesizer (60) A loop filter 21 for filtering out and a signal synthesizing unit 22 for combining the output signal of the loop filter 21 and the output signal of the signal attenuation block 20 are provided.

In addition, the output signal of the signal synthesizing unit 22 is fed to the frequency synthesizing unit 60 through an LC resonant circuit composed of capacitors C7, C8 and C9, resistor R1, variable diode CD1 and inductor L1. Delivered. Here, the capacitors C5 and C6 are capacitors arranged to block the DC signal.

The left audio signal input processing unit 70 includes a pre-emphasis block 71, a limiter block 72, a low pass filter block 73, and a mute block. Block 74).

The write audio signal input processing unit 80 includes a pre-emphasis block 81, a limiter block 82, a low pass filter block 83, and a mute block. Block 84).

The stereo signal generation unit (Stereo Signal Generation MPX Block) (90) is a signal synthesis block (Adder Block) (91, 94, 96), a subtract block (92), a multiplexer block (Multiplier Block) ( 93, and a signal level modulating block 95 for adjusting the level of the signal.

The frequency synthesizer 60 includes a charge pump block 61, an RF oscillator block 62, an RF amplifier 63, and a phase frequency detection block. (Phase Frequency Detector Block) 64, a Programmable Frequency Divider Block 65, and a Digital Interface Block 66.

The first signal generation unit 50a includes a pilot oscillator block 51, a pilot divider block 52, and a pilot level adjust block 53. .

The second signal generator 50b includes an oscillator block 54 and a clock divider block 55.

2 is a basic block diagram for synthesizing a stereo signal of a conventional FM transmitter.

2 shows a basic block for synthesizing a stereo signal. In order to synthesize a stereo signal, a signal subtractor subtracts a left audio signal and a light audio signal from a first signal synthesizer that sums each other, and a signal output from the signal subtractor. Is mixed with the 38 kHz signal output from the oscillator, a second signal synthesizer for synthesizing the output from the first signal synthesizer and the output from the mixer, and the output of the second signal synthesizer is output from the pilot signal generator. A third signal synthesizer is provided for mixing the signal of 19 kHz and outputting it as a strew signal. Therefore, a pilot signal generator is required to generate a 19khz signal. In general, a 38kHz signal is divided into 1/2 and output.

Here, the signal of 19 kHz is a fixed pilot signal of the FM stereo system and serves as a stereo indicator.

The 38khz signal is also a signal defined in the FM stereo system, and is a carrier signal for the subtraction signal L-R of two audio signals Audio L and Audio R.

 When stereo demodulation in the FM stereo system, the write signal is demodulated by L = {L + R) + (LR)} / 2, and the left signal is R = {L + R)-(LR)} / 2. Demodulate. For reference, the mono mode demodulates only the L + R signal.

At the bottom of Fig. 2 is a graph in the frequency domain showing that the stereo signal is demodulated.

As described in the foregoing description, in order to implement the FM stereo system, the stereo signal synthesizing unit 90 of the FM transmitter according to the related art shown in FIG. 1 is configured by the signal synthesizing blocks 91, 94, and 96, respectively. The first to third signal synthesizers), a signal subtraction block 92 (corresponding to the signal subtractor of FIG. 2), and a multiplexer block 93 (corresponding to the mixer of FIG. 2).

Subsequently, the operation of the conventional FM transmitter shown in FIG. 1 will be described.

First, the left and right audio signals (signals below 15kHz) are input through the L / R input. Send and receive audio signal using FM method In order to improve the signal-to-noise ratio (SNR) of the audio signal, most of the audio signals are de-emphasis processed when received through the pre-amplifier blocks 71 and 81.

The pre-amplification blocks 71 and 81 have a frequency of 20 to 15 kHz and de-emphasis that attenuates the signal to 6 db / Octave from 1 kHz or more with 300 Hz as the maximum point. This is because the audio signal In order to emphasize the frequency band above 1kHz, it intentionally amplifies the audio signal above 1kHz to 6db / Octave. The limiter block 72/82 limits the size of the signal over a certain size so that the signals operate without distortion in the integrated circuit for the FM transmitter.

The low pass filter block 73/83 serves to limit signals other than the frequency band of the audio signal carried on the audio signal. The mute block 74/84 is a block that intentionally removes an audio signal as needed.

Signals transmitted through the write / left audio signal input processing units 70 and 80 are synthesized into stereo signals by the stereo signal synthesizing unit. The signal synthesis block 91 serves to add the right audio signal and the left audio signal.

The signal subtraction block 92 serves to subtract the right audio signal from the left audio signal.

The multiplexer 93 serves to multiply the output of the signal difference block 92 by the 38 kHz signal generated by the first signal generator 50a.

The signal synthesis block 94 adds the output of the signal synthesis block 91 and the output of the multiplexer 93. The signal level adjustment block 95 adjusts the level of the output signal of the signal synthesis block 94.

The signal synthesis block 96 adds an output signal of the signal level control block 95 to a pilot signal of 19 kHz generated by the first signal generator 50a and then outputs the pilot signal.

The first signal generator 50a serves to generate a 38 kHz signal as a reference signal and a 19 kHz signal as a pilot signal.

The pilot oscillator block 51 generates a signal of 38 kHz using a 38 kHz crystal (X2) and capacitors C3 and C4, which are external connection elements of the integrated circuit, and divides the 38 kHz signal into two divisions in the pilot divide block 52. To generate and output a 19 kHz pilot signal.

The pilot level adjustment block 53 adjusts the level of the pilot signal output from the pilot divide block 52.

The signal attenuation block 20 serves to adjust the amount of FM modulation by reducing the level of the output signal of the signal synthesis block 96 which is a stereo signal.

The loop filter block 21 is composed of a low pass filter as a loop filter and filters various noise frequency components generated during the operation of the frequency synthesizer and filters the variable diode. It is composed of capacitors, variable diodes and inductors (C7, C8, C9, L1, CD1), which are external devices, as they change the voltage of the negative pin of (CD1). It serves to vary the frequency of the RF oscillator block 62 composed of an LC resonance circuit and a voltage control oscillator (VCO).

The signal synthesizer 22 adds the output of the loop filter block 21 and the output of the signal attenuation block 20 to perform FM modulation of the RF oscillator block 62.

Capacitors C5 and C6 remove the DC component of the stereo signal output from the stereo signal synthesizing unit 90.

The oscillator block 54 of the second signal generator 50b generates a 7.2 MHz signal using a crystal X1 for 7.2 MHz and capacitors C1 and C2 which are external devices.

The clock divide block 55 divides the 7.2 MHz signal generated by the oscillator block 54 into 72 to generate a reference clock of 100 kHz, and outputs it to the phase frequency detection block 64.

The RF oscillator block 62 serves to generate an RF signal (70 to 120 MHz), and the RF amplification block 62 adjusts the level of the RF signal by amplifying the RF signal and outputting it to the outside.

The phase frequency detection block 64 is a block for sensing the phase and the frequency of the signal, and outputs the 100 kHz reference clock and the programmable frequency divide block 65 which are the outputs of the clock divide block 55 of the second signal generator 50b. The signals are compared and the pulse train corresponding to the difference is sent to the charge pump 61.

The programmable frequency divide block 65 receives a signal from the digital interface block 66 and divides the RF signal output from the RF oscillator block 62.

The digital interface block 66 sets an RF frequency by externally input data and interfaces with an external device in a 3-wire manner.

As described above, each block shown in FIG. 1 operates to transmit an FM stereo signal.

Here, the FM transmitter according to the prior art arranges two crystals as an external device of an integrated circuit for internal operation, which increases the overall volume of the FM transmitter.

Crystals are relatively bulkier than integrated circuits, especially for low-frequency 38khz crystals.

Therefore, as in the prior art, the FM transmitter is very difficult to miniaturize. In particular, in recent years, the FM transmitter is used in a large number of portable, such as MP3 players, mobile phones and navigators, there are many problems because the FM transmitter can not be miniaturized.

The present invention has been proposed to solve the above problems, and an object thereof is to provide an FM transmitter capable of operating with improved performance while reducing volume to the maximum.

According to another aspect of the present invention, there is provided a signal synthesizing unit for synthesizing a light audio signal and a left audio signal into a single stereo signal using a stereo carrier signal and a pilot signal; A frequency synthesizer for modulating and outputting a stereo signal synthesized by the signal synthesizer to a carrier signal using a reference signal; And a signal generator for generating and providing the pilot signal and the reference signal, the signal generator including an oscillator for generating and outputting a first preliminary signal using a crystal, and dividing the first preliminary signal by a second. A first divider for generating a preliminary signal, a second divider for dividing the second preliminary signal to output the reference signal, and a divider for the second preliminary signal to output the stereo carrier signal Third divider; And a fourth divider for dividing the stereo carrier signal and outputting the pilot signal, and a level adjuster for adjusting and outputting the level of the pilot signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3 is a block diagram showing an FM transmitter according to a preferred embodiment of the present invention.

Referring to FIG. 3, the FM transmitter according to the present embodiment uses a stereo carrier signal (38 kHz) and a pilot signal (19 kHz) to output a single audio signal R and a left audio signal L from one stereo signal. Frequency for synthesizing the stereo signal synthesized by the signal synthesizing unit 100 using the signal synthesizing unit 100 for synthesizing and outputting the signal and the reference signal (100 kHz) to a carrier signal and outputting the output signal as an RF signal. The synthesizer 300 includes a signal generator 200 for generating and providing a pilot signal (19 kHz) and a reference signal.

The signal synthesizing unit 100 receives the light audio signal R, receives the light audio signal processor 120 for removing noise, and transmits the left audio signal L. The left audio signal L receives the left audio signal L, and removes the noise. A frame for synthesizing a stereo signal using the light audio signal L and the left audio signal R processed by the signal processor 110, the light audio signal processor 110, and the left audio signal processor 120, respectively. The Leo signal synthesizing unit 130 is provided.

The stereo signal synthesizing unit 130 includes a first signal synthesizing block 131 for outputting the sum of the right audio signal L and the left audio signal R, and the right audio signal R and the left audio signal L. A signal decrement block 132 for outputting the difference value LR, a multiplexer 133 for multiplying the output of the signal decrement block 132 by a strain carrier signal (38 kHz), and an output of the multiplexer 133 And a signal synthesis block 134 for summing and outputting the outputs of the signal synthesis block 131, a mute block 135 for outputting to remove a selected portion of the signal output from the signal synthesis block 134, and mute. And a signal synthesis block 136 for combining the output of the block 135 with the output of the pilot signal (18 kHz) and outputting it as a stereo signal.

The write audio signal processor 120 may include a pre-emphasis block 121 for pre-emphasis processing of the input write audio signal R and a signal level of a predetermined magnitude or more among the signals output from the pre-emphasis block 121. Limiter block 122 for limiting the output and the low-pass filter block 123 for limiting and outputting signals other than the frequency band in which the audio signal of the output of the limiter block 122.

The left audio signal processor 110 may include a pre-amplification block 111 for pre-emphasis processing of the left audio signal L and a signal level of a predetermined size or more among the signals output from the pre-emphasis block 111. Limiter block 112 for limiting the output and the low-pass filter block 113 for limiting and outputting signals other than the frequency band in which the audio signal of the output of the limiter block 112.

The signal generator 200 uses the oscillator 210 to generate and output a preliminary signal (19 MHz) using a crystal, and divides the preliminary signal (19 MHz) by 5 to generate a preliminary signal (3.8 MHz). The frequency divider 220 divides the preliminary signal (3.8MHz) by 38 and outputs the reference signal (100kHz), and divides the preliminary signal (3.8MHz) by 100 and the carrier signal for the stereo (38kHz). The frequency divider 240 for outputting the signal, the frequency divider 250 for outputting the pilot signal (19 kHz) by dividing the carrier signal for stereo, and the level adjuster for adjusting and outputting the level of the pilot signal (19 kHz). 260.

Therefore, the crystal (X11) uses a crystal for 19MHz.

In addition, although a crystal for 19 MHz is used here, any crystal that can multiply or divide by an integer multiple of 19 MHz can be used to generate a reference signal of 100 kHz, a pilot signal of 19 kHz, and a carrier signal of 38 kHz.

For example, the above-described signal generation unit can be configured using crystals such as 4.75Mhz, 9.5Mhz, 19Mhz, 38Mhz, 76MHz.

In addition, the oscillator 210 further includes two capacitors C11 and C12 at both ends of the crystal X11 to stably generate a preliminary signal of 19 MHz.

The frequency synthesizer 300 maintains the output level of the stereo signal output from the signal synthesis block 136 so as not to exceed a predetermined size and outputs the signal attenuation block 360 and the frequency of the modulated signal to be applied. A voltage controlled oscillator 340 for outputting an RF signal, an RF amplifier 350 for adjusting the level of the RF signal output by the voltage controlled oscillator 340 and outputting it to the outside, and a voltage controlled oscillator The programmable frequency divide block 310 for dividing the frequency of the RF signal output from the 340 into a frequency corresponding to the digital control code, and the divided signal and the reference signal (100 kHz) output from the frequency divide block 310. Compared with the phase frequency detector 320 for outputting the pulse corresponding to the difference and the pumping of charge in response to the pulse output from the phase frequency detector 320 The filter 330, a loop filter 370 consisting of a low pass filter to remove and output noise components of the output of the charge pump 330, and the output of the signal attenuation block 360 and a low pass filter A signal synthesis block 380 for synthesizing the output of the loop filter 370, a signal synthesis block 380, and an LC resonant circuit 390 disposed between the voltage control oscillator 340.

As shown in FIG. 3, the LC resonant circuit 390 includes a resistor R11, capacitors C15, C16, and C17, a variable diode CD11, and an inductor L11.

The LC resonant circuit 390, the signal attenuation block 360, the loop filter 370, and the signal synthesis block 380 are all external elements of the integrated circuit. Is implemented in a chip for the FM transmitter. For reference, the capacitors C13 and C14 are capacitors arranged to block a DC signal.

In addition, the oscillator 210 also outputs a preliminary signal (19 MHz) by using crystals X11 and capacitors C11 and C12 that are external devices.

On the other hand, the FM transmitter according to the present embodiment is an interface for receiving a digital control signal (CE, DA, CK) for determining the frequency of the carrier used in the frequency synthesizer 300 and transmits it to the frequency synthesizer 300 The circuit unit 400 is further provided.

The interface circuit 400 receives the enable signal CE, the data signal DA, and the clock signal CK, and includes a first interface circuit 410 for outputting a digital control signal, a data signal DA, and a clock. And a second interface circuit 420 for receiving the signal CK and outputting a digital control signal.

FIG. 4 is a block diagram showing a first interface unit of the frequency combining unit shown in FIG.

The first interface circuit 410 is configured to shift a plurality of shift registers for shifting the data signal DA in synchronization with the clock signal CK, and is enabled for the enable signal CE to correspond to the plurality of shift registers. And a plurality of D flip-flops for storing the data signals stored in the corresponding shift registers and then outputting them as digital control signals D <7: 0>.

FIG. 5 is a waveform diagram illustrating an operation of the first interface unit illustrated in FIG. 4.

The first interface circuit 410 is interfaced by using a 3-wire method. The data signal DA is stored in the shift register in synchronization with a clock and stored in the D flip-flop according to the enable signal. The control code is then output to the programmable frequency divide block 310.

The programmable frequency divide block 310 divides the frequency to be modulated to a frequency corresponding to the input control code.

FIG. 6 is a block diagram illustrating a second interface unit of the frequency combining unit shown in FIG.

The second interface circuit 420 is a combination of a clock signal CK and a data signal and an address and start / end signal recognition block for detecting and outputting the start and end of data, and the data signal in synchronization with the clock signal CK. A plurality of shift registers for shifting DA and activated in response to a signal detecting the start and end of data output from the recognition block, corresponding to the plurality of shift registers, and the data stored in the corresponding shift register. A plurality of flip-flops are provided for storage and output as digital control signals.

FIG. 7 is a waveform diagram illustrating an operation of the second interface unit illustrated in FIG. 6.

The second interface circuit 420 interfaces with two lines. The second interface circuit 420 recognizes the start and the end of the data in the recognition block according to a specific pattern of the data signal and the clock.

The data is received and sorted according to a signal indicating the start and end of the data recognized by the recognition block, and then the control code is output to the programmable frequency divide block 310.

The programmable frequency divide block 310 divides the frequency to be modulated to a frequency corresponding to the input control code.

Hereinafter, the operation of the FM transmitter according to the present embodiment will be described in detail with reference to FIGS. 3 to 7.

The audio signal (signal below 15 kHz) is first input to the left and right audio signal input processing units 110 and 120 of the FM transmitter.

Send and receive audio signals using FM In order to improve the signal-to-noise ratio (SNR) characteristics of most audio signals, pre-emphasis is performed during transmission and de-emphasis is performed during reception.

The pre-amplification blocks 111 and 121 have an audio signal having a frequency of approximately 20 to 15 kHz. De-emphasis is attenuated to 6db / Octave from 1kHz or higher with 300Hz as the maximum point. In order to emphasize the frequency band above 1kHz, it intentionally amplifies the audio signal above 1kHz to 6db / Octave.

The limit blocks 112 and 122 serve to limit the level of the signal over a predetermined size so as to operate without distortion of the signal inside the IC of the FM transmitter.

The low pass filter blocks 113 and 123 serve to limit signals other than the frequency band in which the audio signal is carried.

The stereo signal synthesizing unit 130 serves to create a stereo signal using the light audio signal R and the left audio signal L. FIG.

The signal synthesis block 131 serves to add the right audio signal R and the left audio signal L. FIG. The signal subtraction block 132 serves to subtract the right audio signal L from the left audio signal R.

The multiplexer 133 multiplies the output of the signal subtraction block 132 by a 38 kHz stereo carrier signal (38 kHz).

The signal synthesis block 134 adds the output of the signal synthesis block 131 and the output of the multiplexer 133. The mute block 135 intentionally removes the audio signal as necessary. The signal synthesis block 136 adds a 19 kHz pylon signal to the output signal of the mute block 135.

The signal generator 200 generates a reference signal (100 kHz), a pilot signal (19 kHz), and a stereo carrier signal (38 kHz).

First, the oscillator 210 of the signal generator 200 generates a 19 MHz preliminary signal (19 MHz) by using a crystal (X11), which is an external device of the FM transmitter IC, and capacitors (C11, C12).

The divider 220 divides a 19 MHz preliminary signal (19 MHz) into 5 to generate a 3.8 MHz preliminary signal (3.8 MHz). The divider 230 divides the 3.8 MHz preliminary signal (3.8 MHz) into 38 to generate a 100 kHz reference signal (100 kHz). The divider 240 divides the 3.8 MHz preliminary signal (3.8 MHz) into 100 to generate a 38 kHz strain carrier signal (38 kHz).

The divider 250 divides the 38 kHz strain carrier signal (38 kHz) into two to generate a 19 kHz pilot signal (19 kHz). The level adjuster 260 adjusts the level of the pilot signal 19khz.

The operation of the frequency synthesizer 300 will now be described.

The charge pump 330 of the frequency combiner 300 pumps or sinks an amount of current proportional to the pulse width of the signal output from the phase frequency detector 320.

The voltage controlled oscillator 340 serves to generate an RF signal having 70 to 120 MHz. The RF amplifier 350 adjusts and outputs a level of the RF signal output from the voltage controlled oscillator 340.

The phase frequency detector 320 compares the reference signal of 100 kHz with the output signal of the programmable frequency divider 310 and sends a pulse corresponding to the difference to the charge pump 330.

The programmable frequency divider 310 receives a control code output from the first interface circuit 410 or the second interface circuit 420 and divides the output of the RF signal of the voltage control oscillator.

The first interface circuit 410 serves to set the RF frequency by receiving data transmitted from the outside and uses a 3-wire method.

The second interface circuit 420 also sets an RF frequency by externally input data and interfaces with the outside through an IIC scheme, that is, two lines.

Thus, two interface circuits are provided to enable various interfacing when the FM transmitter of the present invention is applied to another system (for example, MP3, portable or car music device, portable horn, PDA, navigator, etc.). Interfacing of the MPU of the devices to be applied may be usefully interfacing when the IIC, that is, the two-line interfacing method.

In addition, if the IIC type interface is provided, the pin to which the enable signal is input can be reduced.

The attenuation block 360 disposed outside the IC for the FM transmitter serves to adjust the amount of FM modulation by reducing the level of the output signal of the signal synthesis block 136 which is a stereo signal.

The loop filter 370 is configured as a low pass filter. Capacitors, resistors, and inductors (C15, C16, C17, L11) are used to filter out various noise frequency components that occur during the frequency modulation operation and to vary the voltage applied to the negative pin of the variable diode (CD11). Together with the LC resonant circuit 390 composed of CD11, the frequency control oscillator 340 serves to vary the frequency.

The signal synthesis block 380 performs the FM modulation of the voltage controlled oscillator by adding the output of the loop filter 370 and the output of the attenuation block 360. The capacitors C13 and C14 remove the DC component of the signal.

As described above, the biggest feature of the FM transmitter according to the present invention is to generate all the signals required for FM modulation of the stereo signal by using a single signal generator, unlike one using two crystals externally You will have a crystal.

Therefore, the present invention requires only two capacitors arranged on both sides of the crystal. In particular, since the crystal for low frequency is very bulky, it has been difficult to miniaturize the FM transmitter using a low frequency crystal in the related art. However, in the present invention, the size of the FM transmitter becomes very easy by using one crystal, especially a high frequency 19 MHz crystal. .

In addition, by using only one crystal, two pins of the IC for the FM transmitter can be saved, and various circuits connected to the two crystals (51, 52, and 53 of FIG. 1) can be omitted. The circuit area can also be reduced.

In addition, the second feature of the FM transmitter of the present invention is that by placing a mute block in the stereo signal synthesizing unit 130, which is conventionally disposed in the light and left audio signal input processing units, only one mute block is needed, thereby reducing the area of the circuit. It is possible to reduce, resulting in various costs.

A third characteristic of the FM transmitter according to the present invention is a signal level control block function (see 95 in FIG. 1) and a signal attenuation function (see 20 in FIG. 1) which are conventionally used in a stereo signal synthesis unit. 360) is in charge.

Therefore, the circuit part responsible for the signal level control block function (refer to 95 in FIG. 1) used in the stereo signal synthesizing part can be omitted, thereby reducing the area of the circuit, thereby reducing various costs. .

The fourth feature of the FM transmitter of the present invention is a three-wire interface circuit 410 and a two-line interface to enable the interfacing method using IIC, which is a signal interfacing method of MPUs of devices to which the FM transmitter is recently applied. All circuits 420 are provided.

If the two-line interface circuit 420 is used, one external input pin of the integrated circuit for the FM transmitter can be saved.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

By constructing the FM transmitter in the same structure as the present invention, the external and internal elements of the FM transmitter IC can be greatly reduced, thereby reducing the manufacturing development cost of the product and greatly reducing the volume of the manufactured FM transmitter.

Claims (17)

A signal synthesizing unit for synthesizing the light audio signal and the left audio signal into one stereo signal and outputting the same using a stereo carrier signal and a pilot signal; A frequency synthesizer for modulating and outputting a stereo signal synthesized by the signal synthesizer to a carrier signal using a reference signal; And And a signal generator for generating and providing the pilot signal and the reference signal. Signal generator, An oscillator for generating and outputting a first preliminary signal using a crystal, a first divider for dividing the first preliminary signal to generate a second preliminary signal, and dividing the second preliminary signal to divide the reference signal A second divider for outputting a second divider, and a third divider for dividing the second preliminary signal to output the stereo carrier signal; And a fourth divider for dividing the stereo carrier signal to output the pilot signal, and a level adjuster for adjusting and outputting the level of the pilot signal. The method of claim 1, The signal synthesis unit A light audio signal processor for receiving the light audio signal and removing the noise; A left audio signal processor for receiving the left audio signal and removing the noise; And And a stereo signal synthesizing unit for synthesizing a stereo signal using the right audio signal and the left audio signal processed by the right audio signal processor and the left audio signal processor. The method of claim 2, The stereo signal synthesizing unit A first signal synthesis block configured to output the sum of the right audio signal and the left audio signal; A signal difference block for outputting a difference value between the write audio signal and the left audio signal; A multiplexer for multiplying and outputting the output of the signal difference block with the strain carrier signal; A second signal synthesizing block configured to sum the output of the multiplexer and the output of the signal synthesis block and output the sum; A mute block for outputting to remove a selected portion of the signal output from the second signal synthesis block; And And a third signal synthesizing block for adding the output of the mute block and the output of the pilot signal to output a stereo signal. The method of claim 3, wherein The light audio signal processor A pre-emphasis block for pre-emphasis processing of the input light audio signal; A limiter block for restricting and outputting a level of a signal of a predetermined size or more among the signals output from the pre-amplification block; And And a low pass filter block for limiting and outputting signals other than a frequency band in which an audio signal is output among the outputs of the limiter block. The method of claim 3, wherein The left audio signal processor A pre-emphasis block for pre-emphasis processing of the input left audio signal; A limiter block for restricting and outputting a level of a signal of a predetermined size or more among the signals output from the pre-amplification block; And And a low pass filter block for limiting and outputting signals other than a frequency band in which an audio signal is output among the outputs of the limiter block. delete The method of claim 1, The crystal is And a crystal capable of multiplying or dividing 19Mhz by an integer multiple to generate the reference signal, the pilot signal and the carrier signal for the stereo. The method of claim 7, wherein The crystal is An FM transmitter using either a crystal for 4.75 MHz, a crystal for 9.5 MHz, a crystal for 19 MHz, a crystal for 38 MHz or a crystal for 76 MHz. The method of claim 7, wherein The first divider is And distributing the first preliminary signal of 19 MHz for 5 minutes to output the second preliminary signal of 3.8 MHz. The method of claim 9, The second divider is And dividing the second preliminary signal at 3.8 MHz by 38 to output the reference signal at 100 kHz. The method of claim 10, The third divider is And dividing the second preliminary signal at 3.8 MHz for 100 to output the carrier signal for stereo at 38 kHz. The method of claim 11, The fourth divider is FM transmitter, characterized in that for dividing the carrier signal for 38kHz 2 kHz to output the pilot signal of 19kHz. The method of claim 1, And an interface circuit unit for receiving a digital control signal for determining a frequency of a carrier wave used in the frequency synthesizer and transmitting the received digital control signal to the frequency synthesizer. The method of claim 13, The interface circuit portion A first interface circuit configured to receive an enable signal, a data signal, and a clock signal and output the digital control signal; And And a second interface circuit for receiving a data signal and a clock signal and outputting the digital control signal. The method of claim 14, The first interface circuit A plurality of shift registers for shifting the data signal in synchronization with the clock signal; And And a plurality of flip-flops enabled for the enable signal and corresponding to the plurality of shift registers, the plurality of flip-flops for storing the data signals stored in the corresponding shift registers and outputting the data signals as the digital control signals. transmitter. The method of claim 14, The second interface circuit A recognition block for detecting and outputting a start and an end of data by combining the clock signal and the data signal; A plurality of shift registers for shifting the data signal in synchronization with the clock signal; And It is activated in response to the detection of the start and end of the data output from the recognition block, corresponding to the plurality of shift registers, and for storing the data signal stored in the corresponding shift register and outputting the digital control signal An FM transmitter comprising a plurality of flip-flops. The method of claim 3, wherein The frequency synthesizer A signal attenuation block for maintaining the output level of the stereo signal output from the third signal synthesis block so as not to be greater than or equal to a predetermined magnitude; A voltage controlled oscillator for varying a frequency of an applied modulated signal and outputting an RF signal; An RF amplifier outputting the RF signal output by the voltage controlled oscillator to the outside by adjusting a level; A programmable frequency divide block for dividing a frequency of an RF signal output from the voltage controlled oscillator into a frequency responsive to a digital control code; A phase frequency detector for comparing the divided signal output from the frequency divide block with the reference signal and outputting a pulse corresponding to the difference; A charge pump pumping charges in response to the pulses output from the phase frequency detector; A loop filter for removing and outputting a noise component of an output of the charge pump; A signal synthesis block for synthesizing the output of the signal attenuation block and the output of the loop filter; And And an LC resonant circuit disposed between the signal synthesis block and a voltage controlled oscillator.

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