KR100771623B1 - Apparatus and method for decoding and processing image - Google Patents

Abstract

Disclosed are an apparatus and a method for decoding and processing an image. The apparatus decodes the compressed input video in response to the decoding synchronization signal, processes the video decoding unit for outputting the decoded video at the first frame rate, and the decoded video input from the video decoding unit in response to the clock signal. And a video processor configured to output the processed result at a second frame rate and to generate a decoded synchronization signal by using the clock signal frequency and the first frame rate. Therefore, the decoding synchronization signal synchronized to the first frame rate can be generated using the frequency of the clock signal without adverse effects of inverting the field, and is suitable to be implemented in hardware, and performs the decoding operation using the generated decoding synchronization signal. Therefore, the video signal can be decoded more accurately.

VDP, VDEC, Frame Rate

Description

Apparatus and method for decoding and processing image

1 is a block diagram of an embodiment of an image decoding and processing apparatus according to the present invention.

FIG. 2 is a block diagram of an embodiment according to the present invention of the image processing unit shown in FIG. 1.

3 is a waveform diagram illustrating one mode of a decoding synchronization signal.

4 is a waveform diagram showing another embodiment of the decoding synchronization signal.

5 (a) and 5 (b) are waveform diagrams illustrating still other aspects of the decoding synchronization signals.

6 is a block diagram of another embodiment according to the present invention of the image processor shown in FIG. 1.

7A and 7B are waveform diagrams each illustrating a display synchronization signal and a decoding synchronization signal, respectively.

8 is a flowchart for explaining an embodiment of an image decoding and processing method according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to image processing performed in digital television (DTV), and more particularly, to an apparatus for decoding and processing an image in a situation where a frame rate for decoding an image and a frame rate for processing an image are different from each other It is about a method.

Compressed images, i.e., digital video, are converted into liquid crystal (LCD) (not shown), plasma display panels (PDP) (not shown), cathode ray tubes (CRT), etc. In order to display on a display device, a video decoder (VDEC: Video DECoder) (not shown) and a video signal processor (VDP: Video Display Processor) are required.

The VDEC decodes the compressed video and delivers it to the VDP. The VDEC processes an input video signal and provides it to a display device. At this time, if the frame rate of the input video provided from the VDEC and the frame rate of the output video provided from the VDP to the display device are different from each other, the frame rate of the input video is set to the frame rate of the output video. There is a need for converting frame rates to fit.

An object of the present invention is to provide an image decoding and processing apparatus and method for decoding an image using a decoding synchronization signal generated according to a frame rate of an input video when a frame rate of an input video and a frame rate of an output video are different from each other. To provide.

According to an aspect of the present invention, there is provided an apparatus for decoding and processing an image, including: an image decoder configured to decode a compressed input image in response to a decoding synchronization signal, and output the decoded image at a first frame rate; And processing the decoded image input from the image decoder in response to a clock signal, and outputting the processed result at a second frame rate, and using the frequency of the clock signal and the first frame rate to decode the decoded synchronization signal. Preferably, the image processing unit generates and generates the display synchronization signal according to the second frame rate.

In addition, the image decoding and processing method according to the present invention comprises the steps of: generating a decoding synchronization signal using the frequency and the first frame rate of the clock signal; Decoding a compressed image using the decoding synchronization signal and providing a decoded image at the first frame rate; And processing the decoded image provided at the first frame rate according to the clock signal, and providing a processed result at a second frame rate, and displaying a display synchronization signal according to the provided second frame rate. Generating and processing the decoded image according to the display synchronization signal.

Hereinafter, the configuration and operation of an embodiment of an image decoding and processing apparatus according to the present invention will be described with reference to the accompanying drawings.

1 is a block diagram of an embodiment of an image decoding and processing apparatus according to the present invention, and includes an image decoding unit 10 and an image processing unit 12.

The image decoder 10 illustrated in FIG. 1 inputs a compressed image through the input terminal IN1, decodes the compressed input image in response to the decoding synchronization signal 14 input from the image processor 12, and decodes the image. The outputted image is output at a first frame rate. Here, the image input through the input terminal IN1 may be an image compressed by an MPEG-2 bit stream, H.264 or DivX, and the image decoder 10 plays a role corresponding to the above-described VDEC.

The image processor 12 processes the decoded image input from the image decoder 10 in response to the clock signal CLK, and processes the processed result to the display unit (not shown) through the output terminal OUT1 at a second frame rate. Output Here, the display unit (not shown) may be an LCD, a PDP or a CRT, and the image processor 12 plays a role corresponding to the above-described VDP. At this time, the image processor 12 generates a decoded synchronization signal using the frequency (pulse / sec) of the clock signal CLK and the first frame rate, and generates the decoded synchronization signal 14 from the image decoder 10. ) Here, the decoding synchronization signal generated by the image processing unit 12 is a kind of field sync signal, which is a reference when decoding the image compressed by the image decoding unit 10 as described above.

The image decoded by the image decoder 10 is not directly provided to the image processor 12 as illustrated in FIG. 1, and unlike the example illustrated in FIG. 1, the image decoded by the image decoder 10 is stored in memory (not shown). It may be provided indirectly to the image processing unit 12 via H). In this case, the decoded image is provided at the first frame rate from the image decoder 10 to the memory (not shown), and the decoded image read out from the memory (not shown) is sent to the image processor 12 at the second frame rate. The result processed by the image processor 12 may be provided to the display unit (not shown) at a second frame rate.

According to the present invention, the first frame rate may be the number of frames per hour or may be the number of fields per hour. Similarly, the second frame rate may be the number of frames per hour or may be the number of fields per hour.

If an image is displayed by an interlace scanning method on a display unit (not shown), the first frame rate is the number of fields per hour, and the second frame rate is also the number of fields per hour. However, when the image is displayed in a progressively progressive manner on the display unit (not shown), the first frame rate is the number of frames per hour, and the second frame rate is also the number of frames per hour.

FIG. 2 is a block diagram of an exemplary embodiment of the image processor 12 shown in FIG. 1 according to the present invention, and includes a first pulse width calculator 20, a first number calculator 22, and a second number calculator 24. ), A second pulse width calculator 26 and a signal generator 28.

The image processor 12 illustrated in FIG. 1 may be implemented as illustrated in FIG. 2 to generate the decoded synchronization signal 14. In this case, the first pulse width calculator 20 divides the frequency f of the clock signal CLK by the first frame ratio k, as shown in Equation 1 below, and divides the integer part of the divided result C. [floor (C)] is output as the first pulse width C1.

Where k is a / b and a is a prime of b.

The first number calculator 22 calculates the first number N1 from the first pulse width C1, the first frame rate k, and the frequency f of the clock signal CLK as shown in Equation 2 below. do.

The second number calculation unit 24 subtracts the first number N1 from a as shown in Equation 3 below, and outputs the subtracted result as the second number N2.

The second pulse width calculation unit 26 adds the first pulse width C1 and '1' input from the first pulse width calculation unit 20 as shown in Equation 4 below, and adds the added result to the second pulse. It outputs as width C2.

To this end, the second pulse width calculator 26 adds the first pulse width C1 and '1' input from the first pulse width calculator 20, and adds the added result to the second pulse width C2. It can be implemented by the adder 30 outputting as).

The signal generator 28 generates the second number N2 fields having the first pulse width C1 and the first number N1 fields having the second pulse width C2 as the decoding synchronization signal. The generated decoding synchronization signal 14 is output to the image decoding unit 10 through the output terminal OUT2.

3 is a waveform diagram illustrating an example of a decoding synchronization signal, in which the decoding synchronization signal includes a first number N2 of fields having a first pulse width C1 and a first pulse having a second pulse width C2. It has a number N1 of fields.

According to an embodiment of the present invention, as shown in FIG. 3, the signal generator 28 generates a second number N2 of fields having a first pulse width C1 as a decoding synchronization signal. The first number N1 of fields having two pulse widths C2 may be generated in succession. Alternatively, unlike FIG. 3, the signal generator 28 generates the first pulse width C1 after generating the first number N1 of fields having the second pulse width C2 as the decoding synchronization signal. The second number N2 of fields may occur in succession.

In this case, the fields of the second number N2 have the same duty, and the fields of the first number N1 have the same duty.

FIG. 4 is a waveform diagram illustrating another embodiment of the decoding synchronization signal, in which the decoding synchronization signal includes the second number N2 fields having the first pulse width C1 and the first number having the second pulse width C2. Has fields of (N1).

According to another exemplary embodiment of the present invention, the signal generator 28 is a decoding synchronization signal and includes a second number N2 of fields having the first pulse width C1 and a second pulse width C2. It may also occur by randomly mixing one number N1 of fields. For example, as shown in FIG. 4, after the field having the first pulse width C1 and the field having the second pulse width C2 are alternately generated, the first or second pulse width C1 is generated. Or fields with C2) can be generated one after the other.

5 (a) and 5 (b) are waveform diagrams illustrating still other aspects of the decoding synchronization signals, and FIG. 5 (a) shows decoding synchronization generated when the second number N1 is larger than the first number N1. FIG. 5B shows a waveform diagram of the decoding synchronization signal generated when the first number N1 is larger than the second number N2.

According to still another embodiment of the present invention, the signal generator 28 is a decoding synchronization signal and includes a second number N2 of fields having a first pulse width C1 and a second pulse width C2. After alternately generating one number N1 of fields, as many fields as N1-N2 (or N2-N1) may be generated.

For example, as shown in FIG. 5A, when the second number N2 is larger than the first number N1, the signal generator 28 is a decoding synchronization signal and is the first pulse width C1. After alternately generating a field of the first number N1 having the first field and a field of the first number N1 having the second pulse width C2, the second number N2 to the first number N1. A field having the first pulse width C1 may be generated by the number N2-N1 subtracted by.

Alternatively, as illustrated in FIG. 5B, when the first number N1 is larger than the second number N2, the signal generator 28 may determine the first pulse width C1 as a decoding synchronization signal. After alternately generating the second number N2 of fields and the second number N2 of fields having the second pulse width C2, the second number N2 is subtracted from the first number N1. A field having the second pulse width C2 by one number N1-N2 may be generated.

As shown in FIGS. 3 to 5, one frame includes two fields, for example, a top field and a bottom field.

In addition, in order to generate the decoding synchronization signal as described above, the signal generator 28 may be implemented as a counter (not shown). In this case, the signal generator 28 inverts the level of the decoding synchronization signal whenever the value counted by the counter becomes the first pulse width C1 or the second pulse width C2.

For better understanding of the present invention, it is assumed that the frequency f of the clock signal CLK is always an integer, and the frame rate is not an integer. For reference, the frame rate supported by MPEG-2 may be 47.952 Hz, 48 Hz, 50 Hz, 59.94 Hz or 60 Hz. For example, the resolution of the display unit (not shown) is 1366 x 768, the second frame rate is 60 Hz, the frequency f of the clock signal CLK is 80.19 MHz, and the first frame rate k = a. / b) is 2997/50 and is assumed to be 59.94 ms. At this time, the result C of dividing the first frame rate k by the frequency f of the clock signal CLK is 80190000 / 59.94 = 1337837.837837. At this time, since C is not an integer, it is difficult to be implemented in hardware. In other words, to simply implement hardware, C can be converted to an integer simply by rounding up, down, or rounding up. However, in this case, if a certain amount of time elapses, there may be a side effect of incorrectly inverting the field, such as a bottom field occurring at a time when the top field should be.

In order to solve this problem, the present invention generates a decoding synchronization signal having a different pulse width as described above in order to disperse the fractional part of C in time. That is, the first pulse width C1 is 1337837, the second pulse width C2 is 1337838, the first number N1 is 2511, and the second number N2 is 486. Here, that the first pulse width C1 is 1337837 means that the first pulse width C1 is 1337837T. T means a unit period of the clock signal CLK. Further, the fact that the second pulse width C2 is 1337838 means that the second pulse width C2 is 1337838T. Therefore, a decoding synchronization signal may be generated as shown in FIG. 3, 4, or 5 (b).

FIG. 6 is a block diagram of another embodiment of the image processing unit 12 shown in FIG. 1 according to the present invention, and includes a format conversion unit 40.

The format converter 40 converts the format of the decoded video input from the image decoder 10 through the input terminal IN2 to match the format of the display unit (not shown), and converts the converted result through the output terminal OUT3. Output At this time, the image processor 12 processes the decoded image having the format converted by the format converter 40, such as Picture Quality Enhancement, by matching display characteristics of a display unit (not shown), The result is output to the display unit (not shown) through the output terminal OUT1.

Meanwhile, the image decoder 10 illustrated in FIG. 1 transmits the decoded image to the image processor 12 in response to the display synchronization signal 16 input from the image processor 12. That is, the time point at which the image decoded by the image decoder 10 is transferred to the image processor 12 may be determined by the display synchronization signal 16.

To this end, the image processor 12 may generate the display synchronization signal 16 according to the second frame rate, and output the generated display synchronization signal 16 to the image decoder 10.

7 (a) and 7 (b) are waveform diagrams illustrating the display synchronization signal and the decoding synchronization signal, respectively, and the time t may be, for example, 0.2 seconds (sec).

As shown in FIG. 7A, a display synchronization signal 16 adjusted to a ratio of the second frame, for example, 30 Hz may be generated from the image processor 12 and output to the image decoder 10. In addition, as illustrated in FIG. 7B, a decoding synchronization signal 14 having a ratio of, for example, 25 Hz of the first frame may be generated from the image processing unit 12 and output to the image decoding unit 10. .

The image decoder 10 and the image processor 12 shown in FIG. 1 may be included in a digital television (not shown). In this case, the video decoding unit 10 decodes the compressed television broadcast video signal input through the input terminal IN1 using the decoding synchronization signal 14. The image processor 12 processes the result decoded by the image decoder 10 according to the characteristics of the display unit (not shown), outputs the processed result to the display unit (not shown), and displays the display unit (not shown). The television broadcast can be displayed via the.

Hereinafter, an embodiment of an image decoding and processing method according to the present invention will be described with reference to the accompanying drawings.

8 is a flowchart for explaining an embodiment of an image decoding and processing method according to the present invention, which includes generating a decoding synchronization signal (step 60), decoding a compressed image (step 62), and decoding. Processing (step 64) of the processed image.

According to the image decoding and processing method according to the present invention, first, the image processing unit 12 describes the decoding synchronization signal 14 by using the frequency f and the first frame rate k of the clock signal CLK. The image is generated as described above and output to the image decoder 10 (step 60).

After operation 60, the image decoder 10 decodes the compressed image given from the outside using the decoding synchronization signal 14, and provides the decoded image to the image processor 12 at a first frame rate. Step 62).

After operation 62, the image processor 12 processes the decoded image provided from the image decoder 10 according to the clock signal CLK, and outputs the processed result to the display unit (not shown) at a second frame rate. (Step 64). Here, the results provided at the second frame rate are displayed on the display unit (not shown).

As described above, the apparatus and method for decoding and processing an image according to the present invention distributes the fractional part of C in time so that the decoding synchronization signal synchronized with the first frame rate is converted to the clock signal CLK without the side effect of inverting the field. Not only can be generated using the frequency (f), but also suitable to be implemented in hardware, since the decoding operation is performed using the generated decoding synchronization signal has an effect that it is possible to decode the video signal more accurately.

Claims (10)

An image decoder which decodes the compressed input image in response to a decoding synchronization signal and outputs the decoded image at a first frame rate; And Process the decoded image input from the image decoder in response to a clock signal and output the processed result at a second frame rate, and generate the decoding synchronization signal using the frequency of the clock signal and the first frame rate. And an image processor configured to generate the display synchronization signal according to the second frame rate. delete The image decoding and processing apparatus of claim 1, wherein the first and second frame rates are at least one of a number of fields per hour and a number of frames per hour. The image processing apparatus of claim 1, wherein the image processor A first pulse width calculator dividing the frequency of the clock signal by the first frame rate and outputting an integer part of the divided result as a first pulse width; A first number calculator configured to calculate a first number from the first pulse width, the first frame rate, and the frequency of the clock signal as follows;

Where N1 represents the first number, k represents the first frame rate, k = a / b, a represents a prime number of b, f represents the frequency of the clock signal, and C1 represents the first number. 1 pulse width respectively.) A second number calculator configured to subtract the first number from a and output the subtracted result as a second number; A second pulse width calculation unit that adds the first pulse width and 1 and outputs the added result as a second pulse width; And And a signal generator for generating the second number of fields having the first pulse width and the first number of fields having the second pulse width as the decoding synchronization signal. . The method of claim 4, wherein the signal generator And generating the second number of fields having the first pulse width one after the other as the decoding synchronization signal. The method of claim 4, wherein the signal generator And the second number of fields having the first pulse width and the first number of fields having the second pulse width are randomly generated as the decoding synchronization signal. The method of claim 4, wherein the signal generator After the alternating generation of the second number of fields having the first pulse width and the first number of fields having the second pulse width as the decoding synchronization signal, a larger number of the first number and the second number is generated. And a field of the video decoding and processing. The image processing apparatus of claim 1, wherein the image processor A format converter which converts a format of the decoded video input from the video decoder, And a decoded image having the converted format in accordance with a display synchronization signal. delete Generating a decoding synchronization signal using the frequency of the clock signal and the first frame rate; Decoding a compressed video using the decoding synchronization signal and providing a decoded video at the first frame rate; And Processing the decoded image provided at the first frame rate according to the clock signal, and providing a processed result at a second frame rate, Generating a display synchronization signal according to the provided second frame rate and processing the decoded image according to the display synchronization signal.

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