CN100484194C - Interlaced image signal frequency multiplication method and device - Google Patents
Interlaced image signal frequency multiplication method and device Download PDFInfo
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- CN100484194C CN100484194C CNB2006100078092A CN200610007809A CN100484194C CN 100484194 C CN100484194 C CN 100484194C CN B2006100078092 A CNB2006100078092 A CN B2006100078092A CN 200610007809 A CN200610007809 A CN 200610007809A CN 100484194 C CN100484194 C CN 100484194C
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Abstract
The method includes steps: first, removing the part, which is not synchronous to horizontal sync signal, in first vertical sync signal, and based on the first vertical sync signal to obtain first image field and second image field from interlace scanning image signal; then, carrying out doublefrequency process for frame composed of first image field and second image field so as to generate second vertical sync signal and second horizontal sync signal; finally, based on second horizontal sync signal to make up the part located at juncture of two image fields in frame after processed doublefrequency of second vertical sync signal. Thus, without need of frame buffer, using line buffer architecture to do doublefrequency process, the invention still can output interlace scanning result not influencing on quality of displayed image.
Description
Technical field
The present invention relates to a kind of picture signal frequency-doubling method and device, and be particularly related to a kind of interlaced image signal frequency multiplication method and device.
Background technology
Image now and video display devices all need double frequency function, and so-called frequency multiplication is to refer to picture signal (Video signal) scan line of being imported is increased or reduce multiple relation, wherein this multiple relation be not defined as integral multiple (for example: can be 0.5 times or 1.5 times ... etc.) so that image or video pictures can meet the resolution of display unit after treatment.With cathode ray tube (CathodeRay Tube) display is example, the mode that picture signal transmits has two kinds of alternating expression (Interlace) sweep signal and noninterlaced (Non-interlace) sweep signals, scans so just can be divided into interleaved type scanning and noninterlaced at the framework of image processing apparatus.Wherein, if adopt the image processing apparatus of interleaved type scanning framework, each picture frame (frame) is necessary for odd number bar scan line, if adopt the image processing apparatus of noninterlaced scan architecture, each picture frame is necessary for even number bar scan line.
Figure 1A is known interleaved type scanning sequential chart.Figure 1B, Fig. 1 C and Fig. 1 D are known interleaved type scanning display mode schematic diagram.Please, in interleaved type scanning sequential Figure 100, comprise vertical synchronizing signal (V-sync) and horizontal-drive signal (H-sync) in the lump with reference to Figure 1A, Figure 1B, Fig. 1 C and Fig. 1 D.Wherein, in the cycle of the 1st pulse V1 of vertical synchronizing signal (V-sync), can do the scanning (being shown in Figure 1B) of odd number bar scan line O to the picture frame F that is imported according to the scan period of horizontal-drive signal (H-sync), and produce a strange figure OF; In the cycle of the 2nd vertical synchronizing signal pulse V2, equally can do the scanning (being shown in Fig. 1 C) of even number bar scan line E to the picture frame F that is imported, and produce bigraph field EF according to the scan period of horizontal-drive signal (H-sync).
A strange figure OF and bigraph field EF can form 1 picture frame F of display, and this picture frame F and have 2n+1 bar scan line SL.For instance, when Qi Tuchang OF, the odd number bar scan line O that the display electron gun only can scintigram picture frame F has n+0.5 bar scan line at this strange figure OF; And when the EF of bigraph field, the even number bar scan line E that the display electron gun only can scintigram picture frame F, EF also has 0.5+n bar scan line in this bigraph field.So, be exactly that display finally is shown to the picture that the user watches when result's (being shown in Fig. 1 D) of strange figure OF superposition bigraph field EF can produce 2n+1 bar scan line SL.Wherein, the solid arrow shown in Figure 1B, Fig. 1 C and Fig. 1 D is display electron gun scan line SL, and the action that dotted arrow retracts for the display electron gun.
Fig. 2 is the block diagram of known displays image processing apparatus.Please refer to Fig. 2, image processing apparatus 200 comprises analog-digital converter (Analog-to-digital converter is called for short ADC) 201, input synchronous processing device 203, getter 205, buffer 207, frequency multiplier (Scaler) 209 and output synchronous processing device 211.Wherein, buffer 207 can be frame buffer (Frame buffer) or scan line buffer device (Line buffer), and frame buffer is in order to store one or more frames (Frame), and the scan line buffer device is in order to store 1 or multi-strip scanning line (Scan line).
Analog-digital converter 201 is in order to receiving picture signal VS, and provides digital signal to getter 205.Input synchronous processing device 203 is in order to receiving the first composite synchronizing signal H/V_Sync_in, and provides first horizontal-drive signal and first vertical synchronizing signal to getter 205 respectively.Getter 205 according to first horizontal-drive signal and first vertical synchronizing signal, obtains digital signal scope to be processed to buffer 207 respectively.Buffer 207 is a storage unit with frame (Frame) or scan line (Scan line) again, by frequency multiplier 209 handle back output digital signal VO and export second horizontal-drive signal respectively and second vertical synchronizing signal to exporting synchronous processing device 211.Output synchronous processing device 211 provides the second composite synchronizing signal H/V_Sync_out according to second horizontal-drive signal and second vertical synchronizing signal respectively.At last, image processing apparatus 200 can provide output digital signal VO and the second composite synchronizing signal H/V_Sync_out back-end circuit processing to display.
The above-mentioned first mentioned composite synchronizing signal H/V_Sync_in be with the mode of modulation (Modulate) with first horizontal-drive signal and first vertical synchronizing signal combine produced.On the contrary, if during, will produce first horizontal-drive signal and first vertical synchronizing signal respectively with the first composite synchronizing signal H/V_Sync_in rectification (Demodulate).In like manner, the second composite synchronizing signal H/V_Sync_out be with the mode of modulation with second horizontal-drive signal and second vertical synchronizing signal combine produced.If during with the second composite synchronizing signal H/V_Sync_out rectification, will produce second horizontal-drive signal and second vertical synchronizing signal respectively.
Fig. 3 A is the frequency-doubling method schematic diagram of known employing frame buffer.Please in the lump with reference to Figure 1A, Fig. 2 and Fig. 3 A, in image processing apparatus 200, because of buffer 207 is frame buffer (Framebuffer).So scan period t in horizontal-drive signal (H-sync), the scan line SL that buffer 207 can will very be schemed an OF earlier stores, after receiving bigraph field EF scan line SL again, be that storage unit is formed complete display frame with strange field scan line O and bigraph field scan line E superposition with picture frame F.So, the scan period t of horizontal-drive signal at one time (H-sync) can realize the output of frequency multiplication relation after frequency multiplier 209 is handled.
Fig. 3 B is that known employing frame buffer frequency multiplication is with noninterlaced scanning display mode schematic diagram.After the frequency multiplier frequency multiplication, with noninterlaced scanning output, though the display frame effect of display output is preferable, it utilizes frame buffer to store frame, so cost also can be comparatively huge again at the known frame buffer that adopts.
Fig. 4 A is known employing scan line buffer device frequency-doubling method schematic diagram.Please in the lump with reference to Figure 1A, Fig. 2 and Fig. 4 A, in image processing apparatus 200, because of buffer 207 is scan line buffer device (Linebuffer).So scan period t in horizontal-drive signal (H-sync), buffer 207 can distinctly will very be schemed the scan line SL of an OF and bigraph field EF, after frequency multiplier 209 processes, make the scan period t of its horizontal-drive signal (H-sync) at one time, the scan line SL that will very scheme an OF and bigraph field EF individually realizes the output of frequency multiplication relation.
Fig. 4 B is that known employing scan line buffer device is with interleaved type scanning display mode schematic diagram.Export with interleaved type scanning after the frequency multiplier frequency multiplication stranger figure field and bigraph field.Originally strange, each self-contained 0.5 scan line of bigraph field can be because the frequency multiplication computing make scan line strange, the bigraph field all become the integer bar, and when the result caused display output, two figure that constitute display frame can be overlapping, shown in Fig. 4 B, and the infringement image quality.
In sum, in known image frequency multiplication device, because of the load mode of picture signal is divided into two kinds of interleaved type scanning signal and noninterlaced sweep signals, so just can be divided into the scanning of interleaved type scanning and noninterlaced at the framework of image processing apparatus, and the buffer that is used has two kinds of frame buffer and scan line buffer devices.Wherein, if adopt frame buffer after the frequency multiplier frequency multiplication, during again with noninterlaced scanning output, though the display frame meeting has preferable image quality because of non-interlaced scanning, the employing frame buffer also can be comparatively huge on cost of manufacture.And if adopt the scan line buffer device after the frequency multiplier frequency multiplication, when export with interleaved type scanning, the odd even figure field that then can cause display to export is overlapping again, has lost the purpose of interleaved type scanning and damages image quality.
Summary of the invention
In view of this, the invention provides a kind of interlaced image signal frequency multiplication method, in order to after the interleaved type scanning signal frequency multiplication that image processing apparatus received, export with the interleaved type scanning signal again, not only can avoid the expensive of conventional frame buffer architecture, also can solve the overlapping shortcoming in output map field of traditional scan line buffer device framework, and can handle the interleaved type scanning signal with the existing image processing apparatus of handling the non-interlaced scanning framework.
The present invention also provides a kind of interlaced image signal frequency multiplication device, according to the spirit of the invention described above method, can be used in device of the present invention, similarly can reach the advantage of the invention described above method.
Interlaced image signal frequency multiplication method provided by the present invention comprises to be removed earlier in first vertical synchronizing signal and the nonsynchronous part of first horizontal-drive signal, and, obtain the first figure field and the second figure field from interlaced image signal according to this first vertical synchronizing signal.Then, the frame that the first figure field and the second figure field are formed carries out process of frequency multiplication, and produces second vertical synchronizing signal and second horizontal-drive signal.At last, according to second horizontal-drive signal, fill the part that second vertical synchronizing signal is positioned at the frame two figure field intersections after the frequency multiplication.
In one embodiment of this invention, process of frequency multiplication can realize for interpolative operation or the mode of duplicating scan line.Wherein, the frame before process of frequency multiplication comprises odd number bar scan line, and the frame after the process of frequency multiplication also comprises odd number bar scan line.
In the present embodiment, the first figure field is strange of scheming in field and the bigraph field, and the second figure field is for very figure field and bigraph field wherein are different from the first figure field person.
From another viewpoint, the invention provides a kind of interlaced image signal frequency multiplication device and comprise: input synchronous processing device, getter, frequency multiplier and output synchronous processing device.Wherein, the input synchronous processing device is exported first vertical synchronizing signal then in order to remove in first vertical synchronizing signal and the nonsynchronous part of first horizontal-drive signal.Getter can obtain and export the first figure field and the second figure field from interlaced image signal according to importing first vertical synchronizing signal that synchronous processing device is exported.Frequency multiplier can carry out the frame of the first figure field and second figure field composition exporting this frame after the process of frequency multiplication, and produces second vertical synchronizing signal and second horizontal-drive signal.The output synchronous processing device can be according to second horizontal-drive signal, fills the part that second vertical synchronizing signal is positioned at the frame two figure field intersections after the frequency multiplication, exports second vertical synchronizing signal and second horizontal-drive signal then.
In another embodiment of the present invention, process of frequency multiplication can realize for interpolative operation or the mode of duplicating scan line.Wherein, the frame before process of frequency multiplication comprises odd number bar scan line, and the frame after the process of frequency multiplication also comprises odd number bar scan line.
In the present embodiment, the first figure field is strange of scheming in field and the bigraph field, and the second figure field is for very figure field and bigraph field wherein are different from the first figure field person.The input synchronous processing device also receives first composite synchronizing signal, and first vertical synchronizing signal and first horizontal-drive signal are from this first composite synchronizing signal of rectification (demodulate).The output synchronous processing device is that second vertical synchronizing signal and second horizontal-drive signal modulation (modulate) are produced the output afterwards of second composite synchronizing signal.
In the present embodiment, the interlaced image signal frequency multiplication device can also comprise analog-digital converter and scan line buffer device.Wherein, analog-digital converter provides interlaced image signal self simulation conversion of signals to getter after for digital signal.The data of at least one scan line of scan line buffer device meeting buffer memory getter output are used for frequency multiplier.
The invention provides a kind of interlaced image signal frequency multiplication method and device, picture signal is after the frequency multiplier frequency multiplication, and output can be identical or different resolution.As described in preferred embodiment after a while, emphasis of the present invention is to remove earlier before frequency multiplication in the vertical synchronizing signal and the nonsynchronous part of horizontal-drive signal, the parts of two figure intersections just, be that unit makes process of frequency multiplication then with picture signal, fill the vertical synchronizing signal of two figure intersections again with the frame.So only need to adopt the scan line buffer device, can avoid the expensive of conventional frame buffer architecture, and the frame before and after the frequency multiplication all comprises odd number bar scan line, can solve the overlapping problem in output map field of traditional scan line buffer device framework.Because the present invention is to be that unit does the frequency multiplication computing with the entire frame, the present invention can utilize the existing image processing apparatus of handling the non-interlaced scanning framework to handle the interleaved type scanning signal, and still can export with interleaved type scanning, and does not influence the quality of display frame.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment of the present invention cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A is known interleaved type scanning sequential chart.
Figure 1B, Fig. 1 C and Fig. 1 D are known interleaved type scanning display mode schematic diagram.
Fig. 2 is the block diagram of known technology display image processing unit.
Fig. 3 A is the frequency-doubling method schematic diagram of known employing frame buffer.
Fig. 3 B is that known employing frame buffer frequency multiplication is with noninterlaced scanning display mode schematic diagram.
Fig. 4 A is the frequency-doubling method schematic diagram of known employing scan line buffer device.
Fig. 4 B is that known employing scan line buffer device is with interleaved type scanning display mode schematic diagram.
Fig. 5 is according to the interlaced image signal frequency multiplication device block diagram of a preferred embodiment of the present invention.
Fig. 6 is the scanning sequence figure according to present embodiment.
Fig. 7 is according to present embodiment scan mode schematic diagram.
Fig. 8 is according to present embodiment display mode schematic diagram.
Fig. 9 is the interlaced image signal frequency multiplication method flow chart according to a preferred embodiment of the present invention.
The main element description of symbols
200: image processing apparatus
201,501: analog-digital converter
203,503: the input synchronous processing device
205,505: getter
207,507: buffer
209,509: frequency multiplier
211,511: the output synchronous processing device
500: the interlaced image signal frequency multiplication device
VS: picture signal
VO: digital signal
H/V_Sync_in: first composite synchronizing signal
OV: first vertical synchronizing signal
OH: first horizontal-drive signal
H/V_Sync_out: second composite synchronizing signal
AV: second vertical synchronizing signal
AH: second horizontal-drive signal
F: picture frame
OF: Qi Tuchang
EF: bigraph field
FF: the first figure field
SF: the second figure field
V1: first vertical synchronizing signal of first vertical synchronizing signal
V2: in first vertical synchronizing signal with the nonsynchronous part of first horizontal-drive signal
V1 ': first vertical synchronizing signal of second vertical synchronizing signal
V2 ': after second vertical synchronizing signal is positioned at frequency multiplication, the part of the picture frame first figure field and the second figure field intersection
SL: scan line
O, OSL: strange field scan line
E, ASL: bigraph field scan line
T: the scan period of horizontal-drive signal
S901～S907: flow chart step
Embodiment
Fig. 5 is the interlaced image signal frequency multiplication device block diagram according to a preferred embodiment of the present invention.Please refer to Fig. 5, comprise input synchronous processing device 503, getter 505, frequency multiplier 509 and output synchronous processing device 511 at interlaced image signal frequency multiplication device 500 of the present invention.In the present embodiment, interlaced image signal frequency multiplication device 500 can also comprise analog-digital converter 501 and scan line buffer device 507.
Fig. 6 is the scanning sequence figure according to present embodiment.Please, in scanning sequence Figure 60 0, comprise the first vertical synchronizing signal OV, the first horizontal-drive signal OH, the second vertical synchronizing signal AV and the second horizontal-drive signal AH in the lump with reference to Fig. 5 and Fig. 6.Wherein, in the cycle of first pulse V1 of the first vertical synchronizing signal OV, can do the scanning of odd number bar scan line to the picture frame F of the picture signal VS that imported according to scan period of the first horizontal-drive signal OH, and produce the first figure field FF; In the cycle of second pulse V2 of the first vertical synchronizing signal OV, equally can do the scanning of even number bar scan line to the picture frame F of the picture signal VS that imported, and produce the second figure field SF according to scan period of the first horizontal-drive signal OH.
In the present embodiment, the first figure field FF is a strange figure OF, and the second figure field SF is bigraph field EF.In other embodiments of the invention, figure configuration can be changed, and just the first figure field FF is bigraph field EF, and the second figure field SF is a strange figure OF.
A strange figure OF has n+0.5 bar scan line OSL, after frequency multiplier 509 process of frequency multiplication, has m+0.5 bar scan line ASL again; And bigraph field EF also has n+0.5 bar scan line OSL, again after frequency multiplier 509 process of frequency multiplication, similarly also have m+0.5 bar scan line ASL,, after frequency multiplier 509 process of frequency multiplication, have 2m+1 bar scan line ASL again so have 2n+1 bar scan line OSL at preceding 1 the picture frame F of frequency multiplication as can be known.Wherein, have the multiple relation between the scan line OSL quantity (being 2n+1) before scan line ASL quantity (being 2m+1) after the frequency multiplication that frequency multiplier 509 is exported and the frequency multiplication, and this multiple relation is not defined as integral multiple, for example can be 0.5 times or 1.5 times ... etc.
In the present embodiment, analog-digital converter 501 provides to getter 505 after being digital signal in order to the picture signal VS self simulation conversion of signals that will be received again.Input synchronous processing device 503 is in order to receive the first composite synchronizing signal H/V_Sync_in, and the first composite synchronizing signal H/V_Sync_in rectification produced the first vertical synchronizing signal OV and the first horizontal-drive signal OH, and remove among the first vertical synchronizing signal OV and the nonsynchronous part of the first horizontal-drive signal OH (be among the V2 with the nonsynchronous part of horizontal-drive signal).
In the present embodiment, picture signal VS can be interlaced image signal (InterlaceVideo signal).Input synchronous processing device 503 does not limit and will receive the first composite synchronizing signal H/V_Sync_in, as long as Jie Shou not the first vertical synchronizing signal OV and the first horizontal-drive signal OH are individual, else be sent to getter 505 then, make getter 505 obtain digital signal scope to be processed according to the first vertical synchronizing signal OV and the first horizontal-drive signal OH.So, can omit the process of modulation and demodulation system.
Then, getter 505 can be exported according to input synchronous processing device 503 and remove nonsynchronous first vertical synchronizing signal OV, obtains and export the first figure field FF and the second figure field SF from interlaced image signal VS.Scan line buffer device 507 uses for frequency multiplier 509 in order to the first figure field FF of buffer memory getter 505 outputs and the data of second figure field SF at least one scan line.At last, after 509 picture frame F to the first figure field FF and second figure field SF composition of frequency multiplier carry out process of frequency multiplication, with alternating expression (interlace) sweep signal output digital signal VO, and produce the second vertical synchronizing signal AV and the second horizontal-drive signal AH to exporting synchronous processing device 511.
Output synchronous processing device 511 is filled the part (being V2 ') that the second vertical synchronizing signal AV is positioned at the picture frame F two figure field intersections after the frequency multiplication again according to the second horizontal-drive signal AH.Then, the second vertical synchronizing signal AV and second horizontal-drive signal AH modulation is produced after the second composite synchronizing signal H/V_Sync_out, the digital signal VO and the second composite synchronizing signal H/V_Sync_out are sent to the back-end circuit processing of display.
In the present embodiment, output synchronous processing device 511 does not limit yet will export the second composite synchronizing signal H/V_Sync_out, as long as the second vertical synchronizing signal AV and the second horizontal-drive signal AH other back-end circuit that is sent to display are processed.So, also can omit the process of rectification and modulation.
Fig. 7 is a present embodiment scan mode schematic diagram.Please in the lump with reference to Fig. 5 and Fig. 7, in interlaced image signal frequency multiplication device 500, be to be processing unit with picture frame F because of present embodiment.So scan period t at the first horizontal-drive signal OH that provided of input synchronous processing device 503, after the scan line OSL that frequency multiplier 509 can will be stored in the strange figure field OF of scan line buffer device 507 and bigraph field EF does process of frequency multiplication, make its scan period t at the same first horizontal-drive signal OH, the scan line ASL that will very scheme an OF and bigraph field EF individually realizes the output of frequency multiplication relation, and this multiple relation is not defined as integral multiple, for example can be 0.5 times or 1.5 times ... etc.Fig. 8 is according to present embodiment display mode schematic diagram.Please in the lump with reference to Fig. 5 and Fig. 8, in interlaced image signal frequency multiplication device 500, after frequency multiplier 509 process of frequency multiplication, the scan line OSL number 2n+1 bar of original picture frame F can be risen to 2m+1 bar scan line ASL, therefore export with alternating expression (Interlace) sweep signal again, just can make two figure fields overlapping, can improve the image quality of display image unlike traditional frequency-doubling method.
In the present embodiment, process of frequency multiplication can realize for interpolative operation or the mode of duplicating scan line.Wherein, the picture frame F before process of frequency multiplication comprises odd number bar scan line OSL, and the picture frame F after the process of frequency multiplication also comprises odd number bar scan line ASL.
Fig. 9 is the interlaced image signal frequency multiplication method flow chart according to a preferred embodiment of the present invention.At first, meeting of the present invention is as described in the step S901, removes earlier in first vertical synchronizing signal and the nonsynchronous part of first horizontal-drive signal.And as described in step S903,, obtain the first figure field and the second figure field from interlaced image signal according to rapid first vertical synchronizing signal that produces of previous step.Then, the present invention understands execution in step S905, and the frame that the first figure field and the second figure field are formed carries out process of frequency multiplication, and produces second vertical synchronizing signal and second horizontal-drive signal.At last, meeting of the present invention is as described in the step S907, according to second horizontal-drive signal, fills the part that second vertical synchronizing signal is positioned at the frame two figure field intersections after the frequency multiplication.
In sum, the present invention provides a kind of interlaced image signal frequency multiplication method and device.The present invention has following advantage:
1. adopt the interleaved type scanning framework, and do not need frame buffer, can be identical or different resolution through digital processing output later.
2. adopt the scan line buffer device and be processing unit with picture frame (Frame), still can be the interleaved type scanning framework through digital processing output later, do not have to scheme an overlapping shortcoming after the conventional method frequency multiplication, and because of adopting the scan line buffer device, so on manufacturing cost, also can reduce.
3. be that unit makes process of frequency multiplication with the frame, can utilize the existing image processing apparatus of handling the non-interlaced scanning signal, handle the interleaved type scanning signal.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the present invention; when can doing a little change and improvement, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (14)
1. interlaced image signal frequency multiplication method is characterized in that comprising:
Remove in first vertical synchronizing signal and the nonsynchronous part of first horizontal-drive signal;
According to rapid this first vertical synchronizing signal that produces of previous step, staggered certainly scan image signal obtains the first figure field and the second figure field;
Frame to this first figure field and this second figure field composition carries out process of frequency multiplication, and produces second vertical synchronizing signal and second horizontal-drive signal; And
According to this second horizontal-drive signal, fill the part that this second vertical synchronizing signal is positioned at these frame two figure field intersections after the frequency multiplication.
2. interlaced image signal frequency multiplication method according to claim 1 is characterized in that this process of frequency multiplication is to realize with interpolative operation.
3. interlaced image signal frequency multiplication method according to claim 1 is characterized in that this process of frequency multiplication is to realize in the mode of duplicating scan line.
4. interlaced image signal frequency multiplication method according to claim 1 is characterized in that, this frame before this process of frequency multiplication comprises odd number bar scan line, and this frame after this process of frequency multiplication also comprises odd number bar scan line.
5. interlaced image signal frequency multiplication method according to claim 1 is characterized in that, this first figure field is strange of scheming in field and the bigraph field, and this second figure field is for very figure field and bigraph field wherein are different from this first figure field person.
6. interlaced image signal frequency multiplication device is characterized in that comprising:
The input synchronous processing device is removed in first vertical synchronizing signal and the nonsynchronous part of first horizontal-drive signal, exports this first vertical synchronizing signal then;
Getter, according to this first vertical synchronizing signal of this input synchronous processing device output, staggered certainly scan image signal obtains and exports the first figure field and the second figure field;
Frequency multiplier, the frame that this first figure field and this second figure field are formed carry out this frame of output after the process of frequency multiplication, and produce second vertical synchronizing signal and second horizontal-drive signal; And
The output synchronous processing device according to this second horizontal-drive signal, is filled the part that this second vertical synchronizing signal is positioned at these frame two figure field intersections after the frequency multiplication, exports this second vertical synchronizing signal and this second horizontal-drive signal then.
7. interlaced image signal frequency multiplication device according to claim 6 is characterized in that this frequency multiplier realizes this process of frequency multiplication with interpolative operation.
8. interlaced image signal frequency multiplication device according to claim 6 is characterized in that this frequency multiplier realizes this process of frequency multiplication in the mode of duplicating scan line.
9. interlaced image signal frequency multiplication device according to claim 6 is characterized in that, this frame before this process of frequency multiplication comprises odd number bar scan line, and this frame after this process of frequency multiplication also comprises odd number bar scan line.
10. interlaced image signal frequency multiplication device according to claim 6 is characterized in that, this first figure field is strange of scheming in field and the bigraph field, and this second figure field is for very figure field and bigraph field wherein are different from this first figure field person.
11. interlaced image signal frequency multiplication device according to claim 6, it is characterized in that this input synchronous processing device also receives first composite synchronizing signal, and this first vertical synchronizing signal and this first horizontal-drive signal are from this first composite synchronizing signal of rectification.
12. interlaced image signal frequency multiplication device according to claim 6 is characterized in that this output synchronous processing device is that this second vertical synchronizing signal and the modulation of this second horizontal-drive signal are produced the output afterwards of second composite synchronizing signal.
13. interlaced image signal frequency multiplication device according to claim 6 is characterized in that also comprising:
Analog-digital converter provides this interlaced image signal self simulation conversion of signals to this getter after for digital signal.
14. interlaced image signal frequency multiplication device according to claim 6 is characterized in that also comprising:
The scan line buffer device, the data of at least one scan line of this getter output of buffer memory are used for this frequency multiplier.
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