KR100771177B1 - A method of fabricating an electronic device comprising a thin-film transistor - Google Patents

Abstract

FIELD OF THE INVENTION The present invention relates to a method of fabricating an electronic device comprising a thin film transistor, wherein the increased off-state current and reduced carrier mobility in a self-aligned thin film transistor. Describes the problem. According to the method, the gate layers 2 and 46 are etched back under the mask layers 20 and 48. Following the implantation step using the mask layer as an implantation mask, etch-back results in implantation damage, which is then annealed by the energy beam 42.

Description

A METHOD OF FABRICATING AN ELECTRONIC DEVICE COMPRISING A THIN-FILM TRANSISTOR}

The present invention relates to a method of fabricating an electronic device comprising a thin film transistor (hereinafter referred to as "TFT"), which provides an improved process for fabricating the TFT using self-aligned technology. . The device may be a flat panel display (e.g., an active-matrix liquid-crystal display (AMLCD), which is an active-matrix liquid crystal display) or a wide area image sensor or several other types of wide area electronic devices (e.g. thin film data storage). Device or memory device).

Much attention has been directed to developing thin film circuits and other thin film circuit devices with TFTs on insulated substrates for a wide range of electronic applications. These circuit elements, fabricated as part of an amorphous, microcrystalline or polycrystalline semiconductor film, are described in a cell matrix, such as US Pat. It is possible to form a switching element in a flat panel display as described, the entire contents of which are incorporated herein by reference. More recently, the device may also include an integrated drive circuit, in particular an integrated drive circuit having TFTs of polycrystalline silicon (hereinafter referred to as "polysilicon") as the circuit element.

In the fabrication of polysilicon TFTs, dopant ions (such as phosphorus) to form the regions for the source / drain of the TFTs in a self-aligning (hereinafter referred to as "SA") manner as the gate of the TFTs. It is known to use implantation. In thin film structures, it is known to activate the implanted dopant and anneal crystal lattice damage by manipulating energy beams, in particular laser beams.

The implanted region may be a highly doped drain region of the TFT. For a TFT used in a drive circuit, it may be advantageous to have a field-relief structure comprising a poorly doped drain region (hereinafter referred to as "LDD") between the channel and the drain region of the TFT. . In this case, the injected SA region may be an LDD region or a more highly doped drain region. Therefore, there may be no significant overlap between the gate and the LDD region, or the gate may overlap the LDD region in a structure called a GOLDD. Unfortunately, it has been found that the resulting SA TFTs can be subjected to an increase in off-state leakage current and a decrease in carrier mobility.

The present invention seeks to provide a manufacturing method and fabrication process for SA TFTs of an electronic device, which brings various improvements to the characteristics of the TFTs and devices having TFTs.

More specifically, the present invention provides a method of fabricating an electronic device comprising a thin film transistor, the method comprising:
(a) depositing gate layers 10 and 46 on insulating films 4 and 44 over semiconductor films 6 and 30, and
(b) defining a patterned mask layer 48 over the gate layers 10, 46;
(c) etching to pattern the gate layers (10, 46) using the mask layer (48), and etching back the gate layers (10, 46) under the mask layer;
(d) implanting the semiconductor film 6, 30 using the mask layer 48 and / or the gate layers 10, 46 as an implantation mask,
(e) removing the mask layer 48;

(f) annealing the semiconductor films 6 and 30 with energy beams.

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In the case of TFTs with SA implanted regions, we believe that an important factor in increasing off-state leakage current and decreasing carrier mobility is lattice damage that extends under the edge of the gate and is blocked from laser annealing by the gate. .

The mask layer can be, for example, a photoresist etchant mask. The energy beam (particularly, but not limited to, the laser beam) serves to anneal implantation damage in semiconductor films that are not masked / shielded by the etched gate layer again.

With this process, several problems due to injection damage in SA polysilicon TFTs (with or without LDD or GOLDD) can be reduced, overcome or avoided.

Instead of the expression "gate etch-back", other terms such as "gate over-etching" and "gate undercut" may be used. Each representation is a reetched gate located below the mask layer, spaced and offset from the edge of the mask window by a distance (gap) sufficient to allow the desired annealing of the grating damage in the intervening region. Means an etching process resulting in an edge. By controlling the degree of etching in step (c), the size of the offset (gap) can be adjusted according to the lateral extent of semiconductor lattice damage, which is determined as different levels of various implant doses.

The reetch step (c) may be performed after the implantation step (d). However, when the overlying mask pattern alone is thick and stable enough to mask the implant, step (c) may be performed before step (d). Indeed, this lattice sequence has advantages. Laser annealing (particularly, but not limited to annealing with UV excimer laser beams) is generally convenient for step (f). However, annealing with other types of energy beams, such as using high intensity UV flash lamps, may be used instead.

Although TFTs can be formed of other crystalline semiconductor materials, it is generally convenient to use polycrystalline silicon for thin film semiconductors that provide the channel region of a TFT. The nature of the insulating substrate that involves the TFTs may vary depending on the nature of the electronic device in which the TFTs form a part. Typically, the substrate may comprise inexpensive glass or insulating polymer. Stainless steel may also be used.

In a preferred embodiment, the etching step (c) is carried out as one process step. This can provide more consistent results and more precise gap length control.

The method may comprise an additional injection step after step (e), which provides a lower level of doping than step (d). This produces an LDD region between the gate and the source / drain regions formed in step (d). This may also be appropriate for TFTs operating at relatively low bias, typically at voltages of up to approximately 5V. For such devices, a wider range of infusion doses can be employed in additional infusion steps, reducing the series resistance when compared to the doses normally used for the generation of LDD field-removal regions. This technique also allows the formation of shorter (typically submicron) LDD regions, thereby reducing the series resistance of the regions.

In yet another embodiment, step (b) comprises: (h) defining a source / drain pattern mask layer; (i) performing an implantation step that provides a higher doping level than step (d) to form a source and drain region defined by the source / drain pattern, wherein only the implantation of step (d) is exposed. Performing an implantation step in which the region forms an LDD region; (j) patterning the mask layer to define a gate pattern. Alternatively, the method may comprise an additional step after step (c), that is, (k) defining a source / drain pattern in another mask layer; (l) performing an implantation step that provides a higher doping level than step (d) to form a source and drain region defined by the source / drain pattern, wherein only the implantation of step (d) is exposed. The region may include performing an implantation step to form an LDD region. Therefore, in these methods the reetching of the gate layer creates a gap between the LDD region and the edge of the gate layer. The implanted area is sufficiently exposed to the energy beam.

Another preferred method comprises the steps of (m) defining an initially patterned mask layer; (n) performing an implantation step using the initial mask layer as an implantation mask, wherein the implantation is performed in a region extending laterally and inwardly beyond the edge of the patterned mask formed in step (b). Performing an implantation step that provides a lower level of doping; (o) annealing the semiconductor film with an energy beam. Thus, an LDD region can be formed in the LDD region that can extend below the gate of the finished device, where all of the region has been exposed to the energy beam to repair implantation damage.

The method may include anodizing the gate layer (p) prior to the reetching step (c). The implantation step (d) is preferably carried out before step (p), since step (d) may serve to cure the mask layer prior to the anodization step (p).

The gate layer can be made of metal, or semiconductor (eg polysilicon), or a combination of materials. Preferably, the gate layer comprises aluminum or titanium and an aluminum double layer. The gate may be reetched in step (e) at intervals of 3 μm or less, more preferably at intervals of 0.25 μm to 0.5 μm.                 

The method of implementing the present invention will now be described by way of example with reference to the accompanying drawings.

1 shows a schematic device structure of SA TFTs fabricated using the gate reetch method of the present invention.

2 is a graph showing gap length as a function of etch time.

3 shows an SEM micrograph of an undercut gate.

4 is a graph showing the mobility and infusion doses of various TFT structures.

FIG. 5 is a graph showing the minimum leakage current and injection dose of various devices with a drain voltage of 5V applied. FIG.

FIG. 6 is a graph showing the ratio of the leakage current at the gate voltage of −10 V to the minimum leakage current shown in FIG. 5 for various devices and injection doses.

FIG. 7 is a graph showing the slope versus drain voltage curve of log (drain current) in the off-state at a gate voltage of −10 V for various devices and injection doses.

Figure 8a is the threshold voltage, V _T (De-symbol), 1V structure III device (n ^- & gap) and in Figure 1 the output characteristics of the below-shown current (on-current) loss (open symbols) on the graph.

FIG. 8B is a graph showing on-current loss (open symbol) of the SA LDD device and threshold characteristics, output characteristics at 1 V under V _T (blocked symbol). FIG.

FIG. 9 is a graph depicting a characteristic drain voltage with 30% on-current loss after 1 minute stress shown as a function of infusion dose for different device structures.

10A-10D illustrate a process sequence for fabricating a SA GOLDD TFT in accordance with the present invention.

Problems associated with conventional SA LDD devices are residual implant damage, which degrades both on- and off-current and provides poor stability. The introduction of submicron offset regions into the SA LDD device completely eliminates laser injection damage, significantly reducing the higher on-current and drain fields. The resulting TFT also shows reduced sensitivity to gate enhanced leakage current due to poorer gate-drain connections. In the case of a GOLDD TFT, the offset region defined by reetching may be part of a previously annealed, annealed LDD region. In this case, reetching after subsequent implantation of the highly doped drain region completely eliminates subsequent implant damage (and thus reduces leakage current) and allows for justified minimization of the gate-drain capacitance.

The field-removal structure is adopted for n-channel TFTs in polysilicon based CMOS devices to meet the stability criteria required for current AMLCD applications and other system-on-panel devices. Field-removal self-matching (SA) and non-SA (NSA) n-channel TFTs display unacceptable device instability in the form of on-current loss and leakage current increase at low drain voltages. A drain bias of 15V can be applied to the corresponding p-channel device without any detectable device degradation. In this regard, for example, JA Ayres, SD Brotherton, and DJ McCulloch (Jpn. J. Appl. Phys. 37, 1801 (1998)). References are made by DJ McCulloch and MJ Trainor, all of which are incorporated herein as background material.

SA LDD TFTs with self-aligned field-removal regions gated have been studied, although a moderate improvement in device stability has been demonstrated when compared to corresponding SA devices, the stability is still not sufficient for current AMLCD applications. In addition, SA LDD devices are characterized not only by high leakage currents, but also by reduced on-current, both of which result in grating damage resulting from n ^- phosphorus implantation by the applicants. I think that's it.

The embodiment described herein consists of an SA structure with a field-removal region outside the gate or substantially outside of the gate, which addresses some of the issues identified above for conventional SA LDD devices. Controlled over-etching of the gate metal is implemented under a resist mask that defines the gate. The small gap created by the overlap-etching of the gate is used to provide field-removal to the drain, which improves device stability and reduces avalanche current. Field-removal can be achieved either by low-dose injection into this gap to form an LDD region, or by diffusion of dopants from the adjacent LDD or source / drain into the gap during excimer laser activity. Compared with conventional SA LDD devices, the former field-removal structure reduces the LDD length, which reduces the series resistance, while the latter structure uses lasers for complete implant damage elimination and extended junction formation. Make it possible. This results in higher mobility and reduced drain field.

The electrical properties of the TFT structure and its stability are discussed below, which are compared with SA LDD devices.

1 shows a cross section of a TFT structure made according to the method of the present invention and denoted by I, II and III, respectively.

Each device includes a gate electrode 2 over the gate insulating layer 4. The gate electrode is preferably formed of an aluminum, aluminum alloy or titanium / aluminum double layer. SiO ₂ silicon dioxide can form an insulating layer. Below the gate insulating layer 4 is a semiconductor layer 6, typically made of silicon.

Silicon layers 6 of each structure were implanted into regions 8 and 10 with a dopant (n ⁺ ) to define the source and drain of each TFT. Structures II and III also include relatively lightly doped (or n ⁻ ) regions 12 and 14 in the silicon layer, adjacent to respective regions 8 and 10, of which One will form an LDD region. Under the gate electrode 2 in each structure, there is a region 16 made of undoped silicon forming the channel of each TFT.

In each structure of FIG. 1, an offset 18 can be identified within the silicon layer 6, extending across from the edge of the gate electrode 2. In structures I and II, the offset is defined by the edges of the source and drain regions 8 and 10 on both sides of the gate electrode, and in structure II, the offset is defined by the width of the lightly doped regions 12 and 14. Corresponding. In structure (III), the offset is defined by the inner edges of regions 12 and 14.

All of the TFTs in FIG. 1 have a SA top-gated structure, where the gate 2 has a source / drain region 8,10 and an LDD region 12/14 (structures II and III only). Defined prior to dopant injection to form. The dopant may be implanted without removing the gate dielectric layer 4. In each case, the area adjacent to the gate 2 was defined by controlled overlapping etching of the gate metal below the edge of the resist mask that had been deposited to define the gate. Conditions were set which resulted in reproducible redundant etching of the gate in the range between 0.3 μm and 3 μm.

For structures I and II, source / drain regions 8, 10 are implanted after overlapping etching the gate 2 leaving the resist. For structure (II), following this process, a low-dose implantation proceeds after resist removal, creating LDD 12/14 regions in the gap, where the gates are etched redundantly. For fabrication of structure (III), the LDD region 12/14 may be implanted first, and after the resist is removed the source / drain regions 8/10 are photo-lithographically defined and implanted. do. Alternatively, the same layer of resist can be used to define the source / drain regions and then patterned again for the LDD implantation step.

As mentioned above, today, p-channel devices do not appear to require a field-removal structure to meet the stability criteria for current polysilicon AMLCD applications. See, for example, the paper cited above by Jay Ayres et al. Therefore, the device structure shown in FIG. 1 has been studied only for n-channel TFTs.

The gap or offset 18 in the structures I to III can be fabricated in the following manner. The gate electrode 2 is limited to lithography and is etched with a mixed solution of phosphoric acid, acetic acid and nitric acid and water (vol%, 16: 1: 1: 2) at a temperature of 40 ° C. The most consistent results and minimum gap length variations are obtained when the etching and overlapping etching of the gate do not remove a sample from the mixed solution after a single stage, ie after etching. The length of the gap can be measured directly through the resist defining the gate after overlapping etching. However, if the gap length is calculated from the difference between the length of the resist before etching and the length of the gate after resist removal, a more accurate result is obtained.

The relationship between the gap length and the total etch time for a sputtered aluminum-titanium metal alloy (titanium at 4% by weight) of thickness 260 nm is shown in FIG. 2. The standard deviation increases strongly for gap lengths greater than 1 μm. 3 shows an SEM micrograph of the overlapped etched gate metal under resist mark 20.                 

The overlap etching technique allows the formation of short submicron LDDs and offset regions. The overlapping etching technique also compares structure (I) (gap) and structure (III) (n ⁻ & gap) with structure (II) (n ⁻ in gap) and current SA LDD devices, The impact of residual injection damage on stability is shown. Introducing uninjected gaps in structures (I and III) is advantageous for excimer laser dopant activity because the laser beam will irradiate the entire LDD or source / drain (S / D) regions, while In the absence, there will be unannealed lateral damage under the gate for devices with S / D or LDD regions self-aligned to the gate.

TFTs with non- implanted gaps illustrate the role of extended junctions to provide field-removal. During laser activity, the dopant dissolves in the gap / n ⁺ junction {structure (I)}, the gap / n ⁻ junction {structure (III)} as well as the n ⁻ / n ⁺ junction {structures (II and III)}. Will diffuse sideways into the silicon. However, in structure (II), there will be no such diffusion in the channel / n ⁻ junction, but instead this junction will be steep as there may be residual implant damage. Lateral diffusion of the dopant provides an extended junction that reduces the peak electric field at the junction. This in turn reduces any unavoidable degeneration that is believed to be due to avalanche currents (kink effect) and hot-carrier damage. This also reduces the magnitude of the field-enhanced leakage current.

TFT mobility data for the device discussed above will now be considered with respect to FIG. 4.

4 shows the injection dose for structures I-III, with field effect mobility of the TFT with a channel length of 6 μm versus data for SA and SA LDD devices. For rescue (II, III) and SA LDD devices, the infusion dose corresponds to low-dose LDD infusion, while representing the S / D dose in the SA and rescue (I) devices. Data points are simply connected by lines to make it easier to distinguish data from different devices. All structures (III) (n ⁻ & gap) and SA LDD devices have an LDD length of 3 μm.

In Figure 4, it can be seen that the mobility increases with the infusion dose, which may be attributed to the decrease in LDD or S / D series resistance. Mobility decreases with increasing gap length in structures (II) (n ⁻ in the gap) and in structures (III) (n ⁻ & gaps), and in structure (III), the mobility is offset not injected The larger sheet resistance of the region decreases faster with respect to the gap length. However, for clarity, mobility data for only one LDD length is shown in FIG. 4. Despite the additional series resistance resulting from the 0.5 μm gap in the structure (III) (n ⁻ & gap), the mobility of this device is less than that of the SA LDD TFT with the same LDD length of 3 μm. Higher for LDD dose. Indeed, a structure (III) TFT having a gap of 0.5 μm and a high LDD concentration of 1 × 10 ¹⁴ P / cm ² exhibits greater mobility than conventional SA TFTs, wherein the structure (III) TFTs are 5 × 10. ^For S / D infusion doses of ¹⁴ P / cm ² typically have a mobility of 130 cm ² / Vs. This allows the introduction of a fully self-aligned submicron offset region into the gate to allow full dopant activity by the laser, and if the offset region is small enough, the series resistance due to residual implant damage is due to the diffusion of the dopant into the dopant. It is suggested that the on-current can be reduced more than the small offset region. The data in FIG. 4 shows that structure (III) devices with gaps of 0.7 μm and 0.9 μm show a strong decrease in mobility, especially for low LDD doses.

TFT on-current is reduced due to the S / D and LDD series resistance, R. The presence of non- implanted gaps in structures (I and III) and residual implant damage of SA, SA LDD, and structure (II) (n ^{-in the} gap) devices will introduce additional resistance ΔR and add to these devices Will bring on-current reduction. Assuming a total series resistance of R + ΔR, the mobility μ ₀ obtained from the TFT transfer characteristic (mutual conductance) is

,

,

에 의해 주어진 채널 저항임.)Where R _Ch is

Is the channel resistance given by.)

By the charge-carrier mobility μ ₀ in the channel.

The resistance R can be calculated from the area resistance of the polysilicon film injected at low dose (LDD) and high dose (S / D) and the dimensions of the LDD and S / D areas (van der Pauws measurement Using}. Mobility μ ₀ The total series resistance R + ΔR can be estimated from a TFT with a sufficiently long channel that can be ignored when compared to the channel resistance. μ ₀ can be estimated even without any residual implant damage from the NSA reference TFT without LDD. Thus, the measurement of the surface resistance and mobility μ together with the evaluation of the channel mobility μ ₀ from a suitable reference TFT allows the estimation of the resistance of the uninjected gap and the residual injection damage.

For SA, SA LDD, and structure (II) (n ⁻ ) gaps with 6 μm channel length, we only calculated the expected mobility reduction considering S / D and LDD series resistance. The channel mobility μ ₀ was on the order of 200 cm ² / Vs to 250 cm ² / Vs, estimated from a reference TFT with a channel length of 60 μm. For all three TFT structures, the measured mobility falls short of the mobility corrected for R only, indicating residual implant damage. This has been confirmed in the SA TFT, and the results discussed are even used here, as is the case for the device of SA LDD and structure II (n ^{− in the} gap) with the lowest LDD dosage shown in FIG. 4. Even if the injection dose to such an area is reduced by factor 50, it confirms that the injection damage near the gate edge cannot be eliminated. The resistance ΔR can be calculated from the above equation, and for all the samples investigated, it was found that ΔR increases with increasing infusion dose, and that the extent of damage simply increases with dose.

Structure (III) (n ^- & gap) The use of the equations shows that for the resistance of the non-injection gap that decreases with the increase in the LDD dose. This decrease in resistance is the result of higher dopant concentrations in the gap for higher LDD doses due to diffusion from adjacent LDD regions in the dissolved silicon during excimer-laser dopant activity. Similarly, in structure (I), a reduced gap resistance is observed in the TFT administered the higher S / D injection dose.

Although SEM micrographs show that the size of the area with residual implantation damage is much smaller than the gap, the series resistance due to implantation damage is equal to the resistance of the 0.7 μm and 0.5 μm unfilled gaps in structures (III and I), respectively It is noteworthy to be comparable. In addition, unlike the non-implanted region, the region with residual implant damage is sufficiently modulated by the gate, reducing its resistance.

Low leakage current is an important requirement for polysilicon TFTs to be used as pixel TFTs in AMLCD applications. The data discussed below demonstrate the gain of the non-injected gap to obtain low current in the off-state leading to a high gate voltage.

FIG. 5 shows the relationship between injection dose and minimum leakage current for SA and SA LDD devices for structures I-III and comparison. The minimum is V _G = 0 ± 1V for all devices. It can be seen immediately that the introduction of the non-injected gap drastically reduces the leakage current. The presence of a 0.5 μm gap in structure (III) indicates structure (II) (n ^{− in the} gap) and SA for all LDD doses. Compared with both LDD devices, the leakage current is reduced by factor 10 to factor 30, and if SA is compared with the structural (I) device, there is a much stronger reduction in leakage current, i.e. a reduction in leakage current by factor 80. Will be. The observation of high leakage currents in SA and SA LDD can be explained by the number of mid-gap trap states near the drain due to residual injection damage. The increase in leakage current observed with increasing dose is the result of an increase in infusion damage with increasing dose, as noted above. In the absence of residual injection damage, the leakage current is low and independent of dosage, as can be seen in devices with non-injected gaps (structures I and III).

The data in FIG. 6 correlates the minimum leakage current shown in FIG. 5 with the current at a gate voltage of -10V. The ratio of these currents is shown as a function of the infusion dose. Devices with non-injected gaps (structures I and III) show a very small increase in leakage current when proceeding from the current minimum at 0V to -10V. There is no consistent trend between current ratio and infusion dose for device structures I-III. For structure II (n ^{− in the} gap) and the SA LDD device, the leakage current ratio is larger and increases strongly with the injection dose, reaching a maximum current ratio of approximately 200 in the SA TFT.

To further investigate leakage current and field-rejection issues, we measured the I _D -V _D curve in the off-state, and compared the slope of the log (I _D ) -V _D curve to the gate voltage of -10 V. Infusion doses are shown in FIG. 7. The slope is proportional to the factor that relates the electric field to the applied voltage. It can be seen that the greater in than the SA LDD devices in structure (III) ^- the slope of the structure (III) (& gap n) ^- in spite of a large variation in the dose of LDD dose in the (n & gap) data The data seems to suggest that the electric field increases more strongly with increasing infusion dose in SA LDD and SA devices than in structure (III) devices. The smaller slope of the log (I _D ) -V _D curve of the structure (III) device and the lower current ratio (see FIG. 6) for the structure (I and III) devices are low current in the off-state leading to the high gate voltage This clearly demonstrates the benefits of field-removal through extended junctions and junction offsets to obtain.

Finally, with regard to leakage current and field-rejection, there is only a minor difference between the SA LDD and the structure (II) device (n ^{− in the} gap), and the LDD length is the electric field distribution at the channel / LDD junction. It will be appreciated from FIGS. 5 and 6 that it does not have a significant effect. These results were confirmed for LDD lengths ranging between 0.3 μm and 3 μm. For clarity, FIGS. 5 and 6 only show data for structure (II) devices with a gap of 0.7 μm. Thus, for SA LDD devices, as long as leakage current and field-rejection are involved, an LDD length of 3 μm can be reduced to submicron length without compromising the leakage current using controlled overlap-etching of the gate. Can be.

8A and 8B show the output characteristics (clogged symbols) recorded at V _T -1V of the structure (III) device (n ⁻ & gap) and SA LDD device, respectively, with various LDD infusion doses administered. It can be seen that the drain current increases strongly with the LDD dose for both device structures, in particular a critical doping range between 9 x 10 ¹² P / cm ² and 3 x 10 ¹³ P / cm ² . Within this range, the current is strongly increased for both structures. It can also be seen that the critical drain voltage with a strong current increase above it decreases with increasing injection dose. For the two highest doses in FIGS. 8A and 8B, the kink effect is shifted by approximately 2V to the higher drain voltage in the structure (III) TFTs. This measurement clearly demonstrates that drain-field-removal is obtained with low dose infusion, and this effect is increased by extended offset conjugation. This result is consistent with the leakage current data discussed above.

The stability of the device structures (I to III) was compared with that of the standard SA LDD device from Koninkeke Phillips. Some of these results are summarized in FIGS. 8A and 8B, which show TFT on-current loss (open symbol) in the linear region after applying drain bias stress for 1 minute, during which time the gate bias The threshold voltage was set, which represents the worst case stress condition.                 

Derived from the data shown in FIGS. 8A and 8B, FIG. 9 compares the characteristic drain voltage with the two device structures in FIGS. 8A and 8B exhibiting a 30% on-current reduction. Data for the structure (I) device (gap) is also shown. It can be appreciated that the introduction of the gap improves device stability by 1-3V, for the structure (III) device. The SA LDD device becomes less stable with increasing LDD dose, thereby reaching the stability of the SA device. From the data in FIG. 9, there is no strong relationship between stability and LDD dose in the Structure (III) device. For devices administered an infusion dose of 6 x 10 ¹³ P / cm ² , higher stability is obtained, from which data is a small infusion dose, whether this is an artefact or an improved stability can be obtained therein. It is not clear whether the window exists. For structure II (n-in ^- gap) devices, the stability is independent of the length of the LDD region for lengths between 0.3 μm and 3 μm. The stability of these devices decreases with increasing LDD dosage and is comparable to SA LDD devices.

The introduction of small offset regions (structures I and III) addresses the problems identified for conventional SA and SA LDD TFTs. These devices exhibit low on-current due to series resistance, high leakage current and poor stability. Residual implantation damage near the gate edge reduces mobility in laser-activated SA and SA LDD devices. When there is a non- implanted gap, implantation damage can be completely eliminated by irradiating the laser with the entire LDD and S / D regions, allowing the device to have higher mobility and lower leakage current. The additional series resistance due to the offset area does not provide an issue if the length is smaller than 0.5 μm. The gap provides field-removal through expanding bonding and offsetting. This results in a significant reduction in the electric field enhanced leakage current. It also reduces avalanche and improves device stability.

The TFT of FIG. 1 has an uninjected gap exposed to laser annealing by reetching the gate. 10 illustrates a process that can be used to optimize SA GOLLD TFTs with respect to low gate-drain capacitance and low leakage current. In this case, the gap region exposed to laser annealing is pre-annealed (n−) before the LDD region is injected in advance.

In FIG. 10A, device islands 30 were formed on substrate 32 and lightly doped n-regions 34 and 36 were formed by implantation using a resist mask (not shown). They will eventually form LDD regions 33 and 35. In addition, the damage associated with the ion implantation is shown (roughly dotted). This extends throughout the implanted area and beyond the lines 38 and 40 corresponding to the mask edge (as doping) position, typically in the same amount as the implantation range.

In FIG. 10B, the film is annealed by an energy beam 42, typically laser irradiation. This crystallizes the material, forming good quality polysilicon, activating the n-dope, annealing away the damage, gradating the junction edges, and further reducing the amount of side dopant diffusion. (0.25 micron or less).

In c of FIG. 10C, the gate structure is formed by patterning and etching the insulator 44, followed by the metal 46, and then the metal with the photoresist 48. The metal is preferably high reflective and smooth, and may comprise an Al alloy or a Ti / Al double layer. High doses (n +) of phosphorus ions 50 are now implanted to form source and drain contacts 52 and 54. This process sequence is based on a known self-aligned gate-overlapped lightly-doped-drain structure (SAGOLDD). SAGOLDD has a gate that overlaps the LDD regions 33 and 35 which are essential for the best stability, but minimizes overlap capacitance due to self-matching of the LDD / n + junction to the gate.

However, c in FIG. 10C shows the implantation damage (approximately dotted) associated with n +, which implantation extends laterally under the gate 46. It is normal to perform secondary laser annealing to activate the dopant in this stage, but this leaves a damaged area under the gate through which the laser light cannot penetrate.

In FIG. 10C d, an additional process step is shown, which is to reetch the metal again (as shown by arrow 56), typically etched by 0.25 microns-0.5 microns so that the damaged area is laser lighted. Access to 42 (e of FIG. 10C). The implanted photoresist is very stable and is a rigid mask. This laser step activates the n + dopant, removes the lattice damage, and gradually transitions from n + to n-. In this way, as shown in FIG. 10D, two LDD subregions (one 58 overlaps and the other 60 non-overlapping) are formed, leaving no residual damage. The non-overlapping bottom region 60 is very narrow and does not add any recognizable series resistance.

An advantage of the process of the present invention disclosed herein is that the photoresist mask 48 is cured by implantation, making it a very robust mask for reetching if performed after implantation. Oxygen plasma ashing is then typically required for mask removal.

Immersion etching is preferred for the reetch. However, it will be apparent to one skilled in the art that alternative processes may be used. If a spray etcher is used instead, the desired reetch may be more difficult to achieve with a high degree of reproducibility. In this case, the desired reetching can be precisely achieved by wet anodization (eg in diethelyene glycol) or by plasma anodization. Composite triple anodization is described on pages 29-31 of a paper by Yoshinouchi et al. Published in the AMLCD Workshop 1996, which is used to form LDD regions (in non-overlapping TFT devices). The entire contents of the AMLCD Workshop papers are incorporated herein by reference. At least one of the three anodizations is very necessary to form a rigid mask over the upper metal surface for side anodization. The techniques described herein may also be advantageous for the device process as cured resist masking can replace this rigid mask anodization step to reduce the number of anodization required.

Upon reading this disclosure, other variations and modifications will be apparent to those skilled in the art. Such modifications and variations may include equivalent and other features as are already known in the design, fabrication, and use of electronic devices, including thin film circuits, semiconductor devices, and components thereof, which are already described herein. Can be used instead or in addition to it.

Although the claims are formulated with specific combinations of features in the present application, either explicitly or indirectly or arbitrarily combining them, the scope of the present disclosure, whether or not related to the invention as currently claimed in any claim, and the present It is to be understood that the invention includes any novel feature or any novel combination of features disclosed herein, whether or not alleviating any or all of the same technical problems as the invention. Features described in connection with a separate embodiment may also be provided in combination in a single embodiment. Conversely, in brief, the various features described in connection with the hole embodiment can also be provided in separate or any suitable subcombination. As such, Applicants disclose that new claims may be formulated with such features and / or combinations of such features during the prosecution of the present application or any further application derived therefrom.

As described above, the present invention is used in a method of manufacturing an electronic device including a thin film transistor.

Claims (15)

An electronic device manufacturing method comprising a thin film transistor, (a) depositing a gate layer 46 on the insulating film 44 over the semiconductor film 30, (b) defining a patterned mask layer 48 over the gate layer 46; (c) etching to pattern the gate layer 46 using the mask layer 48, and etching back the gate layer 46 under the mask layer; (d) implanting a dopant into the semiconductor film 30 using the mask layer 48 and the gate layer 46 as an implantation mask, (e) removing the mask layer 48; (f) annealing the semiconductor film 30 with an energy beam. An electronic device manufacturing method comprising. The method of claim 1, further comprising, after step (e), an additional implantation step that provides a lower doping level than step (d). The method of claim 1, wherein step (b) (h) defining a source / drain pattern mask layer, (i) performing an implantation step that provides a higher doping level than step (d) to form source and drain regions 8, 10 defined by the source / drain pattern, wherein step (d) Performing an implantation step in which a region exposed only to an implantation of an LDD region is formed; (j) patterning the mask layer to define a gate pattern An electronic device manufacturing method comprising. The method of claim 1, wherein after step (c), (k) defining a source / drain pattern in another mask layer, (l) performing an implantation step that provides a higher doping level than step (d) to form source and drain regions 8, 10 defined by the source / drain pattern, wherein step (d) Performing the implantation step of forming the LDD regions 12 and 14 in the region exposed only to the implantation of Further comprising, the electronic device manufacturing method. The method of claim 1, prior to step (a), (m) defining an initially patterned mask layer, (n) an implantation step using said initial mask layer as an implantation mask, said implantation being doped lower than step (d) in regions extending laterally and inwardly beyond the edge of said patterned mask formed in step (b) Performing an injection step providing a level, (o) annealing the semiconductor film with an energy beam Further comprising, the electronic device manufacturing method. 6. The method of claim 5, wherein after the reetching of step (c), the gate layer (46) overlaps over a portion of the implanted region formed in step (n). 7. A method according to any one of the preceding claims, comprising anodizing (p) the gate layer (2, 46) prior to step (c). 7. A method according to any one of the preceding claims, wherein the gate (2, 46) is reetched by an interval in the range of between 0.3 μm and 3 μm in step (c). 9. A method according to claim 8, wherein the gate (2, 46) is reetched in step (c) by an interval in the range of 0.25 [mu] m to 0.5 [mu] m. The method of claim 1, wherein the gate layer comprises aluminum or titanium and an aluminum bilayer. 7. A method according to any one of the preceding claims, wherein a plurality of said thin film transistors are formed on a substrate as switching elements of a matrix. delete delete delete delete

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