KR100763336B1 - Semiconductor memory device and arrangement method of memory cell array thereof - Google Patents

Abstract

A semiconductor memory device and a method for arranging a memory cell array of the same are provided to reduce a layout area, to improve noise immunity by using a folded bit line structure, and to reduce the number of sense amplifiers in a sense amplifying unit. A semiconductor memory device includes a plurality of word line pairs(WL1 to WL8), a plurality of bit line pairs, and a memory cell array. The plurality of bit line pairs(BL1 to BL4B) are arranged vertically to the word lines. Each bit line pair are composed of a bit line and a reverse bit line adjacent to each other. The memory cell array are composed of first to fourth memory cells(MC1 to MC4). Each memory cell includes a transistor of a buried gate structure and a capacitor. The transistor is connected with the reverse bit line between first lines of one word line pair and the bit line between second lines of another word line pair.

Description

Semiconductor memory device and arrangement method of memory cell array

1 is a plan view for explaining the arrangement of a memory cell array of a semiconductor memory device having a transistor of a conventional buried gate structure.

FIG. 2 shows a circuit configuration according to the arrangement of the memory cell array shown in FIG.

FIG. 3 is a simplified cross-sectional view when the memory cell array shown in FIG. 1 is cut in the direction A-A '.

4 is a block diagram illustrating a memory cell array having a general open bit line structure.

Fig. 5 is a plan view for explaining an arrangement of a memory cell array having transistors of a buried gate structure of the present invention.

FIG. 6 shows a circuit configuration in accordance with the arrangement of the memory cell array shown in FIG.

FIG. 7 is a simplified cross-sectional view when the memory cell array shown in FIG. 5 is cut in the direction B-B '.

Figure 8 is a block diagram illustrating a memory cell array having a folded bit line structure of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device having a transistor having a buried gate structure, and a memory cell array arrangement method thereof.

The memory cell of the dynamic semiconductor memory device of the semiconductor memory device is composed of one transistor and one capacitor, and stores data by accumulating charge in the capacitor. However, since data accumulated in the capacitor is lost over time, a refresh operation is required, and power consumption increases due to such a refresh operation. It is also possible to increase the size of the capacitor to increase the refresh period, but this is not a preferable method because the layout area increases as the size of the capacitor increases.

Therefore, a recess channel array transistor (RCAT) has been developed that can reduce the layout area of the semiconductor memory device and increase the refresh period, that is, increase the data retention time. It is adopted in a memory device.

Recently, a buried gate structure transistor has been introduced that can increase the data retention time while reducing the layout area during integration than the recess channel array transistor.

FIG. 1 is a plan view for explaining an arrangement of a memory cell array of a semiconductor memory device having a transistor of a conventional buried gate structure, and FIG. 2 is a circuit configuration according to the arrangement of the memory cell array shown in FIG.

The arrangement of the memory cell array will be described with reference to FIGS. 1 and 2 as follows.

The word lines WL are disposed at the same distance a in the horizontal direction, the bit lines BL are disposed in the direction orthogonal to the word lines WL, and the memory cells MC1 and MC2 are diagonally disposed. Is placed. Transistor and memory cell MC2 of a region in which even-numbered bit lines BL2 and BL4 are disposed between two adjacent word lines WL1 and WL2 to WL7 and WL8. A contact (not shown) is disposed in the common active region 10 of the transistor of FIG. 8, and the odd-numbered bit lines BL1 and BL3 between two adjacent word lines WL2 and WL3 to WL6 and WL7 are disposed. The contact is disposed in the region where this is arranged, that is, the common active region 10 of the transistor of the memory cell MC3 and the transistor of the memory cell MC4. The gate region 12 and the active region 14 of the transistors of each of the memory cells MC1 ˜ MC4 are sequentially disposed in both diagonal directions with respect to the contact. The word line WL is disposed in the gate region 12, and a capacitor (not shown) of each of the memory cells MC1 to MC4 is disposed on the active region 14.

FIG. 3 is a simplified cross-sectional view when the memory cell array shown in FIG. 1 is cut in the direction A-A '.

n + active regions 14 and n + common active regions 10 are formed in the p-type substrate 1, and the buried gate region (between n + active regions 14 and n + common active regions 10) is formed. 12 is formed, and a word line WL is formed in the buried gate region 12. A bit line BL3 is formed on the n + common active regions 12 to be connected to the n + common active regions 10 and is connected to the n + active regions 14 on the n + active regions 14. Capacitor 16 is formed. In FIG. 3, only one electrode of the capacitor 16 is shown.

The transistors of the memory cell shown in Fig. 1 have a buried gate structure as shown in Fig. 3, and the distance between n + active region 42 and n + common active region 10, i.e., the distance a between word lines (a). Is shorter than the distance of a conventional recess channel array transistor (not shown). Accordingly, the layout area in the bit line direction of the memory cell array using the buried gate structure transistor is reduced, compared to the memory cell array using the recess channel array transistor.

The arrangement of the memory cell arrays shown in Figures 1-3 is based on the technique disclosed in US Pat. No. 6,770,535.

The memory cell array including the transistor of the buried gate structure described above has an open bit line structure in which memory cells are disposed between all bit lines and word lines, as shown in FIGS. 1 and 2.

4 is a block diagram illustrating a memory cell array having a general open bit line structure, wherein the memory cell array includes n memory cell array blocks BLK1 to BLKn, and n memory cell array blocks BLK1 to BLKn. (N-1) sense amplification units SA12, SA23, ..., SA (n-1) n are disposed between them.

As shown in FIG. 4, an inversion with the first memory cell array block BLK1, ... having memory cells connected between the bit lines BL1 to BL4,..., And the word lines WL. Memory cell array blocks BLK2, ... having memory cells connected between bit lines BL1B to BL4B, ... are alternately arranged, and the first memory cell array block and the second memory cell array block are alternately arranged. The sense amplifier part between the amplifies the data between the odd (even) bit line of the first memory cell array block and the odd (even) inverted bit line of the second memory cell array block.

However, a memory cell array having an open bit line structure has a disadvantage in that a yield of a semiconductor memory device is deteriorated due to poor operating characteristics due to poor noise immunity of the bit line.

In addition, a memory cell array having an open bit line structure has a disadvantage in that half of the memory cells of the memory cell array blocks disposed at the edge may not be used. That is, memory cells connected to the even-numbered bit lines of the memory cell array block BLK1 illustrated in FIG. 4 and memory cells connected to the inverted odd-numbered bit lines of the memory cell array block BLKn cannot be used.

Accordingly, while a semiconductor memory device having a memory cell array having a buried gate structure transistor has an advantage in that the layout area can be reduced, there are many disadvantages caused by having an open bit line structure.

Thus, there is a need for a new arrangement for a semiconductor memory device having a memory cell array having transistors of buried gate structure.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device having a memory cell array having a transistor of a buried gate structure that can reduce the layout area and eliminate the disadvantages caused by having an open bit line structure.

Another object of the present invention is to provide a method of arranging a memory cell array of a semiconductor memory device for achieving the above object.

A first aspect of the semiconductor memory device of the present invention for achieving the above object is a plurality of word line pairs having a distance greater than the distance between the lines constituting one word line pair, the direction perpendicular to the word line A plurality of bit line pairs arranged in parallel with each other, and a bit line pair having a bit line pair and an inverting bit line adjacent to each other, and a common connection with the inverting bit line disposed between the lines forming the one word line pair. Buried and symmetrically disposed in the diagonal direction and connected in common with the bit line disposed between the lines forming the other word line pair arranged adjacent to the one word line pair The first to fourth memory cells each having a gate transistor and a capacitor are provided. A mori cell array is provided.

The buried gate structure transistors of the first and second memory cells are commonly connected to an inverted bit line disposed between the lines forming the one word line pair, and each of the lines forming the one word line pair is connected to each other. A transistor of the buried gate structure of the third and fourth memory cells having a gate connected to each of the capacitors disposed opposite to each other, and connected to each of the lines forming the one word line pair. A common connection to the bit lines disposed between the lines constituting another word line pair, a connection to each of the capacitors disposed opposite each other with the lines constituting the other word line pair interposed therebetween, And a gate connected to each of the lines forming the other word line pair. All.

Capacitors of each of the first and second memory cells are disposed closer to each of the lines constituting the one word line pair than the inverted bit line, and capacitors of each of the third and fourth memory cells are disposed more than the bit line. It is characterized in that it is disposed close to each of the lines constituting the other word line pair.

A second aspect of the semiconductor memory device of the present invention for achieving the above object comprises a plurality of memory cell array blocks, and a sense amplifier disposed between the plurality of memory cell array blocks, the plurality of memory cell arrays Each of the blocks includes a plurality of word line pairs arranged at a distance greater than a distance between the lines constituting one word line pair, a bit line disposed in a direction orthogonal to the word line and forming a single bit line pair; A plurality of bit line pairs in which inverted bit lines are disposed adjacent to each other, and the inverted bit line commonly connected to the inverted bit line disposed between the lines constituting the one word line pair, and arranged in a symmetrical direction in the diagonal direction; The interposed between the lines forming another word line pair disposed adjacent to the line pair And bit lines commonly connected and characterized in that it comprises the first to fourth memory cells includes a transistor and a capacitor of the buried-gate structure that is symmetrically arranged in the diagonal direction.

In another aspect of the present invention, there is provided a method of arranging a memory cell array of a semiconductor memory device, the method comprising: a memory cell array having a transistor and a capacitor having a buried gate structure; Arrange a plurality of word line pairs having a distance larger than the distance between the lines constituting one word line pair, and the bit line and the inverting bit line constituting one bit line pair in a direction orthogonal to the word line are adjacent to each other. And a plurality of bit line pairs.

The disposition method arranges the first and second memory cells of the memory cells in a diagonal direction and is connected in common with the inverted bit line disposed between the lines constituting the one word line pair. Disposing third and fourth memory cells of the memory cells symmetrically in the diagonal direction and commonly connected to the bit line disposed between the lines constituting another word line pair adjacent to the line pair; It is done.

The disposition method arranges capacitors constituting the first and second memory cells in a diagonal direction on the opposite side with each of the lines constituting the one word line pair interposed therebetween, and lines forming the one word line pair. A buried gate structure of the first and second memory cells having a gate commonly connected to the inverting bit line disposed between the capacitor lines, and connected to each of the capacitors and to each of the lines constituting the one word line pair Arrange the transistors, and place capacitors constituting the third and fourth memory cells in a diagonal direction on the opposite side with each of the lines constituting the other word line pair interposed therebetween, and the other word line pair A common connection to the bit lines disposed between the constituent lines, and to each of the capacitors, The transistor of the buried gate structure of the third and fourth memory cells having a gate connected to each of the lines forming another word line pair may be disposed.

Hereinafter, a semiconductor memory device and a method of arranging a memory cell array of the present invention will be described with reference to the accompanying drawings.

FIG. 5 is a plan view for explaining an arrangement of a memory cell array having a transistor of a buried gate structure according to the present invention, and FIG. 6 shows a circuit configuration according to the arrangement of the memory cell array shown in FIG.

The arrangement of the memory cell array of the present invention will be described with reference to FIGS. 5 and 6 as follows.

Word lines WL1 to WL8 are disposed in the vertical direction, and bit line pairs (BL1, BL1B) to (BL4, BL4B) are disposed in the direction orthogonal to the word lines WL1 to WL8, and memory is disposed. The cells MC1, MC2, MC3, and MC4 are arranged in a diagonal direction. The distance c between the lines constituting each of the word line pairs (WL1, WL2) to (WL7, WL8) is the distance c between the adjacent word line pairs (WL1, WL2) to (WL7, WL8). Shorter than). A region in which the inverted bit lines BL1B to BL4B are disposed between the pair of word lines WL1 and WL2 and WL5 and WL6, that is, a transistor of the memory cell MC1 and a transistor of the memory cell MC2. The contact 41 is disposed in the common active region of the memory cell and the bit lines BL1 to BL4 between the pair of other word lines WL3 and WL4 to WL7 and WL8 are disposed, that is, the memory cell. A contact (not shown) is disposed in the common active region 30 of the transistor of MC3 and the transistor of memory cell MC4. The gate region 32 and the active region 34 of the transistors of each of the memory cells MC1 to MC4 are sequentially disposed in both diagonal directions with respect to the contact. Word lines WL1 ˜ WL8 are disposed in each of the gate regions 32, and capacitors (not shown) of each of the memory cells MC1 ˜ MC4 are disposed on the active region 43. Each of the memory cells MC1 to MC4 is disposed in a diagonal direction with a larger slope than that of the memory cells shown in FIGS. 1 and 2.

As shown in Figs. 5 and 6, in the memory cell array of the present invention, not all word lines are arranged with the same distance, but the distance between the lines constituting the word line pair is smaller than the distance between adjacent word line pairs. It is arranged and has a folded bit line structure. That is, memory cells are connected between one of the bit line pairs of the memory cell array and the word line. In the case of a folded bit line structure, one of a bit line and an inverted bit line constituting another pair of bit lines may be disposed between a bit line constituting a pair of bit lines and an inverted bit line. In the memory cell array of the present invention shown in Fig. 6, bit lines constituting a pair of bit lines and inverted bit lines are disposed adjacent to each other.

FIG. 7 is a simplified cross-sectional view when the memory cell array shown in FIG. 5 is cut in the direction B-B '.

n + active regions 34 and n + common active regions 30 are formed in the p-type substrate 1, and the gate region 32 is interposed between the n + active regions 34 and the n + common active regions 30. ) Is formed, and word lines WL1 to WL4 are formed in each of the gate regions 32. A bit line BL is formed on the n + common active regions 30 and connected to the n + common active regions 30, and connected to the n + active regions 34 on the n + active regions 34. Capacitor 56 is formed. In Fig. 7, only one electrode of the capacitor 16 is shown.

8 is a block diagram illustrating a memory cell array having a folded bit line structure according to an embodiment of the present invention, wherein the memory cell array includes k memory cell array blocks BLK1 to BLKk and k memory cell array blocks ( (K + 1) sense amplifiers SA1, SA12, ..., SAk are disposed on both sides of BLK1 to BLKk.

As shown in FIG. 8, k memory cell array blocks having memory cells connected between bit line pairs (BL1, BL1B) to (BL4, BL4B, ...) and word lines WL. And BLK1 to BLKk, and the sense amplifier SA is shared by two memory cell array blocks disposed at both sides. That is, the sense amplifier disposed in the sense amplifier unit is used to amplify the data of the bit line pair of the memory cell array block disposed on the left side and also to amplify the data of the bit line pair of the memory cell array block disposed on the right side. Used.

A memory cell array having memory cells including a transistor of a conventional buried channel structure has an open bit line structure and one capacitor is disposed in an area between a word line and a bit line. Two capacitors are disposed in a region between two adjacent word lines and a bit line and an inverting bit line, each having a decoded bit line structure.

The semiconductor memory device of the present invention may be fabricated by any process using a buried gate structure transistor. The semiconductor memory device may have the arrangement of the present invention in all cases in which a memory cell array is manufactured using a buried gate structure transistor.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

The semiconductor memory device of the present invention and a method of arranging a memory cell array of the device can reduce the layout area by forming transistors of the memory cells of the memory cell array in a buried gate structure, and by arranging them in a folded bit line structure. The noise immunity is improved and all the memory cells of the memory cell array blocks arranged at the edge can be used. In addition, in the memory cell array having the open bit line structure, the sense amplifiers disposed in the sense amplifier are implemented one by one for a pair of bit lines, whereas the memory cell array having the folded bit line structure is sense amplifier disposed in the sense amplifier. Since is implemented one by one for two pairs of bit lines, the number of sense amplifiers disposed in the sense amplifier is reduced.

Claims (10)

A plurality of word line pairs disposed with a distance greater than a distance between the lines constituting the word line pair; A plurality of bit line pairs arranged in a direction orthogonal to the word line and having a bit line and an inverted bit line adjacent to each other forming one bit line pair; And Lines connected in common with the inverted bit lines disposed between the lines forming one word line pair, symmetrically arranged in a diagonal direction, and lines forming another word line pair disposed adjacent to the one word line pair. And a memory cell array including first to fourth memory cells each having a transistor and a capacitor having a buried gate structure connected in common with the bit line disposed between the bit lines and symmetrically disposed in the diagonal direction. Semiconductor memory device. The transistor of claim 1, wherein the buried gate structure of the first and second memory cells A common connection to an inverting bit line disposed between the lines constituting the one word line pair, a connection to each of the capacitors disposed opposite each other with the lines constituting the one word line pair interposed therebetween, Has a gate connected to each of the lines constituting one word line pair, The buried gate structure of the third and fourth memory cells transistor A common connection to the bit lines disposed between the lines forming the other word line pair, and a connection to each of the capacitors disposed opposite each other with the lines forming the other word line pair interposed therebetween; And a gate connected to each of the lines forming the other word line pair. The method of claim 1, wherein the capacitors of each of the first and second memory cells Disposed closer to each of the lines forming the single word line pair than the inverted bit line, Capacitors of each of the third and fourth memory cells And closer to each of the lines forming the other word line pair than the bit line. A plurality of memory cell array blocks; And A sense amplifier disposed between the plurality of memory cell array blocks; Each of the plurality of memory cell array blocks A plurality of word line pairs disposed with a distance greater than a distance between the lines constituting the word line pair; A plurality of bit line pairs arranged in a direction orthogonal to the word line and having a bit line and an inverted bit line adjacent to each other forming one bit line pair; And Lines connected in common with the inverted bit lines disposed between the lines forming one word line pair, symmetrically arranged in a diagonal direction, and lines forming another word line pair disposed adjacent to the one word line pair. And first to fourth memory cells each having a transistor and a capacitor having a buried gate structure connected in common with the bit line and symmetrically disposed in the diagonal direction. The transistor of claim 4, wherein the buried gate structure of the first and second memory cells A common connection to an inverting bit line disposed between the lines constituting the one word line pair, a connection to each of the capacitors disposed opposite each other with the lines constituting the one word line pair interposed therebetween, Has a gate connected to each of the lines constituting one word line pair, The buried gate structure of the third and fourth memory cells transistor A common connection to the bit lines disposed between the lines forming the other word line pair, and a connection to each of the capacitors disposed opposite each other with the lines forming the other word line pair interposed therebetween; And a gate connected to each of the lines forming the other word line pair. The method of claim 4, wherein the capacitors of each of the first and second memory cells are formed. Disposed closer to each of the lines forming the single word line pair than the inverted bit line, Capacitors of each of the third and fourth memory cells And closer to each of the lines forming the other word line pair than the bit line. A method of arranging a memory cell array in a semiconductor memory device having memory cells each including a transistor having a buried gate structure and a capacitor, the method comprising: Arranging a plurality of word line pairs having a distance greater than the distance between the lines constituting the word line pair, And arranging a plurality of bit line pairs such that bit lines constituting one bit line pair and inverted bit lines are adjacent to each other in a direction orthogonal to the word line. 8. The method of claim 7, wherein the placement method is Arranging first and second memory cells of the memory cells in common with the inverted bit line disposed between the lines forming the one word line pair and symmetrically in a diagonal direction; Third and fourth memory cells of the memory cells that are connected in common with the bit line disposed between the lines forming another word line pair adjacent to the one word line pair and symmetrically in the diagonal direction And arranging a memory cell array of the semiconductor memory device. The method of claim 8, wherein the placement method is Capacitors constituting the first and second memory cells in a diagonal direction on the opposite side with each of the lines constituting the one word line pair interposed therebetween, The first having a gate connected to each of the inverted bit lines disposed between the lines constituting the one word line pair, the gate connected to each of the capacitors, and a gate connected to each of the lines constituting the one word line pair. Disposing a transistor of a buried gate structure of the first and second memory cells, Capacitors constituting the third and fourth memory cells in a diagonal direction on the opposite side with each of the lines constituting the other word line pair interposed therebetween, The gate having a gate connected to each of the bit lines disposed between the lines forming the other word line pair, connected to each of the capacitors, and connected to each of the lines forming the other word line pair. And arranging transistors of the buried gate structure of the third and fourth memory cells. The method of claim 9, Disposing the capacitors of each of the first and second memory cells closer to each of the lines constituting the one word line pair than the inverting bit line; And arranging the capacitors of each of the third and fourth memory cells closer to each of the lines constituting the other word line pair than the bit line.

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