KR100406545B1 - Memory device with improved precharge characteristic in bit line sensing and amplification - Google Patents

Abstract

The present invention improves the operation characteristics of the memory device by changing the layout of the sense amplifier precharge unit without increasing the chip size. A bit line detection amplifier formed corresponding to each of the pairs of bit lines, the bit line sensing amplifier having a first precharge section for amplifying bit lines after the amplification; And a second precharge unit connected between the sub bit line of one bit line pair and the positive bit line of another bit line pair, wherein the one bit line pair and the other bit line pair are formed adjacent to each other. It is composed.

Description

Memory device with improved precharge characteristic in bit line sensing and amplification

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and in particular, to improve the operation characteristics of the semiconductor memory device by changing the layout of a sense amplifier precharge unit.

The main purpose of the bit line sensing amplifiers used in semiconductor memory devices is to effectively detect very small voltage differences between the pairs of bit lines bl and blb, and amplify the small signals to This is to discriminate by signal.

In a semiconductor memory, such as a DRAM, which constitutes a minimum memory device unit with one transistor and one capacitor, a sensing amplifier is essential to make the charge stored in the memory device intact.

Sensing amplifiers operate with amplification and post-amplification initialization, which is currently used in most synchronous DRAMs (DRAMs) or double data rate SDRAMs. That's the way.

1 is a diagram illustrating a memory cell and a sense amplifier arranged in a conventional semiconductor memory device, and FIG. 2 is a diagram illustrating a layout of the sense amplifier precharge unit shown in FIG. 1. Referring to FIG. 1, it can be seen that one sensing amplifier 11 or 12 is connected to each pair of bit lines in order to input data into or read data from the memory cell 10.

The adjacent bit line pairs, i.e., bl / blb and bl1 / blb1, constitute empty spaces isolated according to a minimum design rule.

The sensing amplifier is composed of a precharge unit 11 and an amplifier unit 12 which precharges or equalizes the bit line BL and the sub bit line BLB to a predetermined potential. The precharge unit 11 includes a gate. MOS transistor A (MOS A) for equalizing the bit line BL and the sub bit line BLB by receiving the equalization signal bleq, and the bit line receiving the equalization signal bleq through the gate. It consists of a MOS transistor B (MOS B) and a MOS transistor C (MOS C) for precharging the BL and the sub bit line BLB to a constant potential VBLP, and the amplifying unit 12 has a positive bit line bl. ) And amplifies the voltage difference between the sub bit line blb.

FIG. 2 is a diagram illustrating three MOS transistors (MOS A, MOS B, and MOS C) constituting the precharge unit 11 in the circuit shown in FIG. 1. The bit line 15, the polysilicon 18 used as the gate electrode, to which the equalization signal bleq is applied, and the active region 17 to which the transistor is formed are shown, and the metal line to which the precharge voltage is applied is not shown. not.

Referring to FIG. 2, the conventional sensing amplifiers are formed apart from each other while keeping a minimum design rule between the active regions 17. Referring to FIG. That is, the conventional sense amplifiers have a rectangular active region 17 isolated for each sense amplifier, and the active regions 17 are separated from each other with a minimum limit of the space indicated as '1 SA Pitch'.

3A to 3C are diagrams illustrating principles and process cross-sections of three MOS transistors constituting the precharge unit 11 on a layout, and MOS A, MOS B, and MOD C are formed of respective polysilicon layers ( 18 and the relationship between the metal line 19, the positive bit line 14 and the sub bit line 15 are shown.

The MOS A for equalizing the bit line 14 and the bit line 15 is formed along the dotted line shown in the drawing, and the drain / source region is in contact with the bit line 14 and the bit line 15. It can be seen that the polysilicon layer 18 to which the equalization signal bleq is applied is used as the gate electrode.

The MOS B which precharges the positive bit line 14 and the sub bit line 15 to a constant potential (VBLP) is also formed along the dotted line shown in the figure, and the metal line 19 and the positive bit line 14 to which the VBLP voltage is applied. In the MOS C, the metal line 19 and the sub bit line 15 to which the VBLP voltage is applied are in contact with the drain / source region.

As the gate electrodes of MOS B and MOS C, a polysilicon layer 18 to which an equalization signal bleq is applied is used. Wa, Wb, and Wc shown in FIG. 3B are channels of MOS A, MOS B, and MOS C, respectively. Represents the width.

After reading the data stored in the memory cell or writing the data to the memory cell in the conventional sense amplifier configured as described above, the bit line sense amplifier must equalize the potential of the positive bit line and the sub bit line to a constant potential. Precharged. The sense amplifier has a transistor that plays this role and how fast it can do it can affect t _RP , one of the key performance of DRAM products.

In order to improve t _RP , which is the time required to precharge the positive bit line and the sub bit line, the width of the transistor needs to be widened, which results in widening the layout area of the sense amplifier. There was a limit to improving the performance.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object thereof is to provide a semiconductor memory device having improved precharge time without increasing the area by changing the layout of the sensing amplifier precharge unit used in the semiconductor memory device. .

1 is a view showing a state in which a memory cell and a sense amplifier according to the prior art arranged;

2 is a diagram illustrating a layout of a sensing amplifier precharge unit according to the prior art;

3A to 3C show a circuit diagram, a layout, and a cross-sectional view of a conventional sensing amplifier precharge unit;

4 illustrates a state in which a memory cell and a sense amplifier are arranged in accordance with the present invention;

5 shows a layout of a sense amplifier in accordance with the present invention;

6A and 6B show a circuit diagram and a layout of a sense amplifier precharge unit according to the present invention;

6C is a circuit diagram for explaining that t _RP is improved by the precharge unit according to the present invention.

* Description of the symbols for the main parts of the drawings *

20: memory cell

21: precharge part

22: amplification unit

23: newly inserted precharge unit

24: first bit line

25: first sub bit line

26: second positive bit line

27: active area

28: polysilicon layer

29: metal layer

30: newly inserted polysilicon layer

The present invention for achieving the above object, a plurality of bit line pairs; A bit line detection amplifier formed corresponding to each of the pairs of bit lines, the bit line sensing amplifier having a first precharge section for amplifying bit lines after the amplification; And a second precharge unit connected between the sub bit line of one bit line pair and the positive bit line of another bit line pair, wherein the one bit line pair and the other bit line pair are formed adjacent to each other. The first precharge unit and the second precharge unit serve to precharge and equalize the bit lines under the control of the same control signal.

In the layout of a conventional semiconductor memory device, a plurality of sensing amplifiers are arranged and separated from each other at intervals of a minimum design rule as well as the rectangular active regions. In the present invention, new polysilicon is arranged in the isolated space. This improves the precharge performance of the sense amplifier by inserting a transistor without increasing the total area. That is, the precharge transistor of the sense amplifier is formed in the empty space between the first bit line pair and the second bit line pair, so that a faster bit line precharge operation is performed.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

4 to 6C are diagrams illustrating a circuit and a layout of a sensing amplifier and a cross section thereof according to an embodiment of the present invention.

First, referring to FIG. 4, a plurality of bit line pairs bl / blb, bl1 / blb1, and bl2 / blb2 in a column direction in order to input data into or read data from the memory cell 20. And a sense amplifier comprising an amplifier 22 and a precharge unit 21 are formed in correspondence with each bit line pair, and one bit line pair (bl / blb) is formed. ) And a new precharge unit 23 is added to the space between the other bit line pairs bl1 / blb1.

The operation of the sense amplifier except for the newly inserted precharge unit 23 is the same as in the prior art. In other words. The precharge section 21, which precharges and equalizes the bit line BL and the sub bit line BLB to a predetermined potential, is composed of three transistors, and MOS A is a gate and an equalization signal bleq. The MOS B and the MOS C receive equalization signals bleq through the gates and receive the right bit line bl and the sub bit line blb. ) Precharges to a constant potential. The amplifier 22 detects and amplifies the voltage difference between the positive bit line and the sub bit line.

Unlike the related art, the precharge unit 23 newly inserted in the space between neighboring bit line pairs bl / blb and bl1 / blb1 has a sub bit line blb0 and a second bit line pair of the first bit line pair. It consists of three transistors (MOS A-1, MOS B-1, and MOS C-1) connecting the positive bit line bl1 of the MOS A-1. MOS B-1 and MOS C-1 receive the equalization signal bleq through the gate and receive the positive bit line bl and the sub bit line blb. ) Precharges to a constant potential.

In addition, the arrangement of the sense amplifier according to the present invention does not exceed '1 SA Pitch' as in the prior art.

Referring to FIG. 2, although a rectangular active region 17 is formed to be isolated from each other for each pair of adjacent bit lines, the active region 27 used in the precharge part of the sensing amplifier according to the present invention is isolated. It can be seen from FIG. 5 that the active region is not used but is used.

FIG. 5 is a diagram showing the layout of each transistor. The three MOS transistors MOS A, MOS B, and MOS C constituting the precharge unit 21 are formed in the same manner as in the prior art. That is, the MOS A for equalizing the bit line 24 and the sub bit line 25 is formed along the dotted line shown in the drawing, and the drain / source region is in contact with the bit line 24 and the bit line 25. The polysilicon layer 28 to which the equalization signal bleq is applied is used as the gate electrode.

The MOS B for precharging the positive bit line 24 and the sub bit line 25 to a constant potential (VBLP) is also formed along the dotted line shown in the figure, and the metal line 29 and the positive bit line 24 to which the VBLP voltage is applied. In the MOS C, the metal line 29 and the sub bit line 25 to which the VBLP voltage is applied are in contact with the drain / source region.

The newly inserted precharge unit 23 is formed by inserting a new polysilicon layer 30 between the sub bit line blb0 of the first bit line pair and the positive bit line bl1 of the second bit line pair. The inserted precharge unit 23 is composed of three transistors MOS A-1, MOS B-1, and MOS C-1.

MOS A-1 is formed along the dashed line shown in FIG. 6B and the newly inserted polysilicon layer 30 is used as the gate electrode, and the drain / source region is a first sub bit line 25 and a second maintenance bit. It is in contact with phosphorus 26.

MOS B-1 is formed along the dotted line shown in FIG. 6B and uses a polysilicon layer 28 as the gate electrode and the drain / source region is in contact with the first sub-bit line 25 and the metal layer 29. .

Similarly, MOS C-1 is formed along the dotted line shown in FIG. 6B and uses polysilicon layer 28 as the gate electrode and the drain / source region contacts the second positive bit line 26 and the metal layer 29. It is.

An operation of the sense amplifier precharge unit including the newly inserted precharge unit 23 will be described with reference to FIGS. 6A to 6C.

Conventionally, only a bit line pair connected to one precharge unit can be precharged, but the precharge according to the present invention can also precharge neighboring bit line pairs.

Referring to FIG. 6B, in the related art, only the first positive bit line 24 and the first sub bit line 25 may be precharged. However, in the present invention, the first sub bit line 25 and the second positive bit line 26 may be precharged. Three more transistors were formed between the first sub bit line 25 and the second positive bit line 26 to precharge each other.

Conventionally, only MOS A serves to equalize the first positive bit line 24 and the first sub bit line 25. However, in the present invention, the MOS A-1 using the newly inserted polysilicon layer 30 as a gate is In addition, even the second positive bit line 26 can be used for an equalization operation, thereby reducing the time required for the equalization operation.

In the case of MOS C which precharges the first positive bit line 24 and the first sub bit line 25, the width thereof is conventionally Wc. However, in the present invention, the first sub bit line 25 is illustrated in FIG. 6C. MOS C and MOS B-1 are connected in parallel with each other so that the width of MOS C is reduced to Wc / 2. An equivalent circuit is shown in FIG. 6C.

That is, as shown in FIGS. 6B and 6C, the source regions of the MOS C and the MOS B-1 are connected to the metal line 29 to which the VBLP voltage is applied, and the drain regions of the MOS C and the MOS B-1 are connected to the first region. Since the polysilicon 28, which is connected to the sub bit line 25 and the gate electrode is also applied with the equalization signal bleq, eventually the two transistors MOS C and MOS B-1 are connected to the first part, respectively. It is connected to the bit line 25 in parallel.

Two transistors (MOS C, MOS B-1) having a width of Wc / 2 connected in parallel to the first sub bit line 25 have one transistor having a width of Wc connected to the first sub bit line 25. It is electrically equivalent to the connection and is shown in FIG. 6C.

Even if MOS B-1 and MOS C-1 are inserted between each bit line pair as in the present invention, the voltages precharged by all the bit lines result in VBLP, so it is not necessary to precharge adjacent bit line pairs together. .

In addition, since the transistors inserted between the sense amplifiers are inserted using the space wasted due to the design rule, there is no increase in the added area, and the time required for the equalization operation can be performed as before. It can shorten the operation time of the overall sense amplifier.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in the art.

When the present invention is applied to a semiconductor memory device, it is possible to reduce the precharge time after the bit line sensing amplification without further increasing the chip area, thereby improving the operating characteristics of the memory device.

Claims (4)

Multiple bit line pairs; A bit line detection amplifier formed corresponding to each of the pairs of bit lines, the bit line sensing amplifier having a first precharge section for amplifying bit lines after the amplification; And A second precharge unit connected between the sub bit line of one bit line pair and the positive bit line of another bit line pair, wherein the one bit line pair and the other bit line pair are formed adjacent to each other; Memory device comprising a. The method of claim 1, And the first precharge unit and the second precharge unit precharge and equalize the bit lines under the control of the same control signal. The method of claim 1, The second precharge part The equalization signal is input to the gate and the drain / source is connected to the first transistor connected to the sub bit line and the positive bit line of the adjacent memory cell. An equalization signal is input to the gate and a second transistor connected to the sub bit line and the precharge voltage is connected to the drain / source. A third transistor connected to the bit line and the precharge voltage of an adjacent memory cell is input to the equalization signal through a gate and a drain / source. Memory device, characterized in that configured to include. The method of claim 2, The first and second precharge parts A memory device, characterized in that formed in the same active region.