KR100762225B1 - Cell plate voltage stable circuit of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell plate voltage stabilization circuit of a semiconductor device in which diodes are formed for each Vcp (cell plate voltage) node to prevent malfunction of an integrated circuit generated at a high speed operation. A unit cell array including two unit cells; a diode connected to a Vcp applying unit to correct a level of Vcp to a plate electrode of a capacitor of the unit cell array, each diode being formed near a cell array.

Vcp, Capacitor

Description

Cell plate voltage stabilization circuit of semiconductor device {CELL PLATE VOLTAGE STABLE CIRCUIT OF SEMICONDUCTOR DEVICE}             

1 is a configuration diagram of a typical main cell array

2 is a circuit diagram of a typical unit cell

3 is a diagram illustrating a voltage level in a state in which a write / read operation is not performed

4 is a circuit diagram showing a potential immediately before a read / write operation is performed;

5 is a circuit diagram illustrating an initial level at which a write operation is performed;

6 is a circuit diagram showing the potential of a cell having neighboring low-level data;

7 is a connection diagram for cell plate voltage stabilization according to the present invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to voltage stabilization of semiconductor devices, and more particularly to cell plate voltage stabilization circuits of semiconductor devices in which diodes are formed at each Vcp (cell plate voltage) node to prevent malfunction of integrated circuits generated at high speed. It is about.

Hereinafter, a semiconductor memory device according to the related art will be described with reference to the accompanying drawings.

1 is a configuration diagram of a general main cell array, and FIG. 2 is a circuit configuration diagram of a general unit cell.

In general, a memory cell of a semiconductor device such as a DRAM is composed of one transistor and one capacitor.

A contact connected to the bit line BL is called a bit line contact, and two cells share one contact.

If a bit line contact and a storage node contact exist with a word line WL interposed therebetween, and a high voltage in a positive direction is applied to the word line WL, the transistor is turned on so that the storage node contact and the bit line contact are closed. Are connected to each other.

Here, the storage node contact is connected to the lower electrode of the cell capacitor and the other electrode of the capacitor is connected to 1 (Vdd) / 2 so that the charge stored therein is transferred to the bit line BL.

As such, the conventional semiconductor device has a cell plate potential fixed at Vdd / 2, which is half of the external power supply Vdd.

When a high temperature burn-in test is performed on such a semiconductor device, the memory cell itself is only about a few hundred kilowatts (for example, about 300 kilowatts) no matter how high a voltage is applied from the outside.

As a result, such a small amount of oxide voltage stress requires a very long time of high temperature burn-in stress time, which causes considerable losses in terms of production cost.

When the cell plate applying line is applied as shown in FIG. 1, when the integrated circuit operates at high speed, the cell plate node writes high data to all data except a few cells during the write operation. The same phenomenon as in FIG. 1 occurs.

As several megacells of light are continuously written, the cell plate voltage rises, which in turn increases the Vcp on the low-side side.

At this time, leakage is further accelerated through the cell capacitor. As a result, leakage occurs to a level where low data recognizes high data, and eventually, low data is changed to high data, resulting in the loss of cell data.

However, the cell play voltage application method of the conventional semiconductor memory device has the following problems.

As several mega cells are continuously written, the cell plate voltage is increased. Accordingly, Vcp at the side of the low data is also increased, thereby accelerating leakage through the cell capacitor.

This results in loss of cell data, which degrades device reliability.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem of the semiconductor memory device of the related art. The purpose is to provide a cell plate voltage stabilization circuit.

According to another aspect of the present invention, there is provided a cell plate voltage stabilization circuit comprising: a unit cell array including a plurality of unit cells; And a diode connected to the Vcp applying unit to correct the level of Vcp at the plate electrode of the capacitor of the unit cell array, and form the same level of Vcp as the forward turn on voltage of the diode. This prevents the Vcp from rising above a certain voltage.

Hereinafter, a cell plate voltage stabilization circuit according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a diagram illustrating a voltage level in a state where a write / read operation is not performed, and FIG. 4 is a diagram illustrating a potential of a voltage immediately before performing a read / write operation.

FIG. 5 is a circuit diagram illustrating an initial level at which a write operation is performed, and FIG. 6 is a circuit diagram illustrating potentials of cells having neighboring low level data.

7 is a connection diagram for cell plate voltage stabilization according to the present invention.

The present invention forms a diode for each Vcp node in each mini cell array. The forward turn on voltage of the diode is set to the same level of Vcp to prevent the voltage from rising above a certain voltage.

In DRAMs, capacitors are used to store data of cells. In order to increase the capacity of this capacitor, the distance between two nodes is close.

Capacitance is inversely proportional to distance and proportional to area.

Of course, it is proportional to dielectric constant. While the technique of increasing the dielectric constant and the technique of narrowing the distance is being studied at the same time, reducing the distance increases the capacitance, but also increases the leakage current.

This has the disadvantage that the breakdown voltage is also lowered.

In DRAMs that use these capacitors, the operation is not predictable at all, so reliability must be ensured in any operation.

FIG. 3 shows a state when the DRAM does not input / output data to a cell, and FIG. 4 shows a potential when reading data before writing to data.

FIG. 6 illustrates a principle in which the voltage of Vcp increases momentarily while a write operation is performed, and FIG. 6 illustrates that a leakage current occurs in a cell having low data.

FIG. 7 is for preventing the occurrence of such leakage current, and is connected to the Vcp applying unit to correct the level of Vcp at the plate electrode of the capacitor of the unit cell array, thereby forming diodes in the vicinity of the cell array.

Here, one diode may be formed at both ends or a plurality of diodes may be used.

Here, each unit cell of the plurality of unit cell arrays includes a word line configured in one direction, a bit line passing in a direction perpendicular to the word line, a cell having a gate connected to the word line and a source connected to the bit line. A transistor and a unit capacitor having one electrode connected to the drain of the cell transistor and the other electrode connected to the ground terminal.

According to the present invention, a diode is formed at each Vcp node in each minicell array to prevent the Vcp from rising above a certain voltage by forming a forward turn on voltage of the diode at the same level of Vcp. It was given.

Such a cell plate voltage stabilization circuit of a semiconductor device according to the present invention has the following effects.

The present invention ensures the reliability of the DRAM operation through the level stabilization of the voltage of Vcp which is very important for the operation of the integrated circuit.

Claims (4)

In a semiconductor memory device, A unit cell array including a plurality of unit cells; And a diode connected to the Vcp applying unit to correct the level of Vcp at the plate electrode of the capacitor of the unit cell array. A cell plate voltage stabilization circuit of a semiconductor device which prevents Vcp from rising above a certain voltage by forming the same level of Vcp as the forward turn on voltage of the diode. 2. The cell plate voltage stabilization circuit of claim 1, wherein the diodes are formed one at each end or a plurality of diodes. The method of claim 1, wherein each unit cell is a word line configured in one direction, A bit line passing in a direction perpendicular to the word line, A cell transistor having a gate connected to the word line and a source connected to a bit line; And a unit capacitor having one electrode connected to the drain of the cell transistor and the other electrode connected to the ground terminal. delete

Images