KR100758969B1 - Block interleaver apparatus of next generation wireless lan system and method thereof - Google Patents

Abstract

The present invention relates to a block interleaver device and a method of a next generation wireless LAN system.

The interleaver of the wireless LAN system of the present invention,

A memory unit for storing the received data; A write control unit which writes data to the memory unit based on the memory writable signal generated by analyzing the modulation scheme and the number of channels of the received data; And a read controller configured to generate a memory readable signal based on the memory writable signal of the write controller and read data stored in the memory unit.

According to the present invention, the block interleaver device of the next generation wireless LAN system uses an interleaving block size corresponding to the transmission rate of the conventional wireless LAN and the next generation wireless LAN standard by using less memory and a smaller amount of control logic than the conventional interleaver. All have a satisfying effect.

Next Generation Wireless LAN, Block Interleaver, Interleaving

Description

BLOCK INTERLEAVER APPARATUS OF NEXT GENERATION WIRELESS LAN SYSTEM AND METHOD THEREOF}

1 is a block diagram showing the configuration of a transmitting end of a general next-generation wireless LAN system according to an embodiment of the present invention.

2 is a block diagram showing the configuration of a block interleaver of a next generation wireless LAN system according to an exemplary embodiment of the present invention.

3 is a flowchart illustrating an interleaving method of a block interleaver in a next generation WLAN system according to an exemplary embodiment of the present invention.

The present invention relates to a block interleaver device and a method of a next generation WLAN system, and more particularly, to a block interleaver of a next generation WLAN system implemented to be compatible with a conventional WLAN using a small number of memories and a small amount of control logic. An apparatus and a method thereof are provided.

An interleaver is a device having a function of correcting errors that can occur intensively in wireless communication by using a memory and the like, and serves to extend an error occurrence time within a range of a function of correction.

High-speed digital communication systems including wireless terminals such as next-generation wireless LANs use block interleavers among a plurality of interleavers.

The block interleaver uses a forward error correction scheme for detecting a reception bit error in order to prevent a bit error at the reception side caused by channel distortion, and is an interleaving technology required in a wireless communication channel environment.

As a technique using such a block interleaver, there is a " address counting device for reading a block interleaver " disclosed in Korean Laid-Open Patent Publication No. 2004-0050935. This conventional technique is a read address counting device for quickly processing a memory read operation by simplifying an algorithm for reading data in a memory in an interleaver composed of different patterns according to transmission signal intervals of an asynchronous terminal system and its The method is disclosed.

In general, an interleaver used in a wireless LAN is used in a time-division manner with one memory, and access to the memory is performed by a write control block, a read control block, and blocks that control the entire interleaver.

At this time, the write control block and the read control block perform memory write and read control based on the control of the entire control block. The write control block reads data from the memory while the write control block has a simple method of writing data to the memory. The input method is implemented by a complex algorithm.

Such a conventional interleaver has a problem in that it cannot perform a flexible data processing for a variable packet data rate, and there is a problem in that terminal power consumption is high when a plurality of interleaving processes are performed.

Accordingly, an object of the present invention to solve the above problems is to provide a block interleaver device that supports different sizes of interleaving based on various packet data rates using a small number of memories and a small amount of control logic.

In order to solve the above technical problem, an interleaver of a wireless LAN system according to the first aspect of the present invention,

A memory unit including a plurality of memories and storing received data; Analyzing the modulation scheme and the number of channels of the received data, generating a memory writable signal corresponding to the block size suitable for the transmission rate derived from the analyzed modulation scheme and the number of channels, and during the clock time based on the memory writable signal A write control unit for writing the received data into the memory unit; And a read controller configured to generate a memory readable signal including a read memory address based on a write memory address included in the memory writable signal of the write controller, and to read data stored in the memory unit based on a memory readable signal. It includes.

Here, the read control unit accesses to read data stored in the memory of the memory unit during a clock time based on the memory readable signal.

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According to a second aspect of the present invention, an interleaving method in an interleaver of a wireless LAN system includes: a) analyzing a modulation method of data received by a write controller of the interleaver; b) determining a data rate according to the number of channels to be used based on the analyzed modulation scheme; c) determining a data block size based on the determined transmission rate, and storing data in a memory unit of the interleaver based on the data block size; And d) reading the stored data by the read control unit of the interleaver.

Hereinafter, a block interleaver device and a method for supporting interleaving of different sizes based on various packet data rates according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a configuration of a transmitting end of a general next generation wireless LAN according to an exemplary embodiment of the present invention.

As shown in Fig. 1, the configuration of the next-generation wireless LAN transmitter according to the present invention includes the case where two channels can be used simultaneously.

The data received from the MAC layer 100 is distributed through the data distribution device 200 and is converted and encrypted by the scrambler 300 and the encoder 400.

Then, the interleaver 500 transmits the interleaving to the mapper 600 and the antennas 800 and 900 to the receiver.

2 is a block diagram showing the configuration of a block interleaver of a next generation wireless LAN system according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the block interleaver 500 according to the present invention satisfies both the conventional wireless LAN and the next-generation wireless LAN standard, and includes a write control unit 510, a read control unit 530, and a memory unit 520. do.

The write control unit 510 manages an operation related to writing a memory block by receiving transmission data, and activates and deactivates a writeable signal of the memory in accordance with the memory unit 520.

Here, the memory writable signal refers to a signal that generates a memory write address so that the received data is stored in the memory of the selected memory unit 520 and accesses the memory corresponding to the clock time.

The read controller 530 generates a memory readable signal based on the memory writable signal of the write controller 510 and reads data stored in the memory 520 so as to conform to a modem standard (transmission rate).

The memory readable signal refers to a signal for generating a memory read address to read data stored in the memory of the selected memory unit 520 and accessing a memory corresponding to a clock time.

The memory unit 520 uses 12 memories in the interleaver 500, and each memory has six addresses. In addition, the memory unit 520 stores data in the memory to interleave the interleaving block sizes corresponding to all transfer rates by receiving the memory writeable signal of the write control unit.

In this case, the memory unit 520 can access only one address at a time even though the dual port block memory having the input port and the output port exist together, so that both read and write operations are considered. I use it.

3 is a flowchart illustrating an interleaving method of a block interleaver of a next generation wireless LAN system according to an exemplary embodiment of the present invention.

As shown in FIG. 3, the write control unit 510 according to an embodiment of the present invention receives data from the encoder 400 of FIG. 1 (S100) and analyzes the received data (S102).

The write control unit 510 determines whether the received data is data of BPSK (Binary Phase Shift Keying) (hereinafter referred to as "BPSK") modulation method (S104). It is determined whether the data is used (S106).

If the data of the BPSK method using one channel, the write control unit 510 performs a write operation to the memory unit 520 for a total of 6 clocks, during which the memory unit 520 is write-accessed using a memory write-enabled signal. The data is stored in the memory (S110 and S136).

In this case, the BPSK data using one channel has a number of 48-bit coded data bits corresponding to 1-OFDM symbols.

The memory unit 520 uses only two memories out of a total of 12 memories, and the memory write order by the write control unit is memory 0 (0) / memory 1 (0) / memory 1 (1) / memory 0 (1) / The order is memory 0 (2) / memory 1 (2). Here, '/' is an operation classification signal performed at one clock, and '()' is the memory address.

If the BPSK modulation using the two channels in the step (S104) (not one channel), the write control unit 510 performs a write operation to the memory unit 520 for a total of six clocks, during which the memory can be written Data is stored in the memory of the memory unit 520 which is write-accessed using the signal (S108 and S136).

In this case, the BPSK data using the two channels has a 96-bit coded data bit number corresponding to 1-OFDM symbol.

The memory unit 520 uses only two memories out of a total of 12 memories, and the memory write order by the write controller is memory 0 (0), memory 1 (0) / memory 1 (1), and memory 0 (1) /. Memory 0 (2) / Memory 0 (2), Memory 1 (2) / Memory 1 (3), Memory 0 (3) / Memory 0 (4), Memory 1 (4) / Memory 1 (5), Memory 0 (5) is the order. Here, '/' is an operation distinguishing signal in which one clock is performed, and '()' is a memory address.

If it is not the BPSK modulation method in the step (S104), the write control unit 510 determines whether the data of the Quadrature Phase Shift Keying (QPSK) modulation method (S112), the QPSK modulation method In operation S114, it is determined whether the data using one channel is used to determine the transmission rate.

If the data is of the QPSK method using one channel, the write control unit 510 performs a write operation on the memory unit 520 for a total of 12 clocks, during which the memory unit 520 is write-accessed using a memory writable signal. The data is stored in the memory (S118, S136).

In this case, the data of the QPSK modulation method using the one channel has a number of coded data bits of 96 bits corresponding to 1-OFDM symbols.

The memory unit 520 uses only two memories out of a total of 12 memories, and the memory write order by the write control unit is memory 0 (0) / memory 1 (0) / memory 2 (0) / memory 3 (0) / Memory 1 (1) / Memory 0 (1) / Memory 3 (1) / Memory 2 (1) / Memory 0 (2) / Memory 1 (2) / Memory 2 (2) / Memory 3 (2) Become. Here, '/' is an operation distinguishing signal in which one clock is performed, and '()' is a memory address.

If the data of the QPSK method using the two channels in the step (S114) (not one channel), the write control unit 510 writes to the memory unit 520 for a total of 12 clocks, while the memory By using the writable signal, the memory of the memory unit 520 that is write-accessed is selected to store data (S116 and S136).

In this case, the QPSK data using the two channels has a number of coded data bits of 192-bit corresponding to 1-OFDM symbol.

The memory unit 520 uses only four memories out of a total of twelve memories, and the memory write order by the write controller 510 is memory 0 (0), memory 1 (0) / memory 2 (0), and memory 3 ( 0) / Memory 1 (1), Memory 0 (1) / Memory 3 (1), Memory 2 (1) / Memory 0 (2), Memory 1 (2) / Memory 2 (2), Memory 3 (2) / Memory 1 (3), Memory 0 (3) / Memory 3 (3), Memory 2 (3) / Memory 0 (4), Memory 1 (4) / Memory 2 (4), Memory 3 (4) / Memory The order is 1 (5), memory 0 (5) / memory 3 (5), and memory 2 (5). Here, '/' is an operation classification signal performed at one clock, and '()' is the memory address.

If it is not the QPSK modulation scheme in the step (S112), the write control unit 510 determines whether the data of the 16QAM (Quadrature Amplitude Modulation; "QAM") modulation scheme (S120), if the 16QAM modulation scheme, the data rate It is determined whether the data using one channel to determine (S122).

The write control unit 510 performs a write operation on the memory unit 520 for a total of 24 clocks, and selects a memory of the memory unit 520 that is write-accessed using a memory write enable signal and stores data (S126). , S136).

In this case, 16QAM data using one channel has a number of coded data bits of 192-bit corresponding to 1-OFDM symbol.

The memory 520 uses only 8 memories out of a total of 12 memories, and the memory write order by the write control unit is memory 0 (0) / memory 1 (0) / memory 2 (0) / memory 3 (0) / memory. 4 (0) / Memory 5 (0) / Memory 6 (0) / Memory 7 (0) / Memory 1 (1) / Memory 0 (1) / Memory 3 (1) / Memory 2 (1) / Memory 5 ( 1) / Memory 4 (1) / Memory 7 (1) / Memory 6 (1) / Memory 0 (2) / Memory 1 (2) / Memory 2 (2) / Memory 3 (2) / Memory 4 (2) Memory 5 (2) / Memory 6 (2) / Memory 7 (2) is in order. Here, '/' is an operation distinguishing signal in which one clock is performed, and '()' is a memory address.

If the data of 16QAM using two channels (not one channel) in the step 122, the write control unit 510 writes to the memory unit 520 for a total of 24 clocks, while the memory The memory of the memory unit 520 to be write-accessed by using the writable signal is selected to store data (S124 and S136).

At this time, the 16QAM data using the two channels has a number of coded data bits of 384-bit corresponding to 1-OFDM symbol.

The memory unit 520 uses only eight memories out of a total of 12 memories, and the memory write order by the write control unit is memory 0 (0), memory 1 (0) / memory 2 (0), and memory 3 (0) /. Memory 4 (0), Memory 5 (0) / Memory 6 (0), Memory 7 (0) / Memory 1 (1), Memory 0 (1) / Memory 3 (1), Memory 2 (1) / Memory 5 (1), Memory 4 (1) / Memory 7 (1), Memory 6 (1) / Memory 0 (2), Memory 1 (2) / Memory 2 (2), Memory 3 (2) / Memory 4 ( 2), Memory 5 (2) / Memory 6 (2), Memory 7 (2) / Memory 1 (3), Memory 0 (3) / Memory 3 (3), Memory 2 (3) / Memory 5 (3) Memory 4 (3) / Memory 7 (3), Memory 6 (3) / Memory 0 (4), Memory 1 (4) / Memory 2 (4), Memory 3 (4) / Memory 4 (4), Memory 5 (4) / Memory 6 (4), Memory 7 (4) / Memory 1 (5), Memory 0 (5) / Memory 3 (5), Memory 2 (5) / Memory 5 (5), Memory 4 ( 5) / memory 7 (5), then memory 6 (5). Here, '/' is an operation distinguishing signal in which one clock is performed, and '()' is a memory address.

If it is not the 16QAM modulation method in the step (S120) (64QAM), the write control unit 510 determines whether the data using one channel to determine the transmission rate (S130).

When one channel is used, the write controller 510 performs a write operation on the memory 520 for a total of 36 clocks, and during this time, the write controller 510 writes the memory of the memory unit 520 that is write-accessed using the memory write-enabled signal. Select and store data (S132, S136).

In this case, the 64QAM data using one channel has a number of 288-bit coded data bits corresponding to 1-OFDM symbols.

The memory unit 520 uses all 12 memories out of a total of 12 memories, and the memory write order by the write controller is memory 0 (0) / memory 1 (0) / memory 2 (0) / memory 3 (0). / Memory 4 (0) / Memory 5 (0) / Memory 6 (0) / Memory 7 (0) / Memory 8 (0) / Memory 9 (0) / Memory 10 (0) / Memory 11 (0) / Memory 1 (1) / Memory 0 (1) / Memory 3 (1) / Memory 2 (1) / Memory 5 (1) / Memory 4 (1) / Memory 7 (1) / Memory 6 (1) / Memory 9 ( 1) / Memory 8 (1) / Memory 11 (1) / Memory 10 (1) / Memory 0 (2) / Memory 1 (2) / Memory 2 (2) / Memory 3 (2) / Memory 4 (2 ) / Memory 5 (2) / Memory 6 (2) / Memory 7 (2) / Memory 8 (2) / Memory 9 (2) / Memory 10 (2) / Memory 11 (2). Here, '/' is an operation distinguishing signal in which one clock is performed, and '()' is a memory address.

If the data of 64QAM using two channels (not one channel) in the step 122, the write control unit 510 writes to the memory unit 520 for a total of 36 clocks, The memory of the memory unit 520 to be write-accessed is selected using the writable signal to store data (S134 and S136).

In this case, the 64QAM data using the two channels has a number of 576-bit coded data bits corresponding to 1-OFDM symbols.

The memory unit 520 uses all 12 memories out of a total of 12 memories, and the memory write order by the write controller 510 is memory 0 (0), memory 1 (0) / memory 2 (0), and memory 3. (0) / Memory 4 (0), Memory 5 (0) / Memory 6 (0), Memory 7 (0) / Memory 8 (0), Memory 9 (0) / Memory 10 (0), Memory 11 (0 ) / Memory 1 (1), Memory 0 (1) / Memory 3 (1), Memory 2 (1) / Memory 5 (1), Memory 4 (1) / Memory 7 (1), Memory 6 (1) / Memory 9 (1), Memory 8 (1) / Memory 11 (1), Memory 10 (1) / Memory 0 (2), Memory 1 (2) / Memory 2 (2), Memory 3 (2) / Memory 4 (2), Memory 5 (2) / Memory 6 (2), Memory 7 (2) / Memory 8 (2), Memory 9 (2) / Memory 10 (2), Memory 11 (2) / Memory 1 (3 ), Memory 0 (3) / Memory 3 (3), Memory 2 (3) / Memory 5 (3), Memory 4 (3) / Memory 7 (3), Memory 6 (3) / Memory 9 (3), Memory 8 (3) / Memory 11 (3), Memory 10 (3) / Memory 0 (4), Memory 1 (4) / Memory 2 (4), Memory 3 (4) / Memory 4 (4), Memory 5 (4) / Memory 6 (4), Memory 7 (4) / Memory 8 (4), Memory 9 (4) / Memory 10 (4), Memory 11 (4 ) / Memory 1 (5), Memory 0 (5) / Memory 3 (5), Memory 2 (5) / Memory 5 (5), Memory 4 (5) / Memory 7 (5), Memory 6 (5) / Memory 9 (5), memory 8 (5) / memory 11 (5), and memory 10 (5) are in this order. Here, '/' is an operation distinguishing signal in which one clock is performed, and '()' is a memory address.

The read control unit 530 reads data from the memory unit 510 including the stored data based on the memory write of the write control unit 510 and transmits the data to the MAPPER 600 of FIG. 2 (S138).

In the above description, a preferred embodiment of an interleaver device capable of interleaving all transmission rates of a conventional WLAN system based on IEEE802.11a and a next generation WLAN system based on IEEE802.11n has been described in detail, but the present invention is not limited thereto. Many other modifications and variations are possible.

According to the present invention, by performing block interleaving with only the maximum number of memories that need to be accessed at a time, the transmission rate of the conventional wireless LAN and the next-generation wireless LAN standard using less memory and a smaller amount of control logic than the conventional interleaver This has the effect of satisfying all of the interleaving block sizes.

In addition, since data storage and reading of the memory do not occur at the same time, there is an effect that the size of the memory can be reduced more efficiently than the conventional interleaver.
In addition, according to the configuration of the present invention, since only the memory corresponding to the block size is used, and it is not necessary to simultaneously perform the read and write operations, it is possible to reduce the size of the entire memory and to reduce the complexity on the hardware. .

Claims (8)

In the interleaver of a wireless LAN system, A memory unit including a plurality of memories and storing received data; Analyzing the modulation scheme and the number of channels of the received data, generating a memory writable signal corresponding to a block size suitable for the transmission rate derived from the analyzed modulation scheme and the number of channels, and during the clock time based on the memory writable signal A write control unit for writing the received data into the memory unit; And A read controller configured to generate a memory readable signal including a read memory address based on a write memory address included in the memory writable signal of the write controller, and to read data stored in the memory unit based on a memory readable signal; Interleaver including. delete The method of claim 1, The read control unit, And an interleaver for reading data stored in a memory of the memory unit during a clock time based on the memory readable signal. The method of claim 1, The memory unit uses 2N (N is a natural number) memories, each memory includes N addresses, and a memory writeable signal of the write controller is input to interleave the interleaving block sizes corresponding to all transfer rates. Interleaver, characterized in that for storing. The method of claim 3, The modulation scheme of the received data includes at least one modulation scheme of Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK), 16 Quadrature Amplitude Modulation (16QAM), and 64 Quadrature Amplitude Modulation (64QAM). Having an interleaver. An interleaving method in an interleaver of a wireless LAN system, a) analyzing, by the write controller of the interleaver, a modulation scheme of the received data; b) determining a transmission rate according to the number of channels to be used based on the analyzed modulation scheme; c) determining a data block size based on the determined transmission rate, and storing data in a memory unit of the interleaver based on the data block size; And d) reading the stored data by the read control unit of the interleaver Interleaving method comprising a. The method of claim 6, And the step c) stores data in the memory unit of the interleaver based on the memory writable signal generated from the write control unit of the interleaver according to the determined transfer rate. The method of claim 7, wherein In the step d), the data of the memory unit is read by the read write control signal generated by the read controller based on the memory write control signal.

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