KR100749935B1 - A silicon crystal and producing sillcon wafer thereof - Google Patents

Abstract

The present invention provides a method for producing a high-resistance silicon single crystal having excellent intrinsic gettering ability and having a specific resistance of 10000? Cm or more by the Czochralski method. To this end, in the present invention, while the initial oxygen concentration is 4.5 to 6 ppma, 1 × 10 ¹⁶ ~ 2.5 × 10 ¹⁶ / cm ³ concentration of carbon and 1 × 10 ¹³ ~ 5 × 10 ¹³ / cm ³ of nitrogen One or both are added to provide a silicon single crystal having excellent oxide withstand voltage characteristics and a resistivity of 10000 Ωcm or more.

Oxide withstand voltage, Czochralski, silicon wafer,

Description

A silicon crystal and producing sillcon wafer

1 illustrates the GOI evaluation results for a silicon wafer manufactured according to an embodiment of the present invention.

Figure 2a is a graph showing the specific resistance according to the depth from the surface of the silicon wafer manufactured in accordance with an embodiment of the present invention,

FIG. 2B is a graph showing the resistivity in the radial direction from the center of a wafer for a silicon wafer made in accordance with an embodiment of the invention,

3 is a graph showing the BMD density in the radial direction from the wafer center for a silicon wafer manufactured according to an embodiment of the present invention.

Figure 4 shows the GOI measurement results for the silicon wafer prepared according to Comparative Examples 1 to 3,

FIG. 5 is a photograph showing distribution of oxidative lamination defects (OiSF) of a silicon wafer manufactured according to Comparative Example 1. FIG.

TECHNICAL FIELD The present invention relates to a silicon single crystal and a silicon wafer, and more particularly, to a high resistance silicon single crystal and a silicon wafer having excellent oxide breakdown voltage characteristics by the Czochralski method.

In general, silicon single crystals have an intrinsic carrier density of about 1.45 × 10 ¹⁰ / cm ³ without the dopant added, and thus the resistivity of intrinsic silicon is about 2.3 × 10 ⁵ Ωcm. High value. However, the specific resistance of the silicon single crystal actually grown by the Czochralski method usually shows a low value of 100? Cm or less.

This produces and supplies oxygen-donor (thermal donor) in which interstitial oxygen atoms present in the silicon single crystal grown by the Czochralski method contribute to electrical conduction in the temperature range of about 350 to 500 ° C. Because.

The maximum gate voltage that can be tolerated while the insulating film formed on the wafer acts as a gate insulating film without dielectric breakdown is called an oxide breakdown voltage characteristic. Recently, there is an increasing demand for a high resistance silicon wafer having excellent oxide breakdown voltage characteristics suitable for power devices. .

Conventionally, a silicon wafer used as a substrate for a power device uses a wafer manufactured by using a silicon single crystal manufactured by a floating zone method in which a specific resistance value does not decrease due to an oxygen donor. The production of large diameter silicon single crystals larger than 200 mm is technically limited, and the floating zone method has a disadvantage in that the process cost is very high.

Therefore, a method of manufacturing a silicon wafer having a high resistivity while studying by the Czochralski method has been studied. As one of the results, a method of lowering the oxygen concentration between lattice when pulling up a silicon single crystal has been studied.

For example, Japanese Patent Application Laid-Open No. 8-10695 discloses a method for producing a silicon wafer having a high resistance value of 10000? Cm or more by producing a silicon single crystal having a low lattice oxygen concentration by a magnetic field applied Czochralski method (MCZ method). Japanese Patent Laid-Open No. 5-58788 discloses a method for producing a silicon single crystal having a high resistance value of 10000? Cm or more by the MCZ method using a synthetic quartz crucible.

However, low-oxygen high-resistance silicon wafers manufactured in this way gettering of metal impurities due to bulk micro defects (BMDs) produced in the bulk of the silicon wafer by the heat treatment process of the device manufacturing process due to the low initial oxygen concentration. There is a problem in that the manufacturing of highly integrated devices is not suitable for use because the effect is not obtained.

Another conventional technique is to compensate for oxygen donors by adding p-type impurities to prevent a decrease in specific resistance due to the generation of oxygen donors, resulting in an n-type high resistance silicon wafer. A manufacturing method (Japanese Patent Laid-Open No. 8-10695) has been proposed.

However, in this method, it is practically impossible to accurately predict the amount of oxygen donors generated in the silicon wafer, and it is possible to fundamentally eliminate the problem that the specific resistance value changes due to the change in the oxygen donor concentration which changes with the use environment and time. There is also a problem that this method cannot produce a p-type silicon wafer.

In another prior art WO00 / 55397, a silicon single crystal having a high lattice oxygen concentration (17 ppm or more (JEIDA), 13.6 ppm or more (NEW ASTM)) is grown, the silicon single crystal is processed into a wafer, and the oxygen precipitation heat treatment is performed on the wafer. There is a method for producing a silicon wafer in which the lattice oxygen is precipitated by controlling the amount of interstitial oxygen remaining in the wafer to be low.

However, this method has a limitation to produce an initial oxygen concentration of 13.6 ppm or more during single crystal growth for sufficient oxygen deposition, and also coarse oxygen precipitates due to excessive oxygen precipitation generated during the oxygen precipitation heat treatment process in the silicon wafer bulk. For example, due to the occurrence of oxidation-induced stacking faults (OiSF), there is a problem that the electrical properties are seriously degraded.

In another prior art, Japanese Laid-Open Patent Publication No. 2003-68744, there is a method of manufacturing a high-resistance silicon wafer by raising a low oxygen silicon single crystal and performing a rapid heat-fast cooling (RTP) heat treatment on the wafer produced therefrom.

However, since this method is accompanied by high temperature heat treatment of 1200 ° C. or higher, there is a high possibility of contamination of heavy metals during the manufacturing process, and also due to high heat treatment temperature, slip occurs during heat treatment. In addition, in order to obtain a gettering effect of sufficient heavy metal impurities, an additional heat treatment for BMD generation after rapid heating-rapid cooling (RTP) heat treatment is required, resulting in an increase in manufacturing cost due to the introduction of an additional heat treatment process.

Therefore, the present inventors have studied a method of producing a high-resistance silicon single crystal having excellent oxide resistance voltage characteristics and a specific resistance value of 10000 Ωcm or more without introducing an additional process.

As a result of this study, a method for producing a high-resistance silicon single crystal was developed by adding nitrogen concentration at a high concentration of 2 × 10 ¹⁴ particles / cm ³ or higher or carbon concentration of 3 × 10 ¹⁶ particles / cm ³ or higher.

However, silicon wafers with high nitrogen concentrations of 2 × 10 ¹⁴ / cm ³ or more to form sufficient concentrations of BMD for intrinsic gettering have a coarse oxidative defect in the normal heat treatment process during semiconductor device manufacturing. OiSF: Excessive generation of oxidation-induced stacking faults has resulted in serious degradation of device fabrication yields that cannot be used as substrates for power devices.

In addition, silicon wafers in which carbon is added at a high concentration of 3 × 10 ¹⁶ pieces / cm ³ or more can have an acceptable concentration of impurities (carbon) in a conventional semiconductor device manufacturing process (0.5 ppm or less, 2.5 × 10 ¹⁶ pieces / cm ^3). ), And accompanied by the generation of excessive oxygen precipitates during the heat treatment of the semiconductor device manufacturing process, there was a problem that causes a serious decrease in the yield of semiconductor devices.

In addition, when a heat treatment process of 1000 ° C. or more exists, the precipitated oxygen precipitate is re-dissolved into interstitial oxygen to provide an oxygen donor, thereby reducing a specific resistance value, thereby degrading the function of the finally manufactured semiconductor device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is a method of producing a high-resistance silicon single crystal having excellent intrinsic gettering ability and having a specific resistance of 10000 Ωcm or more by the Czochralski method. To provide.

Another object of the present invention is to provide a silicon wafer having a uniform in-plane resistivity value and excellent oxide film breakdown voltage characteristics as a substrate for power devices.

The silicon single crystal of the present invention for achieving the above technical problem is grown by the Czochralski method, the initial oxygen concentration is 4.5 ~ 6, 1 × 10 ¹⁶ ~ 2.5 × 10 ¹⁶ / cm ³ Any one or both of the carbon of the concentration and nitrogen of 1 × 10 ¹³ ~ 5 × 10 ¹³ / cm ³ concentration is added, characterized in that the resistivity (resistivity) is greater than or equal to 10000 Ωcm.

Silicon single crystal is grown from a liquid phase into a solid single crystal ingot, and the V / G value obtained by dividing the growth rate (V) by the cooling driving force (G) of the solid-liquid interface single crystal (OiSF ring) is an oxidation-induced stacking fault ring. It is preferable to pull under 1.3 times or more than the V / G value (0.2 mm ² / minK) which generates).

Further, the silicon single crystal is preferably grown under the condition that the distribution of the cooling driving force G of the single crystal at the solid-liquid interface is smaller than 10% (relative to the G value at the center) in the radial direction from the single crystal center.

In a silicon single crystal, an oxidation-induced stacking fault ring (OiSF ring) is preferably located at the edge of the single crystal.

For example, the oxidized lamination defect ring is preferably located within 5 mm from the edge of the silicon single crystal having a diameter of 300 mm.

In addition, the silicon wafer manufactured by processing the silicon single crystal preferably has a bulk micro defect (BMD) density of 1 × 10 ⁵ / cm ² or more.
Then, a high-resistance silicon wafer sliced from the silicon single crystal as described above is provided.

Hereinafter, the present invention will be described in detail.

Recently, the requirements for silicon wafers that are used as substrates for power devices that operate stably without breakdown even under high gate voltages are becoming increasingly stringent.

In order to be used as a substrate of a semiconductor device, the oxide breakdown voltage property must be excellent, wherein the oxide breakdown voltage property of the wafer can be expressed as the strength of the gate voltage that can withstand the oxide film formed on the wafer without performing dielectric breakdown. Can be.

The oxide breakdown voltage characteristics of the wafer can be confirmed by gate oxide integrity (GOI) evaluation, and the failure rate of the semiconductor device can be indirectly confirmed through the GOI evaluation.

Therefore, the typical characteristics required for the wafer for power devices include the excellent oxide film breakdown voltage characteristics of the wafer described above, and have a high specific resistance value, and have a BMD at an appropriate density in order to increase the gettering effect of heavy metal impurities. Etc.

In order to manufacture a silicon wafer for a power device satisfying the above-mentioned characteristics, in the present invention, a silicon single crystal in which nitrogen and carbon are added at respective appropriate concentrations and a low initial oxygen concentration is produced, from which a resistivity value is 10000? Cm The above-mentioned silicon wafer is manufactured.

In other words, while the initial oxygen concentration of 4.5 ~ 6 ppma the ^{invention, 1 × 10 16 ~ 2.5 ×} 10 16 threads / cm of carbon and 1 × 10 ^three levels ¹³ ~ 5 × 10 ¹³ threads / cm ³ which of the nitrogen concentration One or both are added to provide a silicon single crystal whose resistivity is greater than or equal to 10000 Ωcm.

The silicon single crystal described above is grown into a silicon single crystal ingot by the Czochralski method, and the silicon single crystal ingot thus produced is processed into a wafer.

The initial oxygen concentration should be at least higher than this, considering that the oxygen solubility in silicon at 1000 ° C. is approximately 4 ppma. If the initial oxygen concentration is lower than 4 ppm, sufficient BMD is not formed to act as a gettering site of the metal impurity even after the oxygen precipitation heat treatment.

More preferably, an oxygen concentration of at least 4.5 ppma or more is required to ensure that at least delta [Oi] (initial [Oi]-final [Oi]) is 0.5 ppma or more.

On the other hand, if the initial oxygen concentration exceeds 6 ppm, in the case of a heat treatment process of 1000 ° C. or higher in the semiconductor device process, the precipitated oxygen precipitate is re-dissolved into interstitial oxygen to provide an oxygen donor, thereby reducing the resistivity value, thus finally manufacturing The function of the device can be reduced. That is, at an initial oxygen concentration of 6 ppm or less, a high-resistance silicon wafer can be provided regardless of the presence or absence of a heat treatment process of 1000 DEG C or higher in the device process.

Therefore, the initial oxygen concentration should be controlled to 4.5 ~ 6ppma to have high resistance and independent gettering capability regardless of the heat treatment process.

The optimum nitrogen concentration proposed in the present invention, 1 × 10 ¹³ to 5 × 10 ¹³ pcs / cm ³ , satisfies the condition that oxygen precipitation can be promoted by addition of nitrogen without generating coarse oxygen stacking defect (OiSF). It is determined by the concentration, and the optimum carbon concentration of 1 × 10 ¹⁶ to 2.5 × 10 ¹⁶ pieces / cm ³ is a range of carbon concentrations allowed in the semiconductor device manufacturing process while achieving the effect of promoting the deposition of oxygen by carbon addition. It was decided in consideration of.

This makes it possible to manufacture a high-resistance silicon wafer with high gettering capability through BMD precipitation heat treatment in a conventional semiconductor device manufacturing process, that is, without specially performing a special heat treatment to a subsequent process.

The present inventors have studied the cause of the non-uniformity of the final oxygen concentration and the specific resistance value in the radial direction of the wafer after the oxygen precipitation heat treatment in the silicon-added silicon wafer. It was found that the entrained void type defects depend on the concentration of void type defects remaining after precipitation into voids, which are three-dimensional defects, in the temperature range of void defect precipitation during the cooling of the crystal. It was found that the concentration is relatively high at the silicon wafer edge.

Therefore, in the present invention, the silicon single crystal ingot grown by the Czochralski method has a V / G value obtained by dividing the growth rate (V) by the cooling driving force (G) of the solid-liquid interface single crystal (OiSF ring: oxidation-induced stacking). It grows under the condition of 1.3 times more than the V / G value (0.2 mm ² / minK) that causes the fault ring, that is, V / G is greater than or equal to 0.26mm ² / minK.

This allows the silicon single crystal to be grown such that the OiSF ring is located at the edge of the silicon single crystal, which causes nonuniformity of the resistivity value in the radial direction of the wafer.

For example, in a silicon single crystal having a diameter of 300 mm, the silicon single crystal may be grown such that the oxidized lamination ring is located within 5 mm from the edge of the silicon single crystal.

In addition, the silicon wafer manufactured by processing the silicon single crystal thus prepared has a BMD density greater than 1 × 10 ⁶ holes / cm ² .

Hereinafter, the present invention will be described in more detail with reference to Examples.

Example

In the embodiment, the silicon single crystal ingot was grown by the Czochralski method, and the initial oxygen concentration was grown to 5 ppma, and the carbon was 2 × 10 ¹⁶ pieces / cm ³ and the nitrogen was 4 × 10 ¹³ pieces. Silicon single crystal ingots were grown by adding / cm ³ concentration. This silicon single crystal ingot was sliced to produce a high resistance silicon wafer.

GOI evaluation results for the high resistance silicon wafer manufactured according to the example are shown in FIG. 1. In the GOI evaluation, the strength of the breakdown voltage (BV) at which the wafer can no longer tolerate and breaks was measured at 218 points per wafer. According to the measured BV intensity, defects are divided into A, B, and C modes, and are shown in different colors for each mode. From the GOI evaluation result shown in FIG. 1, a silicon wafer manufactured according to an embodiment of the present invention is used in most areas. The BV was greater than 13 MV / cm and only showed C mode and C + mode in some areas, no serious defects such as A mode or B mode were seen. From this, it was confirmed that the silicon wafer manufactured according to the example exhibits excellent GOI characteristics at a level that can be used as a substrate for power devices.

The excellent GOI evaluation result of the silicon wafer according to the embodiment can be seen better than the results of Comparative Examples 1 to 3 (FIG. 4) described later.

On the other hand, the resistivity of the silicon wafer manufactured according to the embodiment was measured and the results are shown in Figures 2a and 2b. FIG. 2A is a graph showing the resistivity versus depth from the wafer surface, and FIG. 2B is a graph showing the resistivity in the radial direction from the center of the wafer.

As shown in FIGS. 2A and 2B, the silicon wafer manufactured according to the embodiment showed a uniform resistivity value greater than 10000 Ωcm in the depth direction from the surface, and larger than 10000 Ωcm in the radial direction from the center of the wafer. Uniform resistivity values are shown.

In addition, the BMD density was measured for the silicon wafers prepared according to the examples, and the results are shown in FIG. 3. 3 is a graph illustrating the BMD density from the wafer center in the radial direction.

As shown in FIG. 3, the silicon wafer manufactured according to the embodiment showed a uniform distribution with a BMD density higher than 1 × 10 ⁶ / cm ^{2 in the} radial direction from the center of the wafer.

Meanwhile, in Comparative Examples 1 to 3, nitrogen was added at a concentration of 5.1 × 10 ¹³ pieces / cm ³ , 7.5 × 10 ¹³ pieces / cm ³ , and 1 × 10 ¹⁴ pieces / cm ³ , respectively. A silicon wafer was prepared under the same conditions. GOI measurement results for the silicon wafers prepared according to Comparative Examples 1 to 3 are shown in order from the left in FIG.

As shown in FIG. 4, serious defects in either A mode or B mode were found in the silicon wafers manufactured according to Comparative Examples 1 to 3.

In addition, a photograph of a silicon wafer manufactured according to Comparative Example 1 is shown in FIG. 5, and since the silicon wafer manufactured according to Comparative Example 1 is seriously degraded in the oxide withstand voltage characteristics due to coarse oxygen precipitate generation from these drawings. It was found that it could not be used as a substrate for power devices.

As described above, according to the present invention, it is excellent in oxide pressure resistance characteristics, has an appropriate BMD density, has excellent intrinsic gettering ability, and has a high resistance silicon single crystal having a specific resistance of 10000 Ωcm or more. It provides the method of manufacturing by.

Claims (12)

Silicon single crystals were grown by the Czochralski method and have an initial oxygen concentration of 4.5 to 6 ppma, carbon of 1 × 10 ¹⁶ to 2.5 × 10 ¹⁶ particles / cm ^3, and 1 × 10 ¹³ to 5 × 10 ¹³ pieces / cm ³ Nitrogen is added and the silicon single crystal has a resistivity greater than or equal to 10000 Ωcm. delete The method of claim 1, The silicon single crystal is grown from a liquid phase into a solid single crystal ingot, and V / G, which is a value obtained by dividing the growth rate (V) by the cooling driving force (G) of the single crystal at the interface between the solid phase and the liquid phase, is oxidatively stacked (OiSF: oxidation- Silicon single crystal grown 1.3 times larger than or equal to the V / G value causing the induced stacking fault delete The method of claim 1, And an oxidation-induced stacking fault ring (OiSF ring) in the silicon single crystal. The method of claim 5, Wherein said oxidized lamination ring is located within 10% of a radius of said silicon single crystal from an outer circumference of said silicon single crystal. The method of claim 3, wherein Silicon single crystal with a BMD (bulk micro defect) density higher than 1 × 10 ⁶ pieces / cm ² . The method of claim 6, Silicon single crystal with a BMD (bulk micro defect) density higher than 1 × 10 ⁶ pieces / cm ² . delete It was grown by the Czochralski method, and has an initial oxygen concentration of 4.5 to 6 ppma, 1 × 10 ¹⁶ to 2.5 × 10 ¹⁶ carbons / cm ^3, and 1 × 10 ¹³ to 5 × 10 ¹³ carbons. A silicon wafer made from a silicon single crystal added to a nitrogen / cm ³ concentration and having a resistivity greater than or equal to 10000 Ωcm. The method of claim 10, An oxide-induced stacking fault ring (OiSF ring) is located within 10% of the radius of the silicon wafer from the outer periphery of the silicon wafer. The method of claim 10, Silicon wafers having a bulk micro defect (BMD) density of greater than 1 × 10 ⁶ pieces / cm ² .

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