KR100742268B1 - Reference clock-less clock and data recovery circuit with 4x oversampling - Google Patents

Abstract

The present invention provides a quadruple speed oversampling clock / data recovery circuit having a wide frequency tracking range and no reference clock operable without a reference clock.

The present invention oversamples the input data four times by a predetermined number of clocks to obtain the same number of sampling data as the number of clocks, and uses the sampled data to determine the first, second phase up, A phase detector for outputting down information; A frequency detector for outputting frequency up and down information by determining a change in the transition position of the data in the input data by using the first phase up and down information and the second phase up information output from the phase detector; A VCO for providing a clock to the phase detector; A charge pump and a loop filter outputting a control signal of the VCO from phase and frequency information output from the phase detector and the frequency detector; And data restoring means for outputting predetermined sampling data among the data sampled by the phase detection unit as restoration data based on a predetermined clock provided from the VCO.

Clock / Data Recovery Circuit, 4x Oversampling, Reference Clock, VCO, Phase, Frequency Detector

Description

4x oversampling clock / data recovery circuit without reference clock {REFERENCE CLOCK-LESS CLOCK AND DATA RECOVERY CIRCUIT WITH 4X OVERSAMPLING}

1 illustrates a 4x oversampling clock / data recovery circuit without a reference clock in accordance with the present invention.

FIG. 2 is a detailed configuration diagram of the phase detector of FIG. 1. FIG.

3 is a detailed configuration diagram of the frequency detector of FIG.

FIG. 4 is a diagram illustrating an output clock for sampling input data in FIG. 1. FIG.

5A to 5G are diagrams illustrating output signals of respective parts of a clock / data recovery circuit according to the present invention.

6 is a simulation configuration diagram for verifying a clock / data recovery circuit according to the present invention.

7a and 7b is a VCO control voltage waveform according to the tracking range change as an experimental example of the present invention.

8A-8C illustrate recovered clocks, random input data, and recovered data in accordance with the present invention.

<Explanation of symbols for the main parts of the drawings>

100: phase detector 111-118: first-eighth sampler

121-128: first-eighth XOR gate 131-134: first-fourth multiplexer

200: frequency detector 211,212: inverted gate

213: OR gate 214-216: 1st-3rd D flip flop

300: charge pump 400: loop filter

500: VCO 600: Multiplexer

The present invention relates to a clock / data recovery circuit used in a data communication system, and more particularly to a quadruple speed oversampling clock / data recovery circuit having a wide frequency tracking range and without a reference clock operable without a reference clock.

Recently used information and data communication systems, for example, a gigabit optical communication transceiver or Ethernet system is required not only high speed of operation but also the ability to process, store and transmit large amounts of data.

In the transmission and reception of data between such systems, a clock / data recovery circuit is used for clock synchronization and accurate data transmission and reception.

In particular, in order to satisfy the SONET jitter specification in implementing an optical transceiver such as Gigabit Ethernet, a voltage controlled oscillator (VCO) used in a clock / data recovery circuit has a frequency exactly matched to input data at a receiver. Must be tailored.

Thus, clock / data recovery circuits typically operating at 10Gb / s require an external reference clock, such as a voltage-controlled crystal oscillator, and the operating range is limited to one data rate.

However, in the case of Wavelength Division Multiplexing (WDM) optical communication using Forward Error Correction (FEC), transmission / reception data rates range from 10.8 Gb / s to 9.95 Gb / s depending on the presence or absence of an FEC block in the data packet.

Therefore, in order to apply to WDM, the clock / data recovery circuit must be able to support any data rate between 9.9Gb / s and 10.8Gb / s according to the FEC. The reduced number of components, the shorter the circuit, the lower the cost, and a clock / data recovery circuit that can operate without an external reference clock is required.

The present invention has been made in view of the above, and an object of the present invention is to apply a phase detector using a 4x oversampling scheme and a frequency detector using only an output signal from the phase detector, thereby operating without a reference clock while having a wide frequency tracking range. It provides a 4x oversampling clock / data recovery circuit with no possible reference clock.

In order to achieve the object of the present invention, the 4x oversampling clock / data recovery circuit without a reference clock according to the present invention is configured to oversample the input data 4x by a predetermined number of clocks, thereby sampling the same number as the number of clocks. A plurality of samplers for outputting data, a plurality of exclusive OR circuits for determining a phase position of the input data and an output clock phase using the sampled data, and a first first output from the output of the exclusive OR circuits; Phase detection means including a plurality of multiplexers for outputting second phase up information and first and second phase down information; A plurality of D flip-flops outputting frequency up and down information by determining a change in the transition position of the input data on the basis of the output clock by using the first phase up and down information and the second phase up information output from the phase detection means. Frequency detection means comprising a; A VCO for making a clock based on the phase information in the phase detecting means; Charge pump means for inputting phase information and frequency information output from the phase detection means and the frequency detection means and outputting a signal for controlling the VCO which is a corresponding current value; Loop filter means for converting a signal for controlling the VCO from the charge pump means into a voltage value and outputting the voltage to the VCO; And data restoring means for outputting predetermined sampling data among data sampled by the phase detecting means as restoration data based on a predetermined clock provided from the VCO.

The phase detecting means may include: first to eighth samplers outputting sampled data from the input data; A first to eighth exclusive ora gate for detecting the input data transition position using data sampled by the first to eighth samplers; And a first-fourth multiplexer configured to output the first, second phase-up and phase-down information from an output of the first-eighth exclusive ora gate.

The frequency detecting means includes: a first D flip-flop that outputs the frequency up information from the first phase up and down information; Second and third D flip-flops that output the frequency down information from the inverted signal of the first phase up and down information and the first phase down information; And an oar gate that provides the clear signal to the first to third D flip-flops by oaring the first and second phase up information.

The charge pumping means may include: a first charge pump configured to input first phase up and phase down information output from the phase detection means to output a corresponding current value; A second charge pump configured to input second phase up and phase down information output from the phase detection means and output a corresponding current value; And a third charge pump configured to input frequency up and down information output from the frequency detection means and output a corresponding current value.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the following examples are merely to illustrate the invention is not limited to the contents of the present invention.

1 is a block diagram of a 4x oversampling clock / data recovery circuit without a reference clock according to the present invention. The structure of the clock / data recovery circuit of the present invention basically has a phase-locked loop (PLL) structure. It is constructed based on.

As shown, the present invention is largely composed of six parts: the phase detector 100, the frequency detector 200, the charge pump 300, the loop filter 400, the VCO 500, and the multiplexer 600.

The phase detector 100 oversamples two consecutive input data into eight clocks (clk0-clk3, clk0b-clk3b) at four times, and eight sampling data (Dout0-Dout7) per clock cycle. The sampled data Dout0-Dout7 are used to determine the transition position that changes from 0 to 1 or 1 to 0 in the input data. Phase up, down information (Pup2, Pdn2) and second phase up, down for phase down)

It is configured to output the information Pup1, Pdn1, the detailed configuration of which is as shown in FIG.

As illustrated in FIG. 2, the phase detector 100 may include first through eighth samplers for sampling eight pieces of data Dout0 through Dout7 from two consecutive input data received as differential signals. 111-118) and a first-eighth wing for detecting a transition position of the input data using the data Dout0-Dout7 sampled by the first-eighth samplers 111-118. Eight phase difference signals I and II for phase-up and phase-down outputted through the school ora gate (hereinafter referred to as XOR) gates 121-128 and the first-eighth XOR gates 121-128. ..., i) consisting of first-fourth multiplexers 131-134 for outputting first and second phase-up and phase-down information Pup2, Pdn2, Pup1, Pdn1.

The frequency detector 200 has a rotational frequency detector structure that operates at a 1/2 clock, which is half the data rate, and includes a first phase up and output from the phase detector 100. Frequency up and frequency are determined by using the down information Pup2 and Pdn2 and the second phase up information Pup1 to determine how the position of transition of the data is changed in the two consecutive input data. It is configured to output frequency up and down information Fup and Fdn of frequency down, the detailed configuration of which is as shown in FIG.

As shown in FIG. 3, the frequency detector 200 includes frequency up and down information Fup and Fdn with only the transition components of the first phase up and down information Pup2 and Pdn2 output from the phase detector 100. It is simply implemented using the first-third D flip-flop (214-216) having a reset function to output.

In addition, when the first and second phase up information Pup1 and Pup2 are output from the phase detector 100, the frequency detector 200 reports that the frequency difference between the clock and the input data is in a locked state. The output of the OR gate 213 for ORing the first and second phase up information Pup2 and Pup1 to stop the operation without abnormal operation is performed by the first to third D flip-flops 214-216. It is configured to be input to the clear stage (CLR) of the). Reference numerals 211 and 212 denote inversion gates for inverting the first phase up and down information Pup2 and Pdn2 output from the phase detector 100.

Also, the charge pump 300 may include first and second phase up and down information Pup2, Pdn2, Pup1, and Pdn1 and frequency up and down information output from the phase detector 100 and the frequency detector 200. The first to third charge pumps 310 to 330 are configured to output the control signal of the VCO 500 from Fup and Fdn.

The loop filter 400 includes a resistor R11 and a capacitor C11 connected in parallel to the first and second charge pumps 310 and 320, respectively, and a capacitor C12 connected in series with the resistor R11. An output line of the third charge pump 330 is connected between the resistor R11 and the capacitor C12 to enable faster frequency locking.

The VCO 500 is composed of four conventional delay cells and outputs eight clocks (clk0-clk3, clk0b-clk3b) to be input to the phase detector 100 according to a control voltage input through the loop filter 400. The multiplexer 600 receives a clock clk2 from the VCO 500 and first and fifth sampling data Dout0 and Dout4 of eight data Dout0-Dout7 sampled by the phase detector 100. ) Is output as the restored data.

The operation of the present invention configured as described above is as follows.

The phase detector 100 basically uses a 4x over-sampling scheme, and inputs the input data to eight clocks (clk0-clk3 and clk0b-clk3b) through the first through eighth samplers 111-118. 8 samples (Dout0-Dout7) are output for each cycle of the clock. Here, the clocks (clk0-clk3) and the clock (clk0b-clk3b) is a clock of the opposite phase to each other, the relationship is as shown in FIG.

The first to eighth XOR gates 121 to 128 use eight data Dout0-Dout7 sampled by the first to eighth samplers 111 to 118, and 0 to 1 in input data. Eight phase difference signals (I, II, ..., Ⅷ) are output by detecting a transition position that changes from or changes from 1 to 0.

The first and fifth XOR gates 121 and 125, the outputs of the second and eighth XOR gates 124 and 128, and the second and sixth XOR gates 122 and 126. ) And the outputs of the third and seventh XOR gates 123 and 127 are multiplexed according to the clocks clk0-clk3 in the first to fourth multiplexers 131 to 134, respectively, to thereby first and second phase up and down information. It is output as (Pup2, Pdn2, Pup1, Pdn1).

The frequency detector 200 receives first phase up and down information and second phase up information Pup2, Pdn2, and Pup1 from the phase detector 100, and receives frequency up and down information Fup and Fdn therefrom. Is output to the charge pump 300.

That is, the first phase up and down information Pup2 and Pdn2 output from the phase detector 100 are inverted at the inversion gates 211 and 212, respectively, and then the clock stage clk and the data of the second D flip-flop 215 are used. It is input to the input terminal D. In addition, the first phase up and down information Pup2 and Pdn2 are input to the data input terminal D and the clock terminal clk of the first D flip-flop 214, and the second D flip-flop 215 An output is input to the data input terminal D of the third D flip-flop 216, and the first phase down information Pdn2 is input to the clock terminal clk of the third D flip-flop 216 to output the first, Frequency up and down information Fup and Fdn may be output from the third D flip-flops 214 and 216.

In this case, the value of the first and second phase up information Pup1 and Pup2 from the phase detector 100 oraed at the ora gate 213 is determined by the first to third D flip-flops 214 to 216. The first and second phase up information Pup1 and Pup2 are respectively input to the clear stage CLR. When the first and second phase up information Pup1 and Pup2 are output, the frequency detector 200 determines that the frequency difference between the clock and the input data is locked. This is to stop the operation of the frequency detector 200 so that it no longer operates.

The first and second phase up and down information Pup2, Pdn2, Pup1 and Pdn1 output from the phase detector 100 and the frequency up and down information Fup and Fdn output from the frequency detector 200 are charged. Input to the pump 300 is output as a signal for controlling the VCO (500).

The first charge pump 310 of the charge pump 300 receives the second phase up and down information Pup1 and Pdn1 from the phase detector 100, and the second charge pump 320 receives the phase detector 100 from the phase detector 100. The first phase up and down information Pup2 and Pdn2 of the third charge pump 330 change the frequency up and down information Fup and Fdn from the frequency detector 200 by different amounts of current, respectively, to filter the loop. The output of the voltage to control the VCO (500) through (400). In this case, the third charge pump 330 is directly connected to the capacitor C11 of the loop filter 400 to enable faster frequency locking.

The VCO 500 outputs eight clocks (clk0-clk3, clk0b-clk3b) by the control voltage from the loop filter 400. These eight clocks (clk0-clk3, clk0b-clk3b) are input to the phase detector 100 and used for sampling of input data.

Meanwhile, the multiplexer 600 receives the clock clk2 from the VCO 500 and the first and fifth sampling data Dout0 and Dout4 of the eight data Dout0-Dout7 sampled by the phase detector 100. ) Will be output as restored data.

5A to 5G show output signals of respective parts of the clock / data recovery circuit of the present invention. FIG. 5A shows the output of the loop filter 400 as the VCO control voltage, and FIG. 5B shows the second phase up information Pup1. 5C shows the second phase down information Pdn1, FIG. 5D shows the first phase up information Pup2, FIG. 5E shows the first phase down information Pdn2, and FIG. 5F shows the frequency up information Fup. 5G shows frequency down information Fdn, respectively.

6 shows a simulation configuration diagram for verifying the present invention, and is configured to use the data generated through the random data generator 700 as a circuit input of the present invention.

FIG. 7 illustrates a control voltage waveform of the VCO 500 according to a change in the tracking range, and shows a range of tracking when the data rate is increased based on 3.125 Gbps. FIG. 7A shows that tracking is possible up to data in the 3.5 Gbps range (approximately 12%), and FIG. 7B shows that tracking is possible up to 2.74 Gbps (lower 12%) data.

FIG. 8A shows the recovered clock, FIG. 8B shows random input data by the circuit configured as 6, and FIG. 8C shows recovered data according to the present invention.

7 and 8, it can be seen that the clock / data recovery circuit of the present invention recovers data and clocks in a tracking range of about 24% based on 3.125 Gbps without input of a reference clock.

  As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art various modifications of the present invention without departing from the spirit and scope of the invention described in the claims below Or it may be modified.

As described above, the present invention can recover the clock and data with purely input data only in a wide tracking range of about 24% without a reference clock, which is applicable to the field of transceivers for Ethernet or optical communication, and to existing circuits. Compared with the reduced circuit components and implementation size, it can be used to implement optical receivers with less power consumption.

Claims (8)

A plurality of samplers outputting the same number of sampling data as the number of clocks by oversampling the input data by a predetermined number of clocks four times; and using the sampled data, phase positions of the input data and the output clock phases. Phase detection means including a plurality of exclusive oral circuits for determining and a plurality of multiplexers for outputting first and second phase up information and first and second phase down information from an output of the exclusive oral circuit; A plurality of D flip-flops outputting frequency up and down information by determining a change in the transition position of the input data on the basis of the output clock by using the first phase up and down information and the second phase up information output from the phase detection means. Frequency detection means comprising a; A VCO for making a clock based on the phase information in the phase detecting means; Charge pump means for inputting phase information and frequency information output from the phase detection means and the frequency detection means and outputting a signal for controlling the VCO which is a corresponding current value; Loop filter means for converting a signal for controlling the VCO from the charge pump means into a voltage value and outputting the voltage to the VCO; And Data restoring means for outputting predetermined sampling data among data sampled by said phase detecting means as restoring data based on a predetermined clock provided from said VCO; 4x oversampling clock / data recovery circuit without a reference clock. 4. The quadruple speed oversampling clock / data recovery circuit of claim 1 wherein the input data is two consecutive differential signals. The method of claim 2, wherein the phase detection means A first to eighth sampler configured to output data sampled from the input data; A first to eighth exclusive ora gate for detecting the input data transition position using data sampled by the first to eighth samplers; And A first to fourth multiplexer configured to output the first and second phase up and phase down informations from an output of the first to eighth exclusive oar gates; 4x oversampling clock / data recovery circuit without a reference clock. 4. The method of claim 3, wherein the first multiplexer receives the outputs of the first and fifth exclusive or gates as inputs and outputs first phase up information for phase up, and the second multiplexer outputs the first phase up information for the phase up. Receives an output of an eighth exclusive oar gate as an input and outputs first phase down information for phase down, and the third multiplexer receives an output of the second and sixth exclusive oar gates as an input. Outputs second phase up information on phase up, and the fourth multiplexer receives the outputs of the third and seventh exclusive oar gates as inputs and outputs second phase down information on phase down 4x oversampling clock / data recovery circuit without reference clock. The method of claim 1, wherein the frequency detecting means A first D flip-flop that outputs the frequency up information from the first phase up and down information; Second and third D flip-flops that output the frequency down information from the inverted signal of the first phase up and down information and the first phase down information; And An oar gate for ORing the first and second phase-up information to provide a clear signal to the first to third D flip-flops; 4x oversampling clock / data recovery circuit without a reference clock. The method of claim 1, wherein the charge pump means A first charge pump configured to input first phase up and phase down information output from the phase detection means to output a corresponding current value; A second charge pump configured to input second phase up and phase down information output from the phase detection means and output a corresponding current value; And A third charge pump configured to input frequency up and down information output from the frequency detecting unit to output a corresponding current value; 4x oversampling clock / data recovery circuit without a reference clock. The method of claim 6, wherein the loop filter A resistor and a first capacitor connected in parallel to the first and second charge pumps, respectively; And a second capacitor connected in series with the resistor, wherein the output line of the third charge pump is connected between the resistor and the second capacitor to enable faster frequency locking. Oversampling clock / data recovery circuit. The method of claim 1, wherein the data recovery means 4x oversampling clock / data recovery circuit without a reference clock, characterized by a multiplexer.

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