KR100732842B1 - Organic Light Emitting Display - Google Patents

Abstract

The present invention relates to a light emitting display device capable of reducing the number of output lines of a data driver.

The light emitting display device of the present invention sequentially supplies the first scan signal to the first scan lines during the first period and the second period of the horizontal period, and sequentially supplies the second scan signal to the second scan lines during the first period. And a scan driver for sequentially supplying light emission control signals to light emission control lines overlapping the first and second periods; A data driver for sequentially supplying a plurality of data signals to respective output lines during the first period; Demultiplexers provided for each output line and having a plurality of switching elements connected between the output line and each of the plurality of data lines to supply the plurality of data signals supplied to the output lines to the plurality of data lines; ; A demultiplexer controller configured to supply a control signal to sequentially turn on the plurality of switching devices during the first period; And a pixel configured to receive the data signal during the first period, compensate for the threshold voltage of the driving transistor during the second period, and generate light having a luminance corresponding to the data signal after the second period.

Description

Light Emitting Display {Organic Light Emitting Display}

1 illustrates a conventional light emitting display device.

2 is a diagram illustrating a light emitting display device according to an exemplary embodiment of the present invention.

FIG. 3 is a diagram illustrating the demultiplexer illustrated in FIG. 2.

4A and 4B are waveform diagrams illustrating a method of driving the light emitting display device illustrated in FIG. 2.

FIG. 5 is a circuit diagram illustrating in detail a pixel illustrated in FIG. 2.

FIG. 6 is a diagram illustrating a connection between the pixel and the demultiplexer illustrated in FIG. 5.

<Explanation of symbols for the main parts of the drawings>

10,110: scan driver 20,120: data driver

30,130: pixel portion 40,140: pixel

50,150: timing controller 142: pixel circuit

160: demultiplexer block portion 162: demultiplexer

170: demultiplexer control unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting display device, and more particularly, to a light emitting display device capable of reducing the number of output lines of a data driver.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. The flat panel display includes a liquid crystal display, a field emission display, a plasma display panel, and an organic light emitting display.

Among the flat panel display devices, the light emitting display device displays an image using an organic light emitting diode that generates light by recombination of electrons and holes. Such a light emitting display device has an advantage in that it has a fast response speed and is driven with low power consumption.

1 is a view illustrating a conventional general light emitting display device.

Referring to FIG. 1, a conventional light emitting display device includes a pixel portion 30 including pixels 40 formed in an intersection area of scan lines S1 to Sn and data lines D1 to Dm, and scan lines A timing controller for controlling the scan driver 10 for driving S1 to Sn, the data driver 20 for driving the data lines D1 to Dm, and the scan driver 10 and the data driver 20. 50 is provided.

The scan driver 10 generates a scan signal in response to the scan drive control signals SCS from the timing controller 50, and sequentially supplies the generated scan signal to the scan lines S1 to Sn. In addition, the scan driver 10 generates a light emission control signal in response to the scan drive control signals SCS, and sequentially supplies the generated light emission control signals to the light emission control lines E1 to En.

The data driver 20 generates data signals in response to the data driving control signals DCS from the timing controller 50, and supplies the generated data signals to the data lines D1 to Dm. At this time, the data driver 20 supplies the data signal to the data lines D1 to Dm in synchronization with the scan signal.

The timing controller 50 generates the data drive control signal DCS and the scan drive control signals SCS in response to the synchronization signals supplied from the outside. The data driving control signals DCS generated by the timing controller 50 are supplied to the data driver 20, and the scan driving control signals SCS are supplied to the scan driver 10. The timing controller 50 rearranges the data Data supplied from the outside and supplies the data to the data driver 20.

The pixel unit 30 receives the first power source ELVDD and the second power source ELVSS from the outside. Here, the first power source ELVDD and the second power source ELVSS are supplied to the respective pixels 40. Each of the pixels 40 supplied with the first power source ELVDD and the second power source ELVSS generates light corresponding to the data signal supplied thereto. In addition, the emission time of the pixels 40 is controlled in response to the emission control signal.

In the conventional light emitting display device driven as described above, each of the pixels 40 is positioned at an intersection of the scan lines S1 to Sn and the data lines D1 to Dm. Here, the data driver 20 includes m output lines to supply a data signal to each of the m data lines D1 to Dm. That is, in the conventional light emitting display device, the data driver 20 should have the same number of output lines as the data lines D1 to Dm. Accordingly, a plurality of data driving circuits are included in the data driver 20 so that m output lines are provided, thereby increasing a manufacturing cost. In particular, as the resolution and inch of the pixel unit 30 become larger, the data driver 20 includes more output lines, thereby further increasing the manufacturing cost.

Accordingly, it is an object of the present invention to provide a light emitting display device capable of reducing the number of output lines of a data driver.

In order to achieve the above object, the first aspect of the present invention sequentially supplies the first scan signal to the first scan lines during the first and second periods of the horizontal period and the second scan lines to the second scan lines during the first period. A scan driver for sequentially supplying two scan signals and sequentially supplying emission control signals to emission control lines overlapping the first and second periods; A data driver for sequentially supplying a plurality of data signals to respective output lines during the first period; Demultiplexers provided for each output line and having a plurality of switching elements connected between the output line and each of the plurality of data lines to supply the plurality of data signals supplied to the output lines to the plurality of data lines; ; A demultiplexer controller configured to supply a control signal to sequentially turn on the plurality of switching devices during the first period; A light emitting display including pixels for receiving the data signal during the first period, compensating the threshold voltage of the driving transistor during the second period, and generating light having a luminance corresponding to the data signal after the second period; Provide the device.

Preferably, each of the pixels comprises an organic light emitting diode; A second transistor connected to the data line and the first scan line and turned on when the first scan signal is supplied to supply the data signal to the first node; A storage capacitor having one terminal connected to the first node and the other terminal connected to the second node; The driving transistor for supplying a current corresponding to a voltage value applied to the second node from a first power supply to a second power supply via the organic light emitting diode; A third transistor connected between the second node and a second electrode of the driving transistor, the third transistor being turned on when the first scan signal is supplied to connect the driving transistor in the form of a diode; A fourth transistor connected between the second electrode of the driving transistor and an initialization power supply and turned on when the second scan signal is supplied; And a fifth transistor connected between the first node and the initialization power supply and turned on when the emission control signal is not supplied.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 2 to 6 that can be easily implemented by those skilled in the art.

2 is a diagram illustrating a light emitting display device according to an exemplary embodiment of the present invention.

Referring to FIG. 2, a light emitting display device according to an exemplary embodiment of the present invention may include a scan driver 110, a data driver 120, a pixel unit 130, a timing controller 150, a demultiplexer block unit 160, and a demultiplexer controller. 170 and data capacitors Cdata.

The pixel unit 130 is positioned in an area partitioned by first scan lines S11 to S1n, second scan lines S21 to S2n, emission control lines E1 to En, and data lines DL1 to DLm. A plurality of pixels 140 are provided. Each of the pixels 140 generates light corresponding to a data signal supplied to the pixels 140 from the data line DL.

The scan driver 110 receives the scan driving control signal SCS from the timing controller 150. The scan driver 110 supplied with the scan driving control signal SCS sequentially supplies the first scan signal to the first scan lines S11 to S1n, and the second scan signal to the second scan lines S21 to S2n. Supply sequentially. Here, the first scan signal and the second scan signal supplied to the same pixel 140 are supplied at the same time, and the width of the first scan signal is set wider than the width of the second scan signal. In addition, the scan driver 110 generates an emission control signal in response to the scan driving control signal SCS, and sequentially supplies the generated emission control signal to the emission control lines E1 to En. Here, the emission control signal is supplied to overlap with the first scan signal and is set to a width wider than the width of the first scan signal.

In detail, in the present invention, one horizontal period 1H is divided into a first period T1 and a second period T2 as shown in FIG. 4A. The scan driver 110 supplies the first scan signal and the second scan signal during the first period T1, and supplies only the first scan signal during the second period T2. The scan driver 110 supplies a light emission control signal during the first period T1 and the second period T2.

The data driver 120 receives the data drive control signal DCS from the timing controller 150. The data driver 120 receiving the data driving control signal DCS supplies the data signal to the output lines D1 to Dm / i. Here, the data driver 120 sequentially supplies j (j is a natural number of two or more) or j + 1 data signals as shown in FIG. 4A or 4B for each output line D1 to Dm / i.

In detail, the data driver 120 sequentially supplies the data signals R, G, and B to be supplied to the actual pixels during the first period T1 of one horizontal period 1H. That is, the data signals R, G, and B to be supplied to the actual pixels are supplied only during the first period T1 in which both the first scan signal and the second scan signal are supplied. The data driver 120 supplies the dummy data signal DD during the second period T2 of the one horizontal period 1H. Here, the dummy data DD may be variously set as data signals that do not contribute to the image. In fact, the dummy data signal DD may be selected as the last data signal B supplied in the first period T1 as shown in FIG. 4B. When the dummy data signal DD is selected as the last data signal B supplied in the first period T1, the number of times of switching of the data driver 120 is reduced to reduce power consumption.

The timing controller 150 generates data driving control signals DSC and scan driving control signals SCS in response to external synchronization signals. The data driving control signals DCS generated by the timing controller 150 are supplied to the data driver 120, and the scan driving control signals SCS are supplied to the scan driver 110.

The demultiplexer block unit 160 includes m / i demultiplexers 162. In other words, the demultiplexer block unit 160 includes the same number of demultiplexers 162 as the output lines D1 to Dm / i, and each of the demultiplexers 162 is any of the output lines D1 to Dm / i. Each is connected with one. The demultiplexer 162 supplies j data signals supplied to the first data period DL to the j data lines DL.

As such, when the data signal supplied to one output line D is supplied to the j data lines DL, the number of output lines included in the data driver 120 is drastically reduced. For example, assuming j is 3, the number of output lines included in the data driver 120 is reduced to about 1/3 of the conventional level, and thus the number of data driver circuits included in the data driver 120 is reduced. Will be. That is, in the present invention, the manufacturing cost can be reduced by supplying the data signals supplied to one output line D to the j data lines DL using the demultiplexer 162.

The demultiplexer control unit 170 controls the j control signals during the first period T1 of one horizontal period so that the j data signals supplied to the output line D can be divided into the j data lines DL and supplied. Supply to each of the demultiplexer 162. Here, the j control signals supplied from the demultiplexer controller 170 are sequentially supplied so as not to overlap with each other as shown in FIGS. 4A and 4B. Meanwhile, although the demultiplexer controller 170 is illustrated as being installed outside the timing controller 150, in the embodiment of the present invention, the demultiplexer controller 170 may be installed inside the timing controller 150.

The data capacitors Cdata are provided for each data line DL. The data capacitors Cdata temporarily store a data signal supplied to the data line DL and supply the stored data signal to the pixel 140. The data capacitor Cdata may be used as a parasitic capacitor that is equivalently formed in the data line DL. In addition, an external capacitor may be additionally provided for each data line DL to be used as a data capacitor Cdata. However, the capacity of the data capacitor Cdata is set larger than that of the storage capacitor C included in each pixel as shown in FIG. 5.

FIG. 3 is a diagram illustrating an internal circuit diagram of the demultiplexer illustrated in FIG. 2.

In FIG. 3, j is assumed to be 3 for convenience of description. It is assumed that the demultiplexer shown in FIG. 3 is connected to the first output line D1.

Referring to FIG. 3, each of the demultiplexers 162 includes a first switching element T11 (or a transistor), a second switching element T12, and a third switching element T13.

The first switching element T11 is connected between the first output line D1 and the first data line DL1. The first switching device T11 is turned on when the first control signal CS1 is supplied to supply the data signal supplied to the first output line D1 to the first data line DL1. The data signal supplied to the first data line DL1 is supplied to the pixel 140 and stored in the first data capacitor Cdata1.

The second switching element T12 is connected between the first output line D1 and the second data line DL2. The second switching device T12 is turned on when the second control signal CS2 is supplied and supplies the data signal supplied to the first output line D1 to the second data line DL2. The data signal supplied to the second data line DL2 is supplied to the pixel 140 and stored in the second data capacitor Cdata2.

The third switching element T13 is connected between the first output line D1 and the third data line DL3. The third switching device T13 is turned on when the third control signal CS3 is supplied to supply the data signal supplied to the first output line D1 to the third data line DL3. The data signal supplied to the third data line DL3 is supplied to the pixel 140 and stored in the third data capacitor Cdata3. The detailed operation of the demultiplexer 162 will be described later in combination with the structure of the pixel 140.

FIG. 5 is a circuit diagram illustrating a structure of a pixel illustrated in FIG. 2. In FIG. 5, for convenience of description, the pixel connected to the m-th data line Dm, the 1st scan line S1n, the 2nd scan line S2n, and the nth emission scan line En will be illustrated.

Referring to FIG. 5, the pixel 140 of the present invention is connected to the organic light emitting diode OLED, the data line Dm, the scan lines S1n and S2n, and the emission control line En so that the organic light emitting diode OLED is connected. And a pixel circuit 142 for controlling the amount of current supplied to the.

The anode electrode of the organic light emitting diode OLED is connected to the pixel circuit 142, and the cathode electrode is connected to the second power source ELVSS. Here, the voltage value of the second power supply ELVSS is set lower than the voltage value of the first power supply ELVDD. As described above, the organic light emitting diode OLED generates light having a predetermined luminance corresponding to the amount of current supplied from the pixel circuit 142.

The pixel circuit 142 receives a data signal from the data line Dm when a scan signal is supplied to the 1n scan line S1n and the 2n scan line S2n, and corresponds to the data signal to the organic light emitting diode OLED. Control the amount of current supplied to To this end, the pixel circuit 142 includes first to sixth transistors M1 to M6 and a storage capacitor C.

The first electrode of the second transistor M2 is connected to the data line Dm, and the second electrode is connected to the first node N1. The gate electrode of the second transistor M2 is connected to the 1n scan line S1n. The second transistor M2 is turned on when the first scan signal is supplied to the first n scan line S1n to supply the data signal supplied to the data line Dm (or data capacitor) to the first node N1. To supply.

The first electrode of the first transistor M1 (or the driving transistor) is connected to the first power source ELVDD, and the second electrode is connected to the first electrode of the sixth transistor M6. The gate electrode of the first transistor M1 is connected to the second node N2. The first transistor M1 supplies a current corresponding to the voltage applied to the second node N2 to the organic light emitting diode OLED.

The first electrode of the third transistor M3 is connected to the second electrode of the first transistor M1, and the second electrode is connected to the gate electrode of the first transistor M1. The gate electrode of the third transistor M3 is connected to the 1n scan line S1n. The third transistor M3 is turned on when the first scan signal is supplied to the 1n scan line S1n to connect the first transistor M1 in the form of a diode.

The first electrode of the fourth transistor M4 is connected to the second electrode of the first transistor M1, and the second electrode is connected to the initialization power supply Vint. The gate electrode of the fourth transistor M4 is connected to the second n scan line S2n. The fourth transistor M4 is turned on when the second scan signal is supplied to the second n scan line S2n.

The first electrode of the fifth transistor M5 is connected to the first node N1, and the second electrode is connected to the initialization power supply Vint. The gate electrode of the fifth transistor M5 is connected to the emission control line En. The fifth transistor M5 is turned on when the emission control signal is not supplied from the emission control line En to change the voltage value of the first node N1 to the voltage value of the initialization power supply Vint.

The first electrode of the sixth transistor M6 is connected to the second electrode of the first transistor M1, and the second electrode is connected to the anode electrode of the organic light emitting diode OLED. The gate electrode of the sixth transistor M6 is connected to the emission control line En. The sixth transistor M6 is turned on when the emission control signal is not supplied to supply the current supplied from the first transistor M1 to the organic light emitting diode OLED.

The storage capacitor C is installed between the first node N1 and the second node N2 to charge a predetermined voltage.

6 is a diagram illustrating in detail a connection structure of a demultiplexer and pixels. Here, it is assumed that pixels of red (R), green (G), and blue (B) are connected to one demultiplexer (ie, j = 3).

4A and 6, the operation process will be described in detail. First, the first scan signal is supplied to the 1n scan line S1n during the first period T1 of one horizontal period, and the second scan line S2n is simultaneously applied. Two scan signals are supplied. When the first scan signal and the second scan signal are supplied during the first period T1, the second transistor M2, the third transistor M3, and the fourth transistor included in each of the pixels 140R, 140G, and 140B may be provided. M4) is turned on. In addition, the first switching device T11, the second switching device T12, and the third switching device according to the first control signal CS1 to the third control signal CS3 sequentially supplied during the first period T1. T13 is sequentially turned on.

When the first switching device T11 is turned on by the first control signal CS1, the data signal R supplied to the first output line D1 is supplied to the first data line DL1. In this case, the data signal R supplied to the first data line DL1 is stored in the first data capacitor Cdata1 and supplied to the first node N1 of the pixel 140R. Then, the first node N1 of the pixel 140R is set to the voltage value of the data signal R, and the second node N2 is set to the voltage value of the initialization power supply Vint.

When the second switching device T12 is turned on by the second control signal CS2, the data signal G supplied to the first output line D1 is supplied to the second data line DL2. At this time, the data signal G supplied to the second data line DL2 is stored in the second data capacitor Cdata2 and supplied to the first node N1 of the pixel 140G. Then, the first node N1 of the pixel 140G is set to the voltage value of the data signal G, and the second node N2 is set to the voltage value of the initialization power supply Vint.

When the third switching device T13 is turned on by the third control signal CS3, the data signal B supplied to the first output line D1 is supplied to the third data line DL3. At this time, the data signal B supplied to the third data line DL3 is stored in the third data capacitor Cdata3 and supplied to the first node N1 of the pixel 140B. Then, the first node N1 of the pixel 140B is set to the voltage value of the data signal B, and the second node N2 is set to the voltage value of the initialization power supply Vint.

Thereafter, the supply of the second scan signal is stopped during the second period T2. Then, the fourth transistor M4 included in each of the pixels 140R, 140G, and 140B is turned off. At this time, since the first transistor M1 included in each of the pixels 140R, 140G, and 140B is connected in the form of a diode, the voltage value of the second node N2 is the first value from the voltage value of the first power supply ELVDD. It is set to a value obtained by subtracting the threshold voltage of the transistor M1. (Ie, the second period T2 is a period for compensating the threshold voltage of the first transistor M1.) Then, the data capacitors Cdata1, Cdata2, and Cdata3. ), The first node N1 of each of the pixels 140R, 140G, and 140B maintains the voltage value of the data signal.

Subsequently, supply of the first scan signal is stopped to turn off the second transistor M2 and the third transistor M3 included in each of the pixels 140R, 140G, and 140B. The fifth transistor M5 and the sixth transistor M6 included in each of the pixels 140R, 140G, and 140B are turned off by supplying the emission control signal. When the fifth transistor M5 is turned on, the voltage value of the first node N1 included in each of the pixels 140R, 140G, and 140B is lowered to the voltage value of the initialization power supply Vint. In other words, the voltage value of the first node N1 is lowered from the voltage value of the data signal to the voltage value of the initialization power supply Vint. In this case, since the second node N2 included in each of the pixels 140R, 140G, and 140B is set to the floating state, the voltage value of the second node N2 also corresponds to the voltage value of the first node N1. To descend. For example, the voltage value of the second node N2 is decreased by the voltage of the data signal from the voltage value obtained by subtracting the threshold voltage of the first transistor M1 from the first power supply ELVDD.

Then, the first transistor M1 included in each of the pixels 140R, 140G, and 140B receives the current corresponding to the voltage value applied to the second node N2 via the sixth transistor M6. (OLED), and light of a predetermined luminance is generated in the organic light emitting diode (OLED). In this case, the amount of current supplied from the first transistor M1 is determined by the data signal. In other words, since the voltage value dropped at the second node N2 is determined by the voltage value of the data signal, the amount of current supplied to the organic light emitting diode OLED is determined by the data signal. In addition, since the initial voltage value of the second node N2 is determined as a value obtained by subtracting the threshold voltage of the first transistor M1 from the first power supply ELVDD, the pixel portion is independent of the threshold voltage of the first transistor M1. A uniform image can be displayed at 130.

In the present invention as described above, since the data signal supplied to one output line D1 can be supplied to the j data lines DL by using the demultiplexer 162, manufacturing cost can be reduced. In the present invention, since the voltage value of the first node N1 is maintained at the voltage value of the data signal using the data capacitor Cdata, the image can be stably displayed. In addition, the fourth transistor M4 that supplies the initialization power supply Vint from the pixel 140 of the present invention is connected to the second electrode of the first transistor M1. Therefore, a leakage current does not flow from the gate electrode of the first transistor M1 to the initialization power supply Vint, and thus an image having a desired luminance can be displayed.

The above detailed description and drawings are merely exemplary of the present invention, but are used only for the purpose of illustrating the present invention and are not intended to limit the scope of the present invention as defined in the meaning or claims. Accordingly, those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical protection scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

As described above, according to the light emitting display device according to an exemplary embodiment of the present invention, since the data signal supplied to one output line is divided and supplied into a plurality of data lines, the number of output lines can be reduced, thereby manufacturing cost Can be reduced. In the present invention, since the data signal is stored in the data capacitor and the stored data signal is supplied to the pixel during the period in which the first scan signal is supplied, stable driving can be ensured. In the pixel of the present invention, since the gate electrode of the driving transistor and the transistor for supplying the initialization power supply are not connected, leakage current can be prevented from being generated, thereby displaying an image having a desired luminance.

Claims (10)

Sequentially supplying the first scan signal to the first scan lines during the first period and the second period of the horizontal period, and sequentially supplying the second scan signal to the second scan lines during the first period, A scan driver for sequentially supplying light emission control signals to the light emission control lines so as to overlap with the second period; A data driver for sequentially supplying a plurality of data signals to respective output lines during the first period; Demultiplexers provided for each output line and having a plurality of switching elements connected between the output line and each of the plurality of data lines to supply the plurality of data signals supplied to the output lines to the plurality of data lines; ; A demultiplexer controller configured to supply a control signal to sequentially turn on the plurality of switching devices during the first period; A light emitting display including pixels for receiving the data signal during the first period, compensating the threshold voltage of the driving transistor during the second period, and generating light having a luminance corresponding to the data signal after the second period; Device. delete delete The method of claim 1, And the data driver supplies a dummy data signal that does not contribute to luminance during the second period. The method of claim 4, wherein And the dummy data signal is a last data signal supplied in the first period. The method of claim 1, Each of the pixels An organic light emitting diode; A second transistor connected to the data line and the first scan line and turned on when the first scan signal is supplied to supply the data signal to the first node; A storage capacitor having one terminal connected to the first node and the other terminal connected to the second node; The driving transistor for supplying a current corresponding to a voltage value applied to the second node from a first power supply to a second power supply via the organic light emitting diode; A third transistor connected between the second node and a second electrode of the driving transistor, the third transistor being turned on when the first scan signal is supplied to connect the driving transistor in the form of a diode; A fourth transistor connected between the second electrode of the driving transistor and an initialization power supply and turned on when the second scan signal is supplied; And a fifth transistor connected between the first node and the initialization power source and turned on when the emission control signal is not supplied. The method of claim 6, And a voltage value of the second node is set to a value obtained by subtracting a threshold voltage of the driving transistor from the first power supply during the second period. The method of claim 7, wherein And the fifth transistor is turned on after the second period so that the voltage value of the first node is lowered from the voltage of the data signal to the voltage of the initialization power supply. The method of claim 8, And a voltage value of the second node, which is set to the floating state after the second period, corresponds to a voltage drop amount of the first node. The method of claim 6, And a sixth transistor connected between the second electrode of the driving transistor and the organic light emitting diode and turned on when the emission control signal is not supplied.

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