KR100730141B1 - Thin film transistor and flat panel display device with the same - Google Patents

Abstract

The present invention discloses a thin film transistor for a flat panel display device capable of removing the kink effect and a flat panel display device having the same. To this end, the thin film transistor of the present invention includes a semiconductor layer, a gate electrode and a source / drain electrode formed on the substrate; A gate insulating film formed between the semiconductor layer and the gate electrode; And a carrier trap layer formed between the gate insulating film and the semiconductor layer.

The carrier trap layer includes a plasma, UV, or O3 oxidized oxide film, or the carrier trap layer includes a natural oxide film. The carrier trap layer has a thickness of 20 to 100 GPa and has an interface trap density of 3x10 ¹⁰ cm ^-2 eV ^-1 or more at an interface between the semiconductor layer and the gate insulating layer.

Description

Thin film transistor and flat panel display device with the same

1 is a cross-sectional view of a conventional thin film transistor.

2 is a voltage-current characteristic diagram of a conventional thin film transistor.

3 is a cross-sectional view of a thin film transistor according to an exemplary embodiment of the present invention.

4 is a voltage-current characteristic diagram of a thin film transistor according to an exemplary embodiment of the present invention.

5A through 5D are cross-sectional views illustrating a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention.

6A to 6F are cross-sectional views illustrating a method of manufacturing a thin film transistor according to another exemplary embodiment of the present invention.

7 is a cross-sectional view of an organic light emitting display device having a thin film transistor according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

200, 300: substrate 220, 310: semiconductor layer

270, 340: carrier trap layer 230, 320: gate insulating film

240, 325: gate electrode 250, 330: interlayer insulating film

261, 265, 341 345: source / drain electrodes

223 channel region 360 anode electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display device, and more particularly, to a thin film transistor for a flat panel display device having improved gray scale display capability and driving ability, and an organic light emitting display device having the same.

Among the flat panel display devices, the organic light emitting display device is a self-luminous display device, and has attracted attention as a next generation display device because it has the advantages of wide viewing angle, excellent contrast, and fast response speed. Such organic light emitting display devices are classified into an active matrix display device and a passive matrix display device according to a driving method.

In general, an active matrix organic light emitting display device includes a pixel portion in which pixels are arranged in a matrix, and a driving circuit portion in which a driving circuit for driving the pixel is arranged. Each pixel arranged in the pixel portion includes at least two thin film transistors, one capacitor, and one organic light emitting element. A thin film transistor constituting each pixel is usually composed of a P type thin film transistor, and a driving circuit arranged in the driving circuit portion is usually composed of a P type thin film transistor and a CMOS thin film transistor of an N type thin film transistor.

Since the organic light emitting (EL) device of the pixel is driven by the P-type thin film transistor to display an image, it is preferable that the thin film transistor has a current-voltage characteristic capable of obtaining the same drain current in a wide drain voltage range. On the other hand, the thin film transistor constituting the driving circuit portion is preferably excellent in the on / off characteristics of the drain current according to the voltage provided to the gate voltage.

1 is a cross-sectional view of a conventional thin film transistor. Referring to FIG. 1, a buffer layer 110 is formed on a substrate 100, and a semiconductor layer 120 includes a source region 121, a drain region 125, and a channel region 123 on the buffer layer 110. ) Is formed. A gate 140 is formed on the gate insulating layer 130, and an interlayer insulating layer 150 is formed on the gate insulating layer 130 including the gate 140. Source and drain electrodes 161 and 165 are formed on the interlayer insulating layer 150 through contact holes 151 and 155 in the source region 121 and the drain region 125, respectively.

In the conventional thin film transistor for flat panel display device, the semiconductor layer 120 has an island-shaped pattern structure, and a floating thin film transistor in which the power is not applied to the semiconductor layer 120 is mainly used. As the resolution of the flat panel display device increases, the size of the thin film transistor decreases, and a strong lateral electric field is applied to the drain side. Therefore, when a strong lateral electric field is applied to the drain side of the thin film transistor, unwanted hot carriers, for example, holes, are generated near the boundary between the channel region 123 and the drain region 125.

The hot carriers generated near the boundary between the channel region 123 and the drain region 125 of the floating thin film transistor are accumulated without being discharged because the semiconductor layer 120 is floating. The kink effect such as the breakdown voltage and the threshold voltage of the thin film transistor is changed due to the hot carrier generated near the boundary between the channel region 123 and the drain region 125 of the semiconductor layer 120. 2 shows that in a conventional floating thin film transistor, a kink effect (part A) is generated by a hot carrier.

When the conventional floating thin film transistor as described above is used in the organic light emitting display device, the current-voltage characteristic of the thin film transistor is distorted due to the kink effect in the pixel portion, and gray scale display is difficult. There was a problem that occurred.

In order to prevent such kink effect, Korean Patent Laid-Open Publication Nos. 2003-0050906 and 2003-0050907 have proposed multiple gate thin film transistors. The multiple gate thin film transistor has a structure in which a plurality of gates are arranged corresponding to one channel region.

In addition, in order to prevent the kink effect, Korean Patent Publication Nos. 2004-0092916 and 2005-0028559 have proposed body contact thin film transistors. The body contact thin film transistor connects the channel region of the semiconductor layer to one of the source / drain electrodes to form a discharge path of the hot carrier.

However, since the multiple gate thin film transistor has a structure in which a plurality of gates are arranged with respect to the channel region, and the body contact thin film transistor requires a separate wiring line for connecting the channel region to the source electrode, the layout area is There was a problem that the opening ratio decreases.

The present invention is to solve the problems of the prior art as described above, to provide a thin film transistor for a flat panel display device that can prevent the kink effect and a flat panel display device having the same.

In order to achieve the above object, the present invention is a semiconductor layer, a gate electrode and a source / drain electrode formed on the substrate; A gate insulating film formed between the semiconductor layer and the gate electrode; And a carrier trap layer formed between the gate insulating layer and the semiconductor layer.

The carrier trap layer includes a plasma, UV, or O3 oxidized oxide film, or the carrier trap layer includes a natural oxide film.

The carrier trap layer has a thickness of 20 to 100 GPa and has an interface trap density of 3x10 ¹⁰ cm ^-2 eV ^-1 or more at an interface between the semiconductor layer and the gate insulating layer. In addition, the carrier trap layer has an S-factor of 0.3 V / dec or more and has a kink current generation voltage of 12 V or more.

In addition, the present invention comprises the steps of forming a conductive film on the substrate; Patterning the conductive film to form a semiconductor layer, and simultaneously forming a carrier trap layer on the surface of the semiconductor layer; Forming a gate insulating film on the substrate; Forming a gate on the gate insulating film; Forming an interlayer insulating film on the substrate; Etching the interlayer insulating film, the gate insulating film, and the carrier trap layer to form a contact hole exposing the semiconductor layer; And forming a source electrode and a drain electrode connected to the semiconductor layer through the contact hole, on the interlayer insulating film.

The carrier trap layer is formed of a natural oxide film formed on the surface of the semiconductor layer when the conductive layer is patterned to form a semiconductor layer.

In addition, the present invention comprises the steps of forming a conductive film on the substrate; Patterning the conductive film to form a semiconductor layer; A cleaning step of removing a natural oxide film formed on a surface of the semiconductor layer in the forming of the semiconductor layer; Forming a carrier trap layer on a surface of the semiconductor layer; Forming a gate insulating film on the carrier trap layer; Forming a gate on the gate insulating film; Forming an interlayer insulating film on the substrate; Etching the interlayer insulating film, the gate insulating film, and the carrier trap layer to form a contact hole exposing the semiconductor layer; And forming a source electrode and a drain electrode connected to the semiconductor region through the contact hole, on the interlayer insulating layer.

The carrier trap layer is composed of an oxide film formed by plasma, UV or O3 oxidation treatment.

A flat panel display comprising a thin film transistor manufactured by the method for manufacturing the thin film transistor is provided.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

3 is a cross-sectional view of a thin film transistor according to an exemplary embodiment of the present invention. Referring to FIG. 3, in the thin film transistor according to the exemplary embodiment, a buffer layer 210 is formed on a substrate 200, and a semiconductor layer 220 is formed on the buffer layer 210. The semiconductor layer 2200 includes a source region 221 and a drain region 225, and a channel layer 223 between the source region 221 and the drain region 225.

A gate insulating layer 230 is formed on the buffer layer 210 including the semiconductor layer 220, and a gate 240 is formed on the gate insulating layer 230. An interlayer insulating layer 250 is formed on the gate insulating layer 230 including the gate 240. The source electrode 261 and the drain electrode 265 connected to the source region 221 and the drain region 225 through the contact holes 251 and 255 are formed on the interlayer insulating layer 250, respectively.

In the thin film transistor of the present invention, a carrier trap layer 270 is interposed between the semiconductor layer 220 and the gate insulating layer 230. The carrier trap layer 270 may be formed of a natural oxide film formed when the polysilicon film for forming the semiconductor layer 220 is patterned, or may be formed of a plasma, UV, or O 3 oxidized film. The carrier trap layer 270 preferably has a thickness of 20 to 100 kPa.

The carrier trap layer 270 forms an interface having a carrier trap density between the semiconductor layer 220 and the gate insulating layer 230. At this time, at the interface between the semiconductor layer 220 and the gate insulating film 230, the carrier trap density is preferably 3x10 ¹⁰ cm ^-2 eV ^-1 or more. Accordingly, unwanted hot carriers generated at the boundary between the channel layer 223 and the drain region 225 are trapped in the carrier trap layer 270 without accumulating in the channel layer 223.

4 illustrates current-voltage characteristics of a thin film transistor in which a natural oxide film is formed as a carrier trap layer 270. Referring to FIG. 4, it can be seen that the kink effect is prevented by trapping a hot carrier in the carrier trap layer 270 formed between the semiconductor layer 220 and the gate insulating layer 230.

Table 1 shows the characteristics of the thin film transistor of the present invention in which the carrier capping layer 270 is formed and the conventional thin film transistor in which the natural oxide film as shown in FIG. 1 is removed through the HF cleaning process. It can be seen from Table 1 that the conventional thin film transistor has a S-factor of 0.25 V / dec or less and a king current generation voltage of 7 V or less. On the other hand, in the present invention, the S-factor is 0.3 V / dec or more in which gradation can be expressed, and the kink current generation voltage is also 12 V or more. Therefore, when the thin film transistor of the present invention is applied to a flat panel display, for example, an organic light emitting display, the gray scale display capability and the driving capability can be improved.

In addition, referring to Table 1, in the case of the thin film transistor in which the natural oxide film of FIG. 1 is removed through the HF cleaning process, the interface carrier trap density (Dit) at the interface between the semiconductor layer 120 and the gate insulating film 130 is shown. Is 2 × 10 ¹⁰ cm ⁻² eV ⁻¹ or less, in the present invention, the interface carrier trap density (Dit) at the interface between the semiconductor layer 220 and the gate insulating film 230 is increased according to the formation of the carrier trap layer 270. 3x10 ¹⁰ cm ^-2 eV ^-1 or more, it can be seen that the trapping ability of the carrier is improved.

Table 1

Interface property The present invention Conventional Dit (cm ^-2 eV ^-1 ) > 3x10 ¹⁰ <2x10 ¹⁰ S-factor (V / dec) > 0.3 <0.25 Kink current generating voltage (V) > 12 <7V

5A through 5D are cross-sectional views illustrating a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention.

Referring to FIG. 5A, a buffer layer 210 is formed on a substrate 200, and a conductive film 220a is formed on the buffer layer 210. The substrate 200 may include a glass substrate, a plastic substrate, or a metal substrate. The buffer layer 210 may include an organic insulating layer, an inorganic insulating layer, or an organic-inorganic hybrid layer, and may include a single layer or a multilayer layer. The conductive film 220a may include a silicon film such as a polysilicon film, an amorphous silicon film, or the like.

Referring to FIG. 5B, a photoresist film (not shown) is deposited on the conductive film 220a and then patterned to form a photoresist pattern. The conductive layer 220a is etched using the photosensitive layer pattern as a mask to form a semiconductor layer 220. At this time, when the conductive layer 220a for forming the semiconductor layer 220 is etched, a natural oxide film is formed on the surface of the semiconductor layer 220, and the natural oxide film serves as a carrier trap layer 270. do. That is, the natural oxide film is not removed through the HF cleaning process, and the carrier trap layer 270 for trapping the carrier is formed at the interface between the semiconductor layer 220 and the gate insulating film 230 formed in a subsequent process.

Referring to FIG. 5C, a gate insulating layer 230 is formed on the buffer layer 210 on which the semiconductor layer 220 and the carrier trap layer 270 are formed. The gate insulating layer 230 may include a single layer or a multilayer, and may include an inorganic insulating layer, an organic insulating layer, or an organic-inorganic hybrid layer.

Referring to FIG. 5D, a gate electrode material is deposited on the gate insulating layer 240, and then patterned to form the gate electrode 240. After the gate electrode 240 is formed, a source region 221 and a drain region 225 are formed by ion implanting impurities of a predetermined conductivity type, for example, p-type impurities, into the semiconductor layer 220. A region of the semiconductor layer 220 which is not doped with impurities between the source region 221 and the drain region 225 serves as the channel region 223.

Subsequently, as shown in FIG. 3, an interlayer insulating layer 250 is formed on the gate insulating layer 230 on which the gate electrode 240 is formed. The interlayer insulating layer 250 may include a single layer or a multilayer layer of an organic insulating layer or an inorganic insulating layer, or may include an organic-inorganic hybrid layer. Contact holes 251 and 255 exposing portions of the source region 221 and the drain region 225 by etching the interlayer insulating layer 250, the gate insulating layer 230, and the carrier trap layer 270. Form. Source and drain electrode materials are deposited on the interlayer insulating layer 250 and then patterned to form source electrodes connected to the source region 221 and the drain region 225 through the contact holes 251 and 255, respectively. 261 and the drain electrode 265 are formed.

6A through 6F are cross-sectional views illustrating a method of manufacturing a thin film transistor according to another exemplary embodiment of the present invention. The method of manufacturing a thin film transistor according to another exemplary embodiment of the present invention is different from that of the exemplary embodiment in which a natural oxide film is removed and an oxide film for a carrier trap layer is separately formed.

Referring to FIG. 6A, a buffer layer 210 is formed on a substrate 200, and a silicon film, such as a polysilicon film or an amorphous silicon film, is formed on the buffer layer 210. Referring to FIG. 6B, a photoresist film (not shown) is deposited on the conductive film 220a and then patterned to form a photoresist pattern. The conductive layer 220a is etched using the photosensitive layer pattern as a mask to form a semiconductor layer 220. At this time, during the etching of the conductive film 220a for forming the semiconductor layer 220, a natural oxide film 270a is formed on the surface of the semiconductor layer 220.

Referring to FIG. 6C, the natural oxide film 270a formed on the surface of the semiconductor layer 220 is removed through an HF cleaning process. Referring to FIG. 6D, the carrier trap layer 270 is formed on the exposed surface of the semiconductor layer 220 as the natural oxide layer 270a is removed. The carrier trap layer 270 includes an oxide film formed on the surface of the semiconductor layer 220 through plasma, UV, or O 3 oxidation treatment.

Referring to FIG. 6E, a gate insulating layer 230 is formed on the buffer layer 210 on which the semiconductor layer 220 and the carrier trap layer 270 are formed. Referring to FIG. 6F, a gate electrode material is deposited on the gate insulating layer 240, and then patterned to form a gate electrode 240. After the gate electrode 240 is formed, a source region 221 and a drain region 225 are formed by ion implanting impurities of a predetermined conductivity type, for example, p-type impurities, into the semiconductor layer 220. A region of the semiconductor layer 220 which is not doped with impurities between the source region 221 and the drain region 225 serves as the channel region 223.

3, an interlayer insulating layer 250 is formed on the gate insulating layer 230, and then the source region 221 and the drain region are formed through the contact holes 251 and 255. The source electrode 261 and the drain electrode 265 respectively connected to 225 are formed.

7 is a cross-sectional view of an organic light emitting display device having a thin film transistor according to an exemplary embodiment of the present invention.

Referring to FIG. 7, a buffer layer 305 is formed on a substrate 300, and a semiconductor layer 310 and a carrier trap layer 340 are formed on the buffer layer 305. The substrate 300 includes a glass substrate, a plastic substrate or a metal substrate. The buffer layer 305 may include an organic insulating film, an inorganic insulating film, or an organic-inorganic hybrid film, and may be formed of a single layer or a multilayer. The semiconductor layer 310 may include a silicon film such as a polysilicon film, an amorphous silicon film, or the like.

The carrier trap layer 340 may include a natural oxide film formed on the surface of the semiconductor layer 310 when the silicon layer is patterned to form the semiconductor layer 310. In addition, the carrier trap layer 340 removes the natural oxide film formed during the patterning of the semiconductor layer 310 through an HF cleaning process and then forms an oxide film formed on the surface of the semiconductor layer 310 through plasma, UV, or O3 oxidation. It may include.

A gate insulating film 320 is formed on the substrate, and then a gate electrode 325 is formed on the gate insulating film 320. A source region 311 and a drain region 315 are formed by ion implanting impurities of a predetermined conductivity type, for example, p-type impurities, into the semiconductor layer 310. A portion of the semiconductor layer 310 between the source region 311 and the drain region 315 serves as a channel region 313. The gate insulating layer 320 may include an organic insulating layer, an inorganic insulating layer, or a hybrid layer of a single layer or a multilayer.

An interlayer insulating layer 330 is formed on the gate insulating layer 320 including the gate electrode 325. The interlayer insulating layer 330 may include an organic insulating layer, an inorganic insulating layer, or an organic-inorganic hybrid layer of a single layer or a multilayer. The interlayer insulating layer 330, the gate insulating layer 320, and the carrier trap layer 340 are etched to form contact holes 331 and 335 exposing portions of the source region 311 and the drain region 315. do. Source electrodes 341 and 345 connected to the source region 311 and the drain region 315 are formed on the interlayer insulating layer 330 through the contact holes 331 and 335.

An insulating film 350 is formed on the interlayer insulating film 330 including the source electrode 341 and the drain electrode 345. The insulating film 350 includes a passivation film 350a and a planarization film 350b. The passivation layer 350a may include an organic insulating layer or an inorganic insulating layer of a single layer or a multilayer. The planarization film 350b includes an organic insulating film. The insulating layer 350 is etched to form a via hole 355 exposing the drain electrode 345 of the source electrode 341 and the drain electrode 345.

An anode electrode 360 is formed on the insulating layer 350 as a pixel electrode connected to the drain electrode 345 through the via hole 355. The anode electrode 360 includes a reflective film 360a and a transparent conductive film 360b. The anode electrode 360 has a double layer of the reflective film 360a and the transparent conductive film 360b. However, the anode electrode 360 is not limited thereto and may have various structures such as a triple film.

A pixel isolation layer 370 having an opening 375 exposing a portion of the anode electrode 360 is formed on the insulating layer 370, and the anode electrode 360 in the opening 375 of the pixel isolation layer 370 is formed. The organic film layer 380 is formed on (). The organic layer 380 includes at least one organic layer selected from a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer and a hole suppression layer. The cathode electrode 390 is formed on the front surface of the substrate.

The structure of the thin film transistor and the organic light emitting device constituting each pixel of the pixel area according to the embodiment of the present invention is not limited to the structure shown in FIG. 7 but may have various structures, and not only the top light emitting organic light emitting display device. The present invention can also be applied to a bottom emission type or a bilateral emission type organic light emitting display device. In addition, the thin film transistor of the present invention can be applied to a flat panel display device such as a liquid crystal display device using a thin film transistor as a switching element.

According to the embodiment of the present invention as described above, by forming a carrier trap layer between the semiconductor layer and the gate insulating film to trap unwanted hot carriers generated at the boundary between the drain electrode and the channel layer, the kink effect can be prevented. Therefore, the gray scale display ability can be improved.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (17)

A semiconductor layer, a gate electrode, and a source / drain electrode formed on the substrate; A gate insulating film formed between the semiconductor layer and the gate electrode; And A carrier trap layer formed between the gate insulating film and the semiconductor layer, The carrier trap layer has a thickness of 20 to 100 kHz. The thin film transistor of claim 1, wherein the carrier trap layer comprises one of plasma, UV, and O 3 oxidized oxide films. The thin film transistor of claim 1, wherein the carrier trap layer comprises a native oxide film. delete The method of claim 1, wherein the carrier trap layer is 3x10 ¹⁰ / eV · ㎠ at the interface with the semiconductor layer and the gate insulating film A thin film transistor having the above interface carrier trap density. The thin film transistor of claim 1, wherein the carrier trap layer has an S-factor of 0.3 V / dec or more and a kink current generation voltage of 12 V or more. Forming a conductive film on the substrate; Patterning the conductive film to form a semiconductor layer, and at the same time forming a carrier trap layer on the surface of the semiconductor layer, forming the carrier trap layer to have a thickness of 20 to 100 GPa; Forming a gate insulating film on the substrate; Forming a gate on the gate insulating film; Implanting impurities into the semiconductor layer to form a source region and a drain region; Forming an interlayer insulating film on the substrate; Etching the interlayer insulating film, the gate insulating film, and the carrier trap layer to form a contact hole exposing the source region and the drain region; And Forming a source electrode and a drain electrode connected to the source region and the drain region through the contact hole on the interlayer insulating layer. The method of claim 7, wherein the carrier trap layer comprises a natural oxide film formed on a surface of the semiconductor layer when the conductive layer is patterned to form a semiconductor layer. delete The method of claim 7, wherein the carrier trap layer is 3x10 ¹⁰ / eV · cm 2 at the interface between the semiconductor layer and the gate insulating film. The thin film transistor manufacturing method which has the above interface trap density. The method of claim 7, wherein the carrier trap layer has an S-factor of 0.3 V / dec or more and a kink current generation voltage of 12 V or more. Forming a conductive film on the substrate; Patterning the conductive film to form a semiconductor layer; A cleaning step of removing a natural oxide film formed on a surface of the semiconductor layer in the forming of the semiconductor layer; Forming a carrier trap layer on a surface of the semiconductor layer, wherein the carrier trap layer is formed to have a thickness of about 20 to about 100 microns; Forming a gate insulating film on the carrier trap layer; Forming a gate on the gate insulating film; Implanting impurities into the semiconductor layer to form a source region and a drain region; Forming an interlayer insulating film on the substrate; Etching the interlayer insulating film, the gate insulating film, and the carrier trap layer to form a contact hole exposing the source region and the drain region; And Forming a source electrode and a drain electrode connected to the source region and the drain region through the contact hole on the interlayer insulating layer. The method of claim 12, wherein the carrier trap layer is formed of an oxide film formed by plasma, UV, or O 3 oxidation treatment. delete The method of claim 12, wherein the carrier trap layer is 3x10 ¹⁰ / eV · ㎠ at the interface with the semiconductor layer and the gate insulating film The thin film transistor manufacturing method which has the above interface trap density. The method of claim 12, wherein the carrier trap layer has an S-factor of 0.3 V / dec or more and a kink current generation voltage of 12 V or more. A semiconductor layer formed on the substrate and having a source region and a drain region; A gate insulating film formed on the substrate and the semiconductor layer; A carrier trap layer formed between the gate insulating film and the semiconductor layer; A gate formed on the gate insulating film between the source and drain regions; An interlayer insulating film formed on the gate and the gate insulating film; Source and drain electrodes formed on the interlayer insulating layer and connected to the source and drain regions through contact holes, respectively; An insulating film formed on the interlayer insulating film and the source and drain electrodes; And A display element formed on the insulating layer and having a pixel electrode connected to one of the source and drain electrodes; And the carrier trap layer forms an interface having a trap density between the gate insulating film and the semiconductor layer.

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