KR100725975B1 - Voltage generation circuit, Voltage generation method, and analog to digital converter - Google Patents

Abstract

A voltage generating circuit, a voltage generating method, and an analog to digital converter are disclosed. The voltage generator circuit includes a voltage divider circuit, a control current generator circuit, and a plurality of switches. The voltage divider circuit includes a first terminal for receiving a first reference voltage, a second terminal for receiving a second reference voltage, and a plurality of nodes, the voltage dividing circuit being configured to generate the divided voltages. The difference of the second reference voltage is divided, and each of the divided voltages is output through a corresponding node among the plurality of nodes. The control current generating circuit generates a control current based on an arithmetic mean voltage of the first reference voltage and the second reference voltage. Each of the plurality of switches is connected between an output terminal of the current generating circuit and a corresponding node among the plurality of nodes, and at least one of the plurality of switches is switched in response to a corresponding control signal.

ADC, DAC

Description

Voltage generation circuit, voltage generation method, and analog-to-digital converter

The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.

1 shows a circuit diagram of a conventional analog-to-digital converter.

2A is a graph showing conversion characteristics of an analog-to-digital converter without INL.

2B is a graph showing conversion characteristics of an analog-to-digital converter having INL.

3 shows a circuit diagram of a voltage generating circuit according to an embodiment of the present invention.

4 shows a circuit diagram of an analog to digital converter according to an embodiment of the present invention.

5 is a circuit diagram of an analog-to-digital converter according to another embodiment of the present invention.

FIG. 6 is a graph illustrating conversion characteristics with INL reduced by the analog-to-digital converter according to the present invention shown in FIGS. 4 and 5.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to integrated circuits, and more particularly, to a voltage generating circuit and a voltage generating method capable of alleviating integrated nonlinearity (INL), and an analog-to-digital converter having the voltage generating circuit. .

1 shows a circuit diagram of a conventional analog-to-digital converter. Referring to FIG. 1, an analog / digital converter (ADC) 10 for converting an analog signal into a digital signal includes a voltage distribution circuit 20, a plurality of comparators 41, 42, 43, ... , 44, and 45, and an encoder 50.

The voltage divider circuit 20 may also be referred to as a plurality of resistors connected between the reference voltage Vref and the ground voltage VSS (referred to as a resistor ladder or a resistor string). .) Divides the difference between the reference voltage (Vref) and the ground voltage (VSS) at a predetermined voltage interval, and each of the divided voltages corresponding nodes (31, 32, 33, ..., 34, And 35).

Each comparator 41, 42, 43,..., 44, and 45 has nodes 31, 32, 33,..., 34, and 35 corresponding to the analog input voltage Vin of the ADC 10. Compare the voltages and output the signal according to the comparison result.

The encoder 50 receives the output signals of each of the comparators 41, 42, 43,..., 44, and 45, encodes them and corresponds to the result N (eg, N = 6) bit digital signals ( DOUT).

2A is a graph showing conversion characteristics of an analog-to-digital converter without INL, and FIG. 2B is a graph showing conversion characteristics of an analog-to-digital converter having INL. 1 to 2B, resistors having substantially the same resistance value R are connected in series between the node 31 and the node 35.

2A constitutes a resistance ladder 20, in which case the resistance value of each of the plurality of resistors connected in series between the node 31 and the node 35 is the same (ie, the plurality of resistors connected in series). Conversion characteristics of the input / output voltage of the ADC 10 of each resistance value when there is no mismatch).

However, due to various causes in the process, mismatches occur in the resistance values of each of the plurality of resistors constituting the resistance ladder 20. Thus, a deviation (also called an 'offset') occurs in the voltage difference between two adjacent nodes 31 and 32, 32 and 33, 34 and 35. That is, when voltages across both resistors are different, input / output voltages of the ADC 10 do not maintain linearity as shown in FIG. 2B.

2B shows input / output voltage conversion characteristics of the ADC 10 having INL caused by mismatch of resistors. If there is a mismatch in the resistance value of each of the resistors, as shown in 2b, the integrated nonlinearity INL is greatest near 1/2 of the analog input voltage Vin. This is because the mismatches overlap. The INL has a problem of delaying the data processing speed of the ADC 10.

Accordingly, the technical problem to be achieved by the present invention is to provide a voltage generator circuit having a structure capable of reducing variations in voltage differences caused by mismatches in resistance values and an analog-to-digital converter having the voltage generator circuit.

The voltage generation circuit for achieving the above technical problem is provided with a voltage distribution circuit, a control current generation circuit, and a plurality of switches. The voltage divider circuit includes a first terminal for receiving a first reference voltage, a second terminal for receiving a second reference voltage, and a plurality of nodes, the voltage dividing circuit being configured to generate the divided voltages. The difference of the second reference voltage is divided, and each of the divided voltages is output through a corresponding node among the plurality of nodes. The control current generating circuit generates a control current based on an arithmetic mean voltage of the first reference voltage and the second reference voltage.

Each of the plurality of switches is connected between an output terminal of the current generating circuit and a corresponding node among the plurality of nodes, and at least one of the plurality of switches is switched in response to a corresponding control signal.

The control current generating circuit includes a voltage generator and a unit gain buffer. The voltage generator is connected between the first terminal and the second terminal, and outputs a voltage corresponding to the arithmetic mean voltage of the first reference voltage and the second reference voltage through an output terminal. The unit gain buffer buffers the voltage output from the output terminal of the voltage generator to generate the control current.

An analog to digital converter for achieving the above technical problem is provided with a voltage distribution circuit, a plurality of comparators, encoders, control circuits, and switching circuits. The voltage distribution circuit may include a first terminal for receiving a first reference voltage, a second terminal for receiving a second reference voltage, and a first reference voltage input to the first terminal and a first input terminal to the second terminal. And a plurality of nodes for outputting a plurality of voltages voltage-divided based on the two reference voltages. Each of the plurality of comparators compares an input voltage with a voltage output from a corresponding node among the plurality of nodes.

The encoder encodes the signals output from the plurality of comparators and outputs an N-bit digital signal. The control circuit outputs a control signal in response to an N-bit digital signal output from the encoder. The switching circuit supplies a control current input through an input terminal to a corresponding node among the plurality of nodes in response to a control signal output from the control circuit.

The analog-to-digital converter is connected between the first terminal and the second terminal, a voltage for generating an arithmetic mean voltage of the first reference voltage and the second reference voltage and outputs the generated arithmetic mean voltage through an output terminal. And a unit gain buffer for generating the control current by buffering the arithmetic mean voltage output from the generator and the output terminal of the voltage generator.

The control circuit includes a logic circuit, a digital analog converter, and a second switching circuit. The logic circuit generates the control signal, the second control signal, and the M-bit digital signal in response to the N-bit digital signal output from the encoder. The digital-to-analog converter generates an analog voltage in response to the M-bit digital signal. The second switching circuit outputs any one of an external input voltage input from the outside and an analog voltage output from the digital analog converter as the input voltage in response to the second control signal.

The control circuit includes a logic circuit, a first digital analog converter, a second switching circuit, a second digital analog converter, and a unit gain buffer. The logic circuit generates the control signal, the second control signal, the M bit digital signal, and the L bit digital signal in response to the N bit digital signal output from the encoder. The first digital to analog converter generates an analog voltage in response to the M-bit digital signal. The second switching circuit outputs any one of an external input voltage input from the outside and an analog voltage output from the first digital analog converter as the input voltage in response to the second control signal. The second digital to analog converter generates an analog voltage in response to the L-bit digital signal.

The unit gain buffer generates the control current in response to an analog voltage output from the second digital analog converter.

In order to achieve the above technical problem, a voltage generation method divides a difference between a first reference voltage input through a first terminal and a second reference voltage input through a second terminal into a plurality of voltages, and each of the divided voltages. Outputting a control current through a corresponding node among a plurality of nodes, and generating a control current based on an arithmetic mean voltage of the first reference voltage and the second reference voltage, each of which corresponds to a plurality of nodes. Supplying the control current to a corresponding one of the plurality of nodes through a switch that is on in response to a control signal among a plurality of switches connected to a node, and a level of each of the divided voltages And adjusting based on the control current.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 shows a circuit diagram of a voltage generating circuit according to an embodiment of the present invention. Referring to FIG. 3, the voltage generation circuit includes a voltage distribution circuit 110, a plurality of switches 151 to 155, and a control current generation circuit 157.

The voltage distribution circuit 110 may include a first terminal 101 for receiving a first reference voltage Vref1, a second terminal 103 for receiving a second reference voltage Vref2, and a plurality of nodes ( 111 to 117, and divides the difference between the first reference voltage Vref1 and the second reference voltage Vref2 input through the first terminal 101 at equal intervals, and divides each divided voltage DV1. To DV7) are output through corresponding nodes among the plurality of nodes 111 to 117.

The voltage distribution circuit 110 includes a plurality of resistors R1 to R8 connected in series, and the resistance values of the plurality of resistors R1 to R8 are the same, or the resistors R1 and R8. ) May be half of the resistance values of the remaining resistors R2 to R7, but is not limited thereto.

It is preferable that the resistance values of each of the plurality of resistors R1 to R8 are the same, but deviations occur in the resistance values of the resistors R1 to R8 due to various causes of the manufacturing process. Therefore, when the first reference voltage Vref1 is supplied to the first terminal 101 and the second reference voltage Vref2 is supplied to the second terminal 103, two adjacent nodes 111, 112, 113, and 114 are provided. , Deviations (or offsets) occur in voltage differences between 114 and 115, 116 and 117.

Each of the plurality of switches 151 to 155 is connected between the output terminal 156 of the control current generating circuit 157 and the corresponding node 112, 113, 114, 115, or 117, and the corresponding control signal. It is turned on / off in response to (SW1, SW2, SW3, SW4, SW5).

The control current generation circuit 157 generates a control current I3. The control current generating circuit 157 includes a voltage generator 160 and a unit gain buffer 170. The voltage generator 160 is connected between the first terminal 101 and the second terminal 103 so that the first reference voltage Vref1 and the second terminal 103 input through the first input terminal 101. Generates a third reference voltage (Vref1 + Vref2) / 2 corresponding to the arithmetic mean voltage of the second reference voltage Vref2 inputted through the second reference voltage Vref2, and generates the generated third reference voltage (Vref1 + Vref2) / 2. ) Is output through its output terminal.

The unit gain buffer 170 buffers the third reference voltage (Vref1 + Vref2) / 2 output from the output terminal of the voltage generator 160 and outputs the control current I3 according to the output terminal 156. Will output The unit gain buffer 170 generates an output voltage having the same level as that of the input voltage, and generates an output current having increased driving capability.

A method of reducing a deviation (or offset) in voltage differences between two adjacent nodes 111 and 112, 113 and 114, 114 and 115, 116 and 117 will now be described with reference to FIG. 3.

For convenience of explanation, the resistance values of the resistors R1 to R8 are preferably 10 Ω, but the resistors R1, R2, ..., R3, R4 connected to the first terminal 101 for various reasons of the manufacturing process. ) Is 10.1Ω, the resistances of the resistors R5, R6, ..., R7, R8 connected to the second terminal 103 are 9.9Ω, and the second terminal 101 is connected to the second. Assume that the current I1 = I2 flowing to the terminal 103 is 1A.

When the arithmetic mean voltage ((Vref1 + Vref2) / 2) of the first reference voltage Vref1 and the second reference voltage Vref2 is input to the (+) input terminal of the unit gain buffer 170, the unit gain buffer ( 170 buffers the arithmetic mean voltage (Vref1 + Vref2) / 2 to generate a control current I3.

If the switch 153 of the plurality of switches 151 to 155 is turned on in response to the switching control signal SW3, the control current I3 (eg, I3 = 0.01A) is transmitted to the node 114. Is supplied.

At this time, the current I1 flowing from the first terminal 101 to the node 114 decreases (for example, from 1A to 0.99A) under the influence of the control current I3, and from the node 114 to the second terminal 103. Since the current I2 flowing through) increases due to the influence of the control current I3 (for example, from 1A to 1.01A), the voltage difference between two adjacent nodes 113 and 114 and two adjacent nodes ( The deviation (or offset) of the voltage difference between 114 and 115 is significantly reduced (e.g., decreasing from 0.2V to 0.0V).

Even when the resistance values of the resistors R1 to R8 are different, when the control current I3 flows into the node 114, the control current I3 flows from the first terminal 101 to the node 114 under the influence of the control current I3. The current I1 decreases and the current I2 flowing from the node 114 to the second terminal 103 increases. Thus, the deviation of the voltage difference between two adjacent nodes 101 and 111, 111 and 112, 113 and 114, 114 and 115, 116 and 117, 117 and 103 of the voltage distribution circuit 110 is significantly reduced.

4 shows a circuit diagram of an analog to digital converter according to an embodiment of the present invention. Referring to FIG. 4, the analog-to-digital converter 100 includes a voltage distribution circuit 110, a plurality of comparisons 121 to 127, an encoder 130, a control circuit 140, and a switching circuit 150. .

The voltage distribution circuit 110 may include a first terminal 101 for receiving a first reference voltage Vref1, a second terminal 103 for receiving a second reference voltage Vref2, and the first terminal ( A plurality of nodes 111 to output a plurality of voltages divided by voltage based on the first reference voltage Vref1 inputted to 101 and the second reference voltage Vref2 inputted to the second terminal 103. 117).

Each of the plurality of comparisons 121 to 127 compares an analog input voltage (any one of Vin and Dvin) with voltages output from corresponding nodes among the plurality of nodes 111 to 117, and compares the result with the comparison result. The comparison signal is output to the encoder 130.

The encoder 130 encodes the signals output from the plurality of comparators 121 to 127 and outputs N (eg, N = 6) bit digital signals DOUT according to the result.

The control circuit 140 outputs at least one first control signal CTRL1 to the switching circuit 150 in response to the N-bit digital signal DOUT output from the encoder 130. The control circuit 140 based on the N-bit digital signal DOUT output from the encoder 130, two adjacent nodes 101 and 111, 111 and 112, 113 and 114, 114 and 115, 116 and 117 And monitoring the deviation of the voltage difference between 117 and 103 and outputting at least one first control signal CTRL1 to the switching circuit 150 to remove the deviation according to the result.

The control circuit 140 includes a digital logic circuit 141, a digital analog converter 143, and a switching circuit 145.

The digital logic circuit 141 has two nodes 101 and 111, 111 and 112,..., 113 and 114 in response to an N-bit (eg, 6-bit) digital signal DOUT output from the encoder 130. The first control signal CTRL1 and the analog-to-digital converter 100 correct the first control signal CTRL1 including a plurality of bits for eliminating the deviation of the voltage difference between the points 114, 115, ..., 116, 117, and 117, 103. The second control signal CTRL2 for controlling the switching operation of the switching circuit 145 for outputting the analog voltage DVin output from the digital analog converter 143 to each of the comparators 121 to 127 when performing the step, and Generates an M (M is a natural number) bit digital signal used as an input signal of the DAC 143. Therefore, each bit constituting the first control signal CTRL1 and each bit constituting the M bit digital signal used as an input signal of the DAC 143 are N bits (eg, 6) output from the encoder 130. Bit) can be varied in response to the digital signal DOUT.

The digital-to-analog converter 143 generates a predetermined analog voltage DVin in response to the M-bit digital signal output from the digital logic circuit 141.

The switching circuit 145 removes any one voltage Vin or DVin from the external input voltage Vin input from the outside of the ADC 100 and the analog voltage DVin output from the digital analog converter 143. It outputs to the (+) input terminal of each comparator 121-127 in response to 2 control signal CTRL2. Accordingly, each of the comparators 121 to 127 receives the voltages of the nodes 111 to 117 and the analog voltage DVin, compares them, and outputs a signal according to the comparison result. Accordingly, the encoder 130 receives the output signals of the comparators 121 to 127 and encodes the received signals, and as a result, outputs an N-bit (eg, 6-bit) digital signal DOUT to the digital logic circuit 141. do.

For example, when the analog-to-digital converter 100 performs calibration, the switching circuit 145 responds to the second control signal CTRL2 output from the digital logic circuit 141. The analog voltage DVin outputted from the output signal is output to the positive input terminal of each comparison 121 to 127.

The switching circuit 150 outputs a control current I3 input to the input terminal 156 from among the nodes 112 to 116 in response to the first control signal CTRL1 output from the control circuit 140. Supply to the corresponding node.

The switching circuit 150 includes a plurality of switches 151 to 155, wherein each of the switches 151 to 155 corresponds to an input terminal 156 and a plurality of nodes 112 to 116. It is connected between each node.

At least one of the switches 151 to 155 is connected to the input terminal 156 in response to the at least one first control signal CTRL1 output from the digital logic circuit 141 of the control circuit 140. The input control current I3 is supplied to the corresponding node among the plurality of nodes 112 to 116.

The analog to digital converter 100 further includes a voltage generator 160 and a unity gain buffer 170. The voltage generator 160 is connected between the first terminal 101 and the second terminal 103, and the first reference voltage Vref1 and the second terminal 103 input through the first terminal 101. Generates the arithmetic mean voltage ((Vref1 + Vref2) / 2) of the second reference voltage Vref2 inputted through), and generates the arithmetic mean voltage ((Vref1 + Vref2) / 2) through its output terminal. The unit gain buffer 170 outputs the unit gain buffer 170.

The unit gain buffer 170 buffers the arithmetic mean voltage (Vref1 + Vref2) / 2 output from the output terminal of the voltage generator 160 to generate the control current I3. The unit gain buffer 170 has a high DC gain, generates an output voltage having the same level as that of the input voltage, and performs a function of a current driver for increasing the driving capability of the output current I3.

5 is a circuit diagram of an analog-to-digital converter according to another embodiment of the present invention. Referring to FIG. 5, the analog-to-digital converter 200 includes a voltage distribution circuit 110, a plurality of comparisons 121 to 127, an encoder 130, a control circuit 210, and a switching circuit 150. .

The control circuit 210 accurately outputs a voltage corresponding to the arithmetic mean of the first reference voltage Vref1 and the second reference voltage Vref2 using the digital analog converter 217.

The control circuit 210 includes a digital logic circuit 211, a first digital analog converter 213, a second switching circuit 215, and a second digital analog converter 217.

The digital logic circuit 211 is configured to respond to the N-bit digital signal DOUT output from the encoder 130, the first control signal CTRL1, the second control signal CTRL2, the M-bit digital signal, and the L-bit digital signal. Generate a signal. Where N, M, and L are natural numbers.

The first digital-to-analog converter 213 generates an analog voltage DVin in response to the M-bit digital signal output from the digital logic circuit 211.

The second switching circuit 215 may include any one of the voltage Vin or the external analog input voltage Vin input from the outside of the ADC 200 and the analog voltage DVin output from the first digital analog converter 213. DVin is output to the positive input terminal of each of the comparators 121 to 127 in response to the second control signal CTRL2.

The second digital-to-analog converter 217 is an arithmetic mean of the first reference voltage Vref1 and the second reference voltage Vref2 in response to an L-bit digital signal including a plurality of bits output from the digital logic circuit 211. Generate an analog voltage ((Vref1 + Vref2) / 2) corresponding to the voltage.

The unit gain buffer 170 buffers the analog voltage (Vref1 + Vref2) / 2 output from the second digital-to-analog converter 217 to generate a control current I3 and output the generated control current I3. Supply to terminal 156.

FIG. 6 is a graph illustrating conversion characteristics with INL reduced by the analog-to-digital converter according to the present invention shown in FIGS. 4 and 5. A method of reducing INL will be briefly described with reference to FIGS. 3 to 6 as follows.

As described with reference to FIG. 3, the current I1 flowing from the first terminal 101 to the node 114 decreases under the influence of the control current I3 and from the node 114 to the second terminal 103. The flowing current I2 increases due to the influence of the control current I3, so that the deviation (offset, or INL) is the greatest, for example, above the node 114 and the node 114 to which the control current I3 is supplied. The deviation of the voltage difference between the nodes 113 and 115 below, i.e., two adjacent nodes 113 and 114, and the voltage difference between the two adjacent nodes 114 and 115, is significantly reduced.

In the voltage generation circuit and the analog-to-digital converter having the voltage generation circuit according to the present invention, the INL near the intermediate voltage of the input voltage Vin can be made almost '0', and thus the INL generated by each of the remaining resistors. Can also be improved.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the voltage generation circuit including the resistance ladder according to the present invention has the effect of reducing the variation in voltage differences between two adjacent nodes caused by mismatches in the resistance values of the resistors constituting the resistance ladder. .

In addition, as described above, the voltage generation circuit including the resistance ladder according to the present invention does not increase the size of each of the resistors in order to eliminate mismatches in the resistance values of the resistors constituting the resistance ladder. It is possible to reduce the deviation of the voltage differences between two adjacent nodes or the integrated nonlinearity caused by each of the stores.

Claims (16)

In the voltage generating circuit, A first terminal for receiving a first reference voltage, a second terminal for receiving a second reference voltage, and a plurality of nodes, the first reference voltage and the second reference voltage for generating divided voltages; A voltage distribution circuit for distributing a difference between and outputting each of the divided voltages through a corresponding node among the plurality of nodes; A control current generation circuit for generating a control current based on the third reference voltage; And Each having a plurality of switches connected between an output terminal of the current generating circuit and a corresponding one of the plurality of nodes, At least one of the plurality of switches is switched in response to a corresponding control signal. The voltage generation circuit of claim 1, wherein the third reference voltage is an arithmetic mean voltage between the first reference voltage and the second reference voltage. According to claim 1, wherein the control current generating circuit, The third terminal is connected between the first terminal and the second terminal, and generates the third reference voltage corresponding to the arithmetic mean voltage of the first reference voltage and the second reference voltage and outputs the generated third reference voltage. A voltage generator output through the; And And a unit gain buffer configured to generate the control current by buffering the third reference voltage output from the output terminal of the voltage generator. The voltage generation circuit of claim 1, wherein the level of each of the divided voltages is adjusted based on the control current. In the analog-to-digital converter, Based on a first terminal for receiving a first reference voltage, a second terminal for receiving a second reference voltage, and a first reference voltage input to the first terminal and a second reference voltage input to the second terminal A voltage distribution circuit having a plurality of nodes for outputting a plurality of voltage divided voltages; A plurality of comparators, each for comparing an input voltage with a voltage output from a corresponding one of the plurality of nodes; An encoder for encoding signals output from the plurality of comparators and outputting an N-bit digital signal; A control circuit outputting a control signal in response to an N-bit digital signal output from the encoder; And And a switching circuit for supplying a control current input through an input terminal to a corresponding node among the plurality of nodes in response to a control signal output from the control circuit. The method of claim 5, wherein the analog to digital converter, And a control current generating circuit for generating the control current based on the arithmetic mean voltage of the first reference voltage and the second reference voltage. The method of claim 5, wherein the analog to digital converter, A voltage generator connected between the first terminal and the second terminal, the voltage generator generating an arithmetic mean voltage of the first reference voltage and the second reference voltage and outputting the arithmetic mean voltage generated through an output terminal; And And a unit gain buffer for generating the control current by buffering the arithmetic mean voltage output from the output terminal of the voltage generator. The method of claim 5, wherein the voltage distribution circuit, A plurality of resistors connected in series between the first terminal and the second terminal, And wherein each of the plurality of nodes is a connection node of two corresponding resistors of the plurality of resistors. The method of claim 5, wherein the control circuit, A logic circuit for generating the control signal, the second control signal, and the M-bit digital signal in response to an N-bit digital signal output from the encoder; A digital analog converter for generating an analog voltage in response to the M-bit digital signal; And And a second switching circuit for outputting any one of an external input voltage input from the outside and an analog voltage output from the digital analog converter as the input voltage in response to the second control signal. Digital converter. The method of claim 5, wherein the switching circuit, Each having a plurality of switches connected between an input terminal of the switching circuit and a corresponding one of the plurality of nodes, Any one of said plurality of switches is on (on) in response to a control signal output from said control circuit. 6. The analog-to-digital converter according to claim 5, wherein the level of each of the plurality of voltage-divided voltages is adjusted based on the control current. The method of claim 5, wherein the control circuit, A logic circuit generating the control signal, the second control signal, the M bit digital signal, and the L bit digital signal in response to the N bit digital signal output from the encoder; A first digital analog converter for generating an analog voltage in response to the M-bit digital signal; A second switching circuit for outputting any one of an external input voltage input from the outside and an analog voltage output from the first digital analog converter as the input voltage in response to the second control signal; A second digital analog converter for generating an analog voltage in response to the L-bit digital signal; And And a current driver for generating the control current in response to the analog voltage output from the second digital analog converter. 13. The analog of claim 12, wherein the second digital analog converter generates the analog voltage corresponding to the arithmetic mean voltage of the first reference voltage and the second reference voltage in response to the L-bit digital signal. Digital converter. 13. The analog to digital converter of claim 12, wherein the current driver is a unity gain buffer. The method of claim 12, wherein the switching circuit, Each having a plurality of switches connected between an input terminal of the switching circuit and a corresponding one of the plurality of nodes, At least one of the plurality of switches is on (on) in response to a control signal output from the control circuit. In the voltage generation method, The difference between the first reference voltage input through the first terminal and the second reference voltage input through the second terminal is divided into a plurality of voltages, and each of the divided voltages is distributed through a corresponding node among the plurality of nodes. Outputting; Generating a control current based on an arithmetic mean voltage of the first reference voltage and the second reference voltage; Supplying the control current to a corresponding node among the plurality of nodes through a switch that is on in response to a control signal, among a plurality of switches each connected with a corresponding node among the plurality of nodes; ; And And adjusting the level of each of the divided voltages based on the control current.

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