KR100712981B1 - Method For Forming The Bit Line Of Semiconductor Device - Google Patents

Method For Forming The Bit Line Of Semiconductor Device Download PDF

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KR100712981B1
KR100712981B1 KR1020000077148A KR20000077148A KR100712981B1 KR 100712981 B1 KR100712981 B1 KR 100712981B1 KR 1020000077148 A KR1020000077148 A KR 1020000077148A KR 20000077148 A KR20000077148 A KR 20000077148A KR 100712981 B1 KR100712981 B1 KR 100712981B1
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bit line
forming
film
hard mask
semiconductor device
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KR20020046810A (en
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김상덕
박성기
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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Abstract

볼록형 결함의 발생을 방지하여 브릿지를 방지할 수 있는 반도체소자의 비트라인 형성방법은, 반도체기판 상에 비트라인 도전층을 형성하는 단계와, 비트라인 도전층 상에 하드마스크를 형성하는 단계와, 하드마스크 상에 HSQ(Hydrogen Silsesquioxane)막을 도포하여 평탄화층을 형성하는 단계, 및 평탄화층, 하드마스크 및 비트라인 도전층을 패터닝하는 단계를 포함하여 이루어진다.A method of forming a bit line of a semiconductor device capable of preventing bridges by preventing the occurrence of convex defects includes: forming a bit line conductive layer on a semiconductor substrate, forming a hard mask on the bit line conductive layer, Forming a planarization layer by applying an HSQ (Hydrogen Silsesquioxane) film on the hard mask, and patterning the planarization layer, the hard mask, and the bit line conductive layer.

텅스텐 비트라인, 볼록형 결함, HSQ막Tungsten Bitline, Convex Defects, HSQ Film

Description

반도체소자의 비트라인 형성방법 {Method For Forming The Bit Line Of Semiconductor Device} {Method For Forming The Bit Line Of Semiconductor Device}             

도 1a 내지 도 1c는 종래의 비트라인을 형성할 때, 볼록형 결함이 형성되는 상태를 보인 도면이고,1A to 1C are views showing a state in which convex defects are formed when forming a conventional bit line,

도 2a 내지 도 2d는 본 발명에 따른 볼록형 결함을 제거하면서 비트라인을 형성하는 공정을 순차적으로 보인 도면이고,2A to 2D are views sequentially showing a process of forming a bit line while removing convex defects according to the present invention;

도 3은 일반적인 비트라인에 볼록형 결함이 형성된 상태를 보인 사진이다. 3 is a photograph showing a state in which convex defects are formed in a general bit line.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

110 : 반도체기판 115 : 비트라인110: semiconductor substrate 115: bit line

120 : 제1볼록형결함 125 : 하드마스크120: first convex defect 125: hard mask

130 : 제2볼록형결함 135 : HSQ막130: second convex defect 135: HSQ film

140 : 반사방지막140: antireflection film

본 발명은 비트라인을 형성하는 방법에 관한 것으로서, 특히, 볼록형 결함의 발생을 방지하여 소자의 전기적인 특성 저하를 방지하도록 하는 반도체소자의 비트라인 형성방법에 관한 것이다.
일반적으로, 반도체소자가 점차적으로 고집적화되면서, 배선층이나 절연층 등을 적층하고 식각하는 과정에서 미세한 오차로 인하여 도전물질이 제거되어야 하는 부분에서 제대로 제거되지 못하여 전기적인 단락(Short)을 유발시키는 브릿지(Bridge)를 유발하게 된다. The present invention relates to a method for forming a bit line, and more particularly, to a method for forming a bit line of a semiconductor device to prevent the occurrence of convex defects to prevent the deterioration of electrical characteristics of the device.
In general, as semiconductor devices are gradually integrated, bridges that cause electrical shorts due to minute errors in the process of stacking and etching wiring layers or insulating layers, etc., may not be properly removed from areas where conductive materials should be removed. Bridge).

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도 1a 내지 도 1d 종래의 비트라인 형성방법을 순차적으로 보인 도면이다. 1A to 1D are diagrams sequentially illustrating a conventional bit line forming method.

도 1a에 도시된 바와 같이, 반도체기판(1) 상에 텅스텐 등과 같은 도전층으로 비트라인(15)을 적층한다. 이때, 상기 비트라인(15)으로서 텅스텐층을 주로 사용하는 경우, 폴리실리콘층에 비하여 표면이 거칠다는 특징을 지닌 것으로서, 비트라인(15)의 상부면에 작은 크기의 제1 볼록형 결함(20)이 형성된다.As shown in FIG. 1A, the bit lines 15 are stacked on the semiconductor substrate 1 with a conductive layer such as tungsten. In this case, when the tungsten layer is mainly used as the bit line 15, the surface is rougher than the polysilicon layer, and the first convex defect 20 having a small size is formed on the upper surface of the bit line 15. Is formed.

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도 1b에 도시된 바와 같이, 상기 결과물 상에 하드마스크(25)를 적층한다. 이때, 상기 하드마스크(25) 상에는 상기 제1 볼록형 결함(20)으로 인하여 더욱 크기가 증폭된 제2 볼록형 결함(20)이 형성된다.As shown in FIG. 1B, a hard mask 25 is stacked on the resultant. In this case, a second convex defect 20 is further formed on the hard mask 25 due to the first convex defect 20.

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도 1c에 도시된 바와 같이, 상기 결과물 상에 반사방지막(40)을 적층하는 경우, 상기 제2 볼록형 결함(30)에 비하여 그 크기가 더욱 커진 제3 볼록형 결함(40)이 형성된다.As shown in FIG. 1C, when the anti-reflection film 40 is stacked on the resultant, a third convex defect 40 having a larger size than the second convex defect 30 is formed.

도 3은 일반적인 비트라인에 볼록형결함이 형성된 상태를 보인 사진이다. 3 is a photograph showing a convex defect formed on a general bit line.

그런데, 상기한 바와 같이, 반도체기판 상에 비트라인을 적층할 때, 상부면에 형성된 볼록형 결함부위에 의하여 상기 비트라인의 상부면에 적층되는 하드마스크의 상부면에는 큰 볼록형결함이 형성되고, 이 결함으로 인하여 그 상부면에 적층되는 반사방지막에는 상당하게 큰 결함부위가 형성되어지므로 후속공정에서 브릿지(Bridge)를 유발하여 소자의 전기적인 특성을 악화시키는 문제점을 지닌다.As described above, when the bit lines are stacked on the semiconductor substrate, a large convex defect is formed on the upper surface of the hard mask stacked on the upper surface of the bit line by the convex defect portion formed on the upper surface. Due to the defect, since the antireflection film laminated on the upper surface is formed with a relatively large defect, there is a problem of deteriorating the electrical characteristics of the device by causing a bridge in a subsequent process.

본 발명이 이루고자 하는 기술적 과제는 반도체기판 상에 비트라인을 적층할 때, 하드마스크 상에 HSQ 막을 적층하여 표면의 균일도를 증가시켜 볼록형 결함을 방지함으로써 브릿지를 예방하여 소자의 전기적인 특성 저하를 방지하는 반도체소자의 비트라인 형성방법을 제공하는 것이다.The technical problem to be achieved by the present invention, when stacking the bit line on the semiconductor substrate, by stacking the HSQ film on the hard mask to increase the uniformity of the surface to prevent convex defects to prevent the bridge to reduce the electrical characteristics of the device To provide a bit line forming method of a semiconductor device.

상기 기술적 과제를 이루기 위하여 본 발명에 의한 반도체소자의 비트라인 형성방법은, 반도체기판 상에 비트라인 도전층을 형성하는 단계; 상기 비트라인 도전층 상에 하드마스크를 형성하는 단계; 상기 하드마스크 상에 HSQ(Hydrogen Silsesquioxane)막을 도포하여 평탄화층을 형성하는 단계; 및 상기 평탄화층, 하드마스크 및 비트라인 도전층을 패터닝하는 단계를 포함하는 것을 특징으로 한다.
상기 비트라인은 텅스텐막을 PE-CVD 방법으로 600 ∼ 1000Å의 두께로 증착하여 형성할 수 있다.
상기 하드마스크는 실리콘질화막을 PE-CVD법으로 1200 ∼ 2000Å의 두께로 증착하여 형성할 수 있다.
상기 HSQ막을 형성할 때, SOG(Spin On Glass) 코팅법으로 형성하고, 웨이퍼의 회전속도는 3000 ∼ 10000rpm인 것이 바람직하다. 상기 HSQ막을 형성한 후, 상기 HSQ막을 열처리하는 단계를 더 진행할 수도 있다.
상기 반사방지막은 PECVD 방법으로 SiOXNY 막을 증착하여 형성할 수 있다.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 일실시예에 대해 상세하게 설명하고자 한다.According to an aspect of the present invention, there is provided a method of forming a bit line of a semiconductor device, the method including: forming a bit line conductive layer on a semiconductor substrate; Forming a hard mask on the bit line conductive layer; Forming a planarization layer by applying a hydrogen silsesquioxane (HSQ) film on the hard mask; And patterning the planarization layer, the hard mask, and the bit line conductive layer.
The bit line may be formed by depositing a tungsten film to a thickness of 600 to 1000 Å by PE-CVD.
The hard mask may be formed by depositing a silicon nitride film to a thickness of 1200 to 2000 GPa by PE-CVD.
When the HSQ film is formed, it is preferably formed by a spin on glass (SOG) coating method, and the rotation speed of the wafer is preferably 3000 to 10000 rpm. After forming the HSQ film, the step of heat-treating the HSQ film may be further performed.
The anti-reflection film may be formed by depositing a SiO X N Y film by PECVD.
Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

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도 2a 내지 도 2d는 본 발명에 따른 볼록형 결함을 제거하면서 비트라인을 형성하는 공정을 순차적으로 보인 단면도들이다.2A through 2D are cross-sectional views sequentially illustrating a process of forming a bit line while removing convex defects according to the present invention.

도 2a에 도시된 바와 같이, 트랜지스터 등 하부 소자가 형성되어 있는 반도체기판(110) 상에 텅스텐(W) 등과 같은 도전물질을 증착하여 비트라인 도전층(115)을 형성한다. 상기 비트라인 도전층(115)은, 텅스텐(W)을 플라즈마 인핸스드 화학기상증착(Plasma Enhanced Chemical Vapor Deposition; PE-CVD) 방법으로 600 ∼ 1000Å의 두께로 증착하여 형성한다. 이때, 텅스텐막의 증착특성상 상기 비트라인 도전층(115)의 상부 표면에는 제1 볼록형 결함(120)이 형성된다.As illustrated in FIG. 2A, a bit line conductive layer 115 is formed by depositing a conductive material such as tungsten (W) on a semiconductor substrate 110 on which a lower element such as a transistor is formed. The bit line conductive layer 115 is formed by depositing tungsten (W) to a thickness of 600 to 1000 kPa by a plasma enhanced chemical vapor deposition (PE-CVD) method. At this time, the first convex defect 120 is formed on the upper surface of the bit line conductive layer 115 due to the deposition characteristic of the tungsten film.

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도 2b에 도시된 바와 같이, 상기 비트라인 도전층(115) 상에 하드마스크(125)를 형성한다. 이때, 상기 제1 볼록형 결함(120)의 영향을 받아서 상기 하드마스크(125) 상에는 제1 볼록형 결함(120)보다 그 크기가 커진 제2 볼록형 결함(130)이 형성된다.As shown in FIG. 2B, a hard mask 125 is formed on the bit line conductive layer 115. At this time, the second convex defect 130 having a larger size than the first convex defect 120 is formed on the hard mask 125 under the influence of the first convex defect 120.

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상기 하드마스크(125)는, 실리콘질화막을 PE-CVD 방법을 사용하여 1200 ∼ 2000Å의 두께로 증착하여 형성하고, 상기 실리콘질화막의 굴절율은 1.95 ∼ 2.02인 것이 바람직하다.The hard mask 125 is formed by depositing a silicon nitride film to a thickness of 1200 to 2000 GPa using a PE-CVD method, and the refractive index of the silicon nitride film is preferably 1.95 to 2.02.

도 2c에 도시된 바와 같이, 상기 하드마스크(125) 상의 제2 볼록형 결함(130)에 의한 표면 거칠기를 제거하기 위하여 균일한 도포 능력이 뛰어난 HSQ(Hydrogen Silsesquioxane) 막(135)을 형성하면, 제2 볼록형 결함(130)의 파장이 증폭되는 것을 방지하여 결과면이 평탄하게 된다.As shown in FIG. 2C, when the HSQ (Hydrogen Silsesquioxane) film 135 having excellent uniformity of application is formed to remove surface roughness caused by the second convex defect 130 on the hard mask 125, The wavelength of the two convex defects 130 is prevented from being amplified so that the resultant surface becomes flat.

상기 HSQ막(135)은 SOG(Spin On Glass) 코팅법으로 증착하는데, 코팅시 웨이퍼의 회전속도는 3000 ∼ 10000rpm의 범위로 한다.The HSQ film 135 is deposited by SOG (Spin On Glass) coating, and the rotation speed of the wafer during coating is in the range of 3000 to 10000 rpm.

한편, 상기 HSQ막(135)을 증착한 후, 열처리 공정을 더 진행하면 HSQ막(135) 내의 오가닉(organic) 기의 분해 및 탈착을 유발하여 막의 평탄화를 이룰 수 있다.On the other hand, after the deposition of the HSQ film 135, further heat treatment process may cause the organic groups in the HSQ film 135 to decompose and desorption to achieve a planarization of the film.

도 2d에 도시된 바와 같이, 상기 HSQ막(135) 상에 반사방지막(140)을 형성한다. 상기 반사방지막(140)은 PE-CVD 방법을 사용하여 실리콘산화질화막(SiOXNY)을 300 ∼ 600Å 두께로 증착하여 형성하며, 막의 굴절율은 1.89 ∼ 1.92 범위로 하여 형성한다. 계속해서, 도시되지는 않았지만, 사진식각 공정을 사용하여 상기 반사방지막, HSQ막, 하드마스크 및 비트라인 도전층을 차례로 패터닝하여 비트라인을 형성한다.As shown in FIG. 2D, an antireflection film 140 is formed on the HSQ film 135. The anti-reflection film 140 is formed by depositing a silicon oxynitride film (SiO X N Y ) to a thickness of 300 to 600 Pa by using a PE-CVD method, and the refractive index of the film is formed to be in the range of 1.89 to 1.92. Subsequently, although not shown, the anti-reflection film, the HSQ film, the hard mask, and the bit line conductive layer are sequentially patterned using a photolithography process to form bit lines.

삭제delete

상기한 바와 같이, 본 발명에 따른 반도체소자의 비트라인 형성방법에 의하면, 볼록형 결함부위를 포함하는 하드마스크 상에 표면이 평탄한 HSQ막을 형성함으로써, 상기 볼록형 결함에 의한 표면 거칠기를 제거할 수 있다. 따라서, 브릿지를 예방하여 소자의 전기적인 특성을 저하를 방지할 수 있다.As described above, according to the method for forming a bit line of a semiconductor device according to the present invention, the surface roughness caused by the convex defect can be removed by forming the HSQ film having a flat surface on the hard mask including the convex defect portion. Therefore, it is possible to prevent the bridge from being lowered in the electrical characteristics of the device.

Claims (6)

반도체기판 상에 비트라인 도전층을 형성하는 단계;Forming a bit line conductive layer on the semiconductor substrate; 상기 비트라인 도전층 상에 하드마스크를 형성하는 단계;Forming a hard mask on the bit line conductive layer; 상기 하드마스크 상에, HSQ(Hydrogen Silsesquioxane)막을 도포하여 평탄화층을 형성하는 단계; 및Forming a planarization layer by applying a hydrogen silsesquioxane (HSQ) film on the hard mask; And 상기 평탄화층, 하드마스크 및 비트라인 도전층을 패터닝하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 비트라인 형성방법.And patterning the planarization layer, hard mask, and bit line conductive layer. 제1항에 있어서, 상기 비트라인은,The method of claim 1, wherein the bit line, 텅스텐막을 PE-CVD 방법으로 600 ∼ 1000Å의 두께로 증착하여 형성하는 것을 특징으로 하는 반도체소자의 비트라인 형성방법.A method of forming a bit line in a semiconductor device, characterized by depositing a tungsten film with a thickness of 600 to 1000 GPa by PE-CVD. 제1항에 있어서, 상기 하드마스크는,The method of claim 1, wherein the hard mask, 실리콘질화막을 PE-CVD법으로 1200 ∼ 2000Å의 두께로 증착하여 형성하는 것을 특징으로 하는 반도체소자의 비트라인 형성방법.A method for forming a bit line in a semiconductor device, characterized by depositing a silicon nitride film to a thickness of 1200 to 2000 GPa by PE-CVD. 제1항에 있어서, The method of claim 1, 상기 HSQ막을 형성할 때, SOG(Spin On Glass) 코팅법으로 형성하고, 웨이퍼의 회전속도는 3000 ∼ 10000rpm인 것을 특징으로 하는 반도체소자의 비트라인 형성방법.When the HSQ film is formed, it is formed by a spin on glass (SOG) coating method, and the rotational speed of the wafer is 3000 ~ 10000rpm, characterized in that the bit line forming method of a semiconductor device. 제1항 또는 제4항에 있어서, The method according to claim 1 or 4, 상기 HSQ막을 형성한 후, 상기 HSQ막을 열처리하는 단계를 더 진행하는 것을 특징으로 하는 반도체소자의 비트라인 형성방법.And forming a heat treatment of the HSQ film after forming the HSQ film. 제1항에 있어서,The method of claim 1, 상기 반사방지막은 PE-CVD 방법으로 SiOXNY 막을 증착하여 형성하는 것을 특징으로 하는 반도체소자의 비트라인 형성방법.The anti-reflection film is a bit line forming method of a semiconductor device, characterized in that formed by depositing a SiO X N Y film by a PE-CVD method.
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KR940016532A (en) * 1992-12-12 1994-07-23 김주용 Minimal surface defect removal method of interlayer insulation layer (BPSG)
KR960002075A (en) * 1994-06-07 1996-01-26 에취.더블유. 한네만 Printing device of digital image data
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KR940016532A (en) * 1992-12-12 1994-07-23 김주용 Minimal surface defect removal method of interlayer insulation layer (BPSG)
KR960002075A (en) * 1994-06-07 1996-01-26 에취.더블유. 한네만 Printing device of digital image data
KR100354442B1 (en) * 2000-12-11 2002-09-28 삼성전자 주식회사 Method of forming spin on glass type insulation layer

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